Ignore:
Timestamp:
Oct 15, 2014, 11:41:49 AM (8 years ago)
Author:
meunier
Message:

Trunk:

  • Cosmetic in mem_cache_directory.h and xram_transaction.h
  • Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
  • Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py
File:
1 edited

Legend:

Unmodified
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  • trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd

    r779 r836  
    3232                memc_cell_size_int = parameter.Reference('vci_data_width_int'),
    3333                memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
    34                 dspin_in_width  = parameter.Reference('dspin_rsp_width'),
    35                 dspin_out_width = parameter.Reference('dspin_cmd_width')),
     34                memc_dspin_in_width  = parameter.Reference('dspin_rsp_width'),
     35                memc_dspin_out_width = parameter.Reference('dspin_cmd_width')),
    3636
    3737        Uses('caba:vci_simple_rom',
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