Changeset 247 for trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
- Timestamp:
- Aug 8, 2012, 12:03:25 PM (12 years ago)
- File:
-
- 1 edited
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trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
r234 r247 14 14 size_t y_id, 15 15 size_t cluster_id, 16 const 17 const 18 const 16 const soclib::common::MappingTable &mtd, 17 const soclib::common::MappingTable &mtc, 18 const soclib::common::MappingTable &mtx, 19 19 size_t x_width, 20 20 size_t y_width, 21 size_t 22 size_t 23 size_t 24 size_t 25 size_t 26 size_t 27 size_t 28 size_t 29 size_t 30 size_t 31 size_t 32 size_t 33 size_t 34 size_t 21 size_t tgtid_memc, 22 size_t tgtid_xicu, 23 size_t tgtid_fbuf, 24 size_t tgtid_mtty, 25 size_t tgtid_brom, 26 size_t tgtid_bdev, 27 size_t tgtid_mdma, 28 size_t memc_ways, 29 size_t memc_sets, 30 size_t l1_i_ways, 31 size_t l1_i_sets, 32 size_t l1_d_ways, 33 size_t l1_d_sets, 34 size_t xram_latency, 35 35 bool io, 36 size_t 37 size_t 38 char* 39 size_t 36 size_t xfb, 37 size_t yfb, 38 char* disk_name, 39 size_t block_size, 40 40 const Loader &loader, 41 uint32_t 42 uint32_t 41 uint32_t frozen_cycles, 42 uint32_t debug_start_cycle, 43 43 bool debug_ok) 44 44 : soclib::caba::BaseModule(insname), … … 55 55 signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"), 56 56 57 58 57 signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"), 58 signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"), 59 59 60 60 signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"), … … 86 86 87 87 // on coherence network : local srcid[proc] in [0...nprocs-1] 88 88 // on coherence network : local srcid[memc] = nprocs 89 89 90 90 std::cout << " - building proc_" << x_id << "_" << y_id << "-*" << std::endl; … … 97 97 sproc.str().c_str(), 98 98 cluster_id*nprocs + p, 99 mtd, // Mapping Table Direct 100 mtc, // Mapping Table Coherence 101 IntTab(cluster_id,p), // SRCID_D 102 IntTab(cluster_id,p), // SRCID_C 103 IntTab(cluster_id,p), // TGTID_C 104 8, // ITLB ways 105 8, // ITLB sets 106 8, // DTLB ways 107 8, // DTLB sets 108 l1_i_ways,l1_i_sets,16, // ICACHE size 109 l1_d_ways,l1_d_sets,16, // DCACHE size 110 4, // WBUF width 111 4, // WBUF depth 112 frozen_cycles, // max frozen cycles 99 mtd, // Mapping Table Direct 100 mtc, // Mapping Table Coherence 101 IntTab(cluster_id,p), // SRCID_D 102 IntTab(cluster_id,p), // SRCID_C 103 IntTab(cluster_id,p), // TGTID_C 104 8, // ITLB ways 105 8, // ITLB sets 106 8, // DTLB ways 107 8, // DTLB sets 108 l1_i_ways,l1_i_sets,16, // ICACHE size 109 l1_d_ways,l1_d_sets,16, // DCACHE size 110 4, // WBUF width 111 4, // WBUF depth 112 x_width, // X Width 113 y_width, // Y Width 114 nprocs, // Memory Cache Local Id (coherence) 115 frozen_cycles, // max frozen cycles 113 116 debug_start_cycle, 114 117 debug_ok); … … 122 125 smemc.str().c_str(), 123 126 mtd, mtc, mtx, 124 IntTab(cluster_id), 125 IntTab(cluster_id, nprocs), 126 IntTab(cluster_id, tgtid_memc), 127 IntTab(cluster_id, nprocs), 128 memc_ways, memc_sets, 16, 129 4096, 130 8, 131 8, 127 IntTab(cluster_id), // SRCID_X 128 IntTab(cluster_id, nprocs), // SRCID_C 129 IntTab(cluster_id, tgtid_memc), // TGTID_D 130 IntTab(cluster_id, nprocs), // TGTID_C 131 memc_ways, memc_sets, 16, // CACHE SIZE 132 4096, // HEAP SIZE 133 8, // TRANSACTION TABLE DEPTH 134 8, // UPDATE TABLE DEPTH 132 135 debug_start_cycle, 133 136 debug_ok); … … 147 150 std::cout << " - building xicu_" << x_id << "_" << y_id << std::endl; 148 151 149 size_t nhwi = 4; 150 if( io == true ) nhwi = 9; 152 size_t nhwi = 4; // always 4 (or 9) ports, even if 153 if( io == true ) nhwi = 9; // there if less than 4 processors 151 154 std::ostringstream sicu; 152 155 sicu << "xicu_" << x_id << "_" << y_id; 153 156 xicu = new VciXicu<vci_param>( 154 157 sicu.str().c_str(), 155 mtd, 156 IntTab(cluster_id, tgtid_xicu), 157 0, 158 nhwi, 159 0, 160 nprocs); 158 mtd, // mapping table 159 IntTab(cluster_id, tgtid_xicu), // TGTID_D 160 0, // number of timer IRQs 161 nhwi, // number of hard IRQs 162 0, // number of soft IRQs 163 nprocs); // number of output IRQs 161 164 162 165 std::cout << " - building dma_" << x_id << "_" << y_id << std::endl; … … 168 171 sdma.str().c_str(), 169 172 mtd, 170 IntTab(cluster_id, nprocs), 171 IntTab(cluster_id, tgtid_mdma), 172 64, 173 nprocs); 173 IntTab(cluster_id, nprocs), // SRCID 174 IntTab(cluster_id, tgtid_mdma), // TGTID 175 64, // burst size 176 nprocs); // number of IRQs 174 177 175 178 std::cout << " - building xbard_" << x_id << "_" << y_id << std::endl; … … 182 185 nb_direct_initiators = nprocs + 2; 183 186 nb_direct_targets = 7; 184 187 } 185 188 std::ostringstream sd; 186 189 sd << "xbard_" << x_id << "_" << y_id; … … 188 191 sd.str().c_str(), 189 192 mtd, 190 IntTab(cluster_id), 191 IntTab(cluster_id), 192 nb_direct_initiators, 193 nb_direct_targets); 193 IntTab(cluster_id), // cluster initiator index 194 IntTab(cluster_id), // cluster target index 195 nb_direct_initiators, // number of initiators 196 nb_direct_targets); // number of targets 194 197 195 198 std::cout << " - building xbarc_" << x_id << "_" << y_id << std::endl; … … 201 204 sc.str().c_str(), 202 205 mtc, 203 IntTab(cluster_id), 204 IntTab(cluster_id), 205 nprocs + 1, 206 nprocs + 1); 206 IntTab(cluster_id), // cluster initiator index 207 IntTab(cluster_id), // cluster target index 208 nprocs + 1, // number of initiators 209 nprocs + 1); // number of targets 207 210 208 211 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; … … 213 216 iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 214 217 wid.str().c_str(), 215 4, 216 4); 218 4, // cmd fifo depth 219 4); // rsp fifo depth 217 220 218 221 // direct target wrapper … … 221 224 tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 222 225 wtd.str().c_str(), 223 4, 224 4); 226 4, // cmd fifo depth 227 4); // rsp fifo depth 225 228 226 229 // coherence initiator wrapper … … 229 232 iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>( 230 233 wic.str().c_str(), 231 4, 232 4); 234 4, // cmd fifo depth 235 4); // rsp fifo depth 233 236 234 237 // coherence target wrapper … … 237 240 tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>( 238 241 wtc.str().c_str(), 239 4, 240 4); 242 4, // cmd fifo depth 243 4); // rsp fifo depth 241 244 242 245 std::cout << " - building cmdrouter_" << x_id << "_" << y_id << std::endl; … … 264 267 // IO cluster components 265 268 if ( io == true ) 266 269 { 267 270 brom = new VciSimpleRam<vci_param>( 268 271 "brom", … … 275 278 IntTab(cluster_id, tgtid_fbuf), 276 279 mtd, 277 280 xfb, yfb); 278 281 279 282 bdev = new VciBlockDeviceTsarV4<vci_param>( … … 290 293 mtd, 291 294 "tty0", "tty1", "tty2", "tty3", NULL); 292 295 } 293 296 294 297 std::cout << " - all components constructed" << std::endl; … … 299 302 300 303 // CMDROUTER and RSPROUTER 301 cmdrouter->p_clk 302 cmdrouter->p_resetn 303 rsprouter->p_clk 304 rsprouter->p_resetn 304 cmdrouter->p_clk (this->p_clk); 305 cmdrouter->p_resetn (this->p_resetn); 306 rsprouter->p_clk (this->p_clk); 307 rsprouter->p_resetn (this->p_resetn); 305 308 for(int x = 0; x < 2; x++) 306 309 { … … 314 317 } 315 318 316 cmdrouter->p_out[0][4] 317 cmdrouter->p_out[1][4] 318 cmdrouter->p_in[0][4] 319 cmdrouter->p_in[1][4] 320 321 rsprouter->p_out[0][4] 322 rsprouter->p_out[1][4] 323 rsprouter->p_in[0][4] 324 rsprouter->p_in[1][4] 319 cmdrouter->p_out[0][4] (signal_dspin_cmd_g2l_d); 320 cmdrouter->p_out[1][4] (signal_dspin_cmd_g2l_c); 321 cmdrouter->p_in[0][4] (signal_dspin_cmd_l2g_d); 322 cmdrouter->p_in[1][4] (signal_dspin_cmd_l2g_c); 323 324 rsprouter->p_out[0][4] (signal_dspin_rsp_g2l_d); 325 rsprouter->p_out[1][4] (signal_dspin_rsp_g2l_c); 326 rsprouter->p_in[0][4] (signal_dspin_rsp_l2g_d); 327 rsprouter->p_in[1][4] (signal_dspin_rsp_l2g_c); 325 328 326 329 // VCI/DSPIN WRAPPERS 327 iniwrapperd->p_clk 328 iniwrapperd->p_resetn 329 iniwrapperd->p_vci(signal_vci_l2g_d);330 iniwrapperd->p_dspin_out(signal_dspin_cmd_l2g_d);331 iniwrapperd->p_dspin_in(signal_dspin_rsp_g2l_d);332 333 tgtwrapperd->p_clk 334 tgtwrapperd->p_resetn 335 tgtwrapperd->p_vci(signal_vci_g2l_d);336 tgtwrapperd->p_dspin_out(signal_dspin_rsp_l2g_d);337 tgtwrapperd->p_dspin_in(signal_dspin_cmd_g2l_d);338 339 iniwrapperc->p_clk 340 iniwrapperc->p_resetn 341 iniwrapperc->p_vci(signal_vci_l2g_c);342 iniwrapperc->p_dspin_out(signal_dspin_cmd_l2g_c);343 iniwrapperc->p_dspin_in(signal_dspin_rsp_g2l_c);344 345 tgtwrapperc->p_clk 346 tgtwrapperc->p_resetn 347 tgtwrapperc->p_vci(signal_vci_g2l_c);348 tgtwrapperc->p_dspin_out(signal_dspin_rsp_l2g_c);349 tgtwrapperc->p_dspin_in(signal_dspin_cmd_g2l_c);330 iniwrapperd->p_clk (this->p_clk); 331 iniwrapperd->p_resetn (this->p_resetn); 332 iniwrapperd->p_vci (signal_vci_l2g_d); 333 iniwrapperd->p_dspin_out (signal_dspin_cmd_l2g_d); 334 iniwrapperd->p_dspin_in (signal_dspin_rsp_g2l_d); 335 336 tgtwrapperd->p_clk (this->p_clk); 337 tgtwrapperd->p_resetn (this->p_resetn); 338 tgtwrapperd->p_vci (signal_vci_g2l_d); 339 tgtwrapperd->p_dspin_out (signal_dspin_rsp_l2g_d); 340 tgtwrapperd->p_dspin_in (signal_dspin_cmd_g2l_d); 341 342 iniwrapperc->p_clk (this->p_clk); 343 iniwrapperc->p_resetn (this->p_resetn); 344 iniwrapperc->p_vci (signal_vci_l2g_c); 345 iniwrapperc->p_dspin_out (signal_dspin_cmd_l2g_c); 346 iniwrapperc->p_dspin_in (signal_dspin_rsp_g2l_c); 347 348 tgtwrapperc->p_clk (this->p_clk); 349 tgtwrapperc->p_resetn (this->p_resetn); 350 tgtwrapperc->p_vci (signal_vci_g2l_c); 351 tgtwrapperc->p_dspin_out (signal_dspin_rsp_l2g_c); 352 tgtwrapperc->p_dspin_in (signal_dspin_cmd_g2l_c); 350 353 351 354 // CROSSBAR direct 352 xbard->p_clk 353 xbard->p_resetn 354 xbard->p_initiator_to_up 355 xbard->p_target_to_up 355 xbard->p_clk (this->p_clk); 356 xbard->p_resetn (this->p_resetn); 357 xbard->p_initiator_to_up (signal_vci_l2g_d); 358 xbard->p_target_to_up (signal_vci_g2l_d); 356 359 357 xbard->p_to_target[tgtid_memc] 358 xbard->p_to_target[tgtid_xicu] 359 xbard->p_to_target[tgtid_mdma] 360 xbard->p_to_target[tgtid_memc] (signal_vci_tgt_d_memc); 361 xbard->p_to_target[tgtid_xicu] (signal_vci_tgt_d_xicu); 362 xbard->p_to_target[tgtid_mdma] (signal_vci_tgt_d_mdma); 360 363 361 xbard->p_to_initiator[nprocs] 364 xbard->p_to_initiator[nprocs] (signal_vci_ini_d_mdma); 362 365 363 366 for ( size_t p=0 ; p<nprocs ; p++) 364 367 { 365 xbard->p_to_initiator[p] 366 } 367 368 369 370 xbard->p_to_target[tgtid_mtty] 371 xbard->p_to_target[tgtid_brom] 372 xbard->p_to_target[tgtid_bdev] 373 xbard->p_to_target[tgtid_fbuf] 368 xbard->p_to_initiator[p] (signal_vci_ini_d_proc[p]); 369 } 370 371 if ( io == true ) 372 { 373 xbard->p_to_target[tgtid_mtty] (signal_vci_tgt_d_mtty); 374 xbard->p_to_target[tgtid_brom] (signal_vci_tgt_d_brom); 375 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 376 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 374 377 375 xbard->p_to_initiator[nprocs+1] 376 378 xbard->p_to_initiator[nprocs+1] (signal_vci_ini_d_bdev); 379 } 377 380 378 381 // CROSSBAR coherence 379 xbarc->p_clk 380 xbarc->p_resetn 381 xbarc->p_initiator_to_up 382 xbarc->p_target_to_up 383 xbarc->p_to_initiator[nprocs] 384 xbarc->p_to_target[nprocs] 382 xbarc->p_clk (this->p_clk); 383 xbarc->p_resetn (this->p_resetn); 384 xbarc->p_initiator_to_up (signal_vci_l2g_c); 385 xbarc->p_target_to_up (signal_vci_g2l_c); 386 xbarc->p_to_initiator[nprocs] (signal_vci_ini_c_memc); 387 xbarc->p_to_target[nprocs] (signal_vci_tgt_c_memc); 385 388 for ( size_t p=0 ; p<nprocs ; p++) 386 389 { 387 xbarc->p_to_target[p] 388 xbarc->p_to_initiator[p] 390 xbarc->p_to_target[p] (signal_vci_tgt_c_proc[p]); 391 xbarc->p_to_initiator[p] (signal_vci_ini_c_proc[p]); 389 392 } 390 393 … … 392 395 for ( size_t p=0 ; p<nprocs ; p++) 393 396 { 394 proc[p]->p_clk 395 proc[p]->p_resetn 396 proc[p]->p_vci_ini_d 397 proc[p]->p_vci_ini_c 398 proc[p]->p_vci_tgt_c 399 proc[p]->p_irq[0] 397 proc[p]->p_clk (this->p_clk); 398 proc[p]->p_resetn (this->p_resetn); 399 proc[p]->p_vci_ini_d (signal_vci_ini_d_proc[p]); 400 proc[p]->p_vci_ini_c (signal_vci_ini_c_proc[p]); 401 proc[p]->p_vci_tgt_c (signal_vci_tgt_c_proc[p]); 402 proc[p]->p_irq[0] (signal_proc_it[p]); 400 403 for ( size_t j = 1 ; j < 6 ; j++ ) 401 404 { 402 proc[p]->p_irq[j] 405 proc[p]->p_irq[j] (signal_false); 403 406 } 404 407 } 405 408 406 409 // XICU 407 xicu->p_clk 408 xicu->p_resetn 409 xicu->p_vci 410 xicu->p_clk (this->p_clk); 411 xicu->p_resetn (this->p_resetn); 412 xicu->p_vci (signal_vci_tgt_d_xicu); 410 413 for ( size_t p=0 ; p<nprocs ; p++) 411 414 { 412 xicu->p_irq[p] 415 xicu->p_irq[p] (signal_proc_it[p]); 413 416 } 414 417 for ( size_t p=0 ; p<nprocs ; p++) 415 418 { 416 xicu->p_hwi[p] 419 xicu->p_hwi[p] (signal_irq_mdma[p]); 417 420 } 418 421 for ( size_t x=nprocs ; x<4 ; x++) 419 422 { 420 xicu->p_hwi[x] 423 xicu->p_hwi[x] (signal_false); 421 424 } 422 425 if ( io == true ) 423 424 xicu->p_hwi[4] 425 xicu->p_hwi[5] 426 xicu->p_hwi[6] 427 xicu->p_hwi[7] 428 xicu->p_hwi[8] 429 426 { 427 xicu->p_hwi[4] (signal_irq_tty0); 428 xicu->p_hwi[5] (signal_irq_tty1); 429 xicu->p_hwi[6] (signal_irq_tty2); 430 xicu->p_hwi[7] (signal_irq_tty3); 431 xicu->p_hwi[8] (signal_irq_bdev); 432 } 430 433 431 434 // MEMC 432 memc->p_clk 433 memc->p_resetn 434 memc->p_vci_ixr 435 memc->p_vci_tgt 436 memc->p_vci_ini 437 memc->p_vci_tgt_cleanup 435 memc->p_clk (this->p_clk); 436 memc->p_resetn (this->p_resetn); 437 memc->p_vci_ixr (signal_vci_xram); 438 memc->p_vci_tgt (signal_vci_tgt_d_memc); 439 memc->p_vci_ini (signal_vci_ini_c_memc); 440 memc->p_vci_tgt_cleanup (signal_vci_tgt_c_memc); 438 441 439 442 // XRAM 440 xram->p_clk 441 xram->p_resetn 442 xram->p_vci 443 xram->p_clk (this->p_clk); 444 xram->p_resetn (this->p_resetn); 445 xram->p_vci (signal_vci_xram); 443 446 444 447 // CDMA 445 mdma->p_clk 446 mdma->p_resetn 447 mdma->p_vci_target 448 mdma->p_vci_initiator 448 mdma->p_clk (this->p_clk); 449 mdma->p_resetn (this->p_resetn); 450 mdma->p_vci_target (signal_vci_tgt_d_mdma); 451 mdma->p_vci_initiator (signal_vci_ini_d_mdma); 449 452 for (size_t p=0 ; p<nprocs ; p++) 450 453 { … … 452 455 } 453 456 454 455 456 457 458 459 bdev->p_clk(this->p_clk);460 bdev->p_resetn(this->p_resetn);461 bdev->p_irq(signal_irq_bdev);462 bdev->p_vci_target(signal_vci_tgt_d_bdev);463 bdev->p_vci_initiator(signal_vci_ini_d_bdev);464 465 466 fbuf->p_clk(this->p_clk);467 fbuf->p_resetn(this->p_resetn);468 fbuf->p_vci(signal_vci_tgt_d_fbuf);469 470 471 brom->p_clk(this->p_clk);472 brom->p_resetn(this->p_resetn);473 brom->p_vci(signal_vci_tgt_d_brom);457 // Components in IO cluster 458 459 if ( io == true ) 460 { 461 // BDEV 462 bdev->p_clk (this->p_clk); 463 bdev->p_resetn (this->p_resetn); 464 bdev->p_irq (signal_irq_bdev); 465 bdev->p_vci_target (signal_vci_tgt_d_bdev); 466 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 467 468 // FBUF 469 fbuf->p_clk (this->p_clk); 470 fbuf->p_resetn (this->p_resetn); 471 fbuf->p_vci (signal_vci_tgt_d_fbuf); 472 473 // BROM 474 brom->p_clk (this->p_clk); 475 brom->p_resetn (this->p_resetn); 476 brom->p_vci (signal_vci_tgt_d_brom); 474 477 475 478 // MTTY 476 mtty->p_clk 477 mtty->p_resetn 478 mtty->p_vci 479 mtty->p_irq[0] 480 mtty->p_irq[1] 481 mtty->p_irq[2] 482 mtty->p_irq[3] 479 mtty->p_clk (this->p_clk); 480 mtty->p_resetn (this->p_resetn); 481 mtty->p_vci (signal_vci_tgt_d_mtty); 482 mtty->p_irq[0] (signal_irq_tty0); 483 mtty->p_irq[1] (signal_irq_tty1); 484 mtty->p_irq[2] (signal_irq_tty2); 485 mtty->p_irq[3] (signal_irq_tty3); 483 486 } 484 487 } // end constructor
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