- Timestamp:
- May 28, 2013, 9:53:03 AM (11 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r386 r394 63 63 : public soclib::caba::BaseModule 64 64 { 65 typedef uint32_t vaddr_t; 66 typedef uint32_t tag_t; 67 typedef uint32_t type_t; 68 typedef typename iss_t::DataOperationType data_op_t; 69 70 typedef typename vci_param::addr_t paddr_t; 71 typedef typename vci_param::data_t vci_data_t; 72 typedef typename vci_param::be_t vci_be_t; 73 typedef typename vci_param::srcid_t vci_srcid_t; 74 typedef typename vci_param::trdid_t vci_trdid_t; 75 typedef typename vci_param::pktid_t vci_pktid_t; 76 typedef typename vci_param::plen_t vci_plen_t; 77 78 enum icache_fsm_state_e { 65 66 typedef typename vci_param::fast_addr_t paddr_t; 67 68 enum icache_fsm_state_e 69 { 79 70 ICACHE_IDLE, 80 71 // handling XTN processor requests … … 104 95 }; 105 96 106 enum dcache_fsm_state_e { 97 enum dcache_fsm_state_e 98 { 107 99 DCACHE_IDLE, 108 100 // handling itlb & dtlb miss … … 154 146 }; 155 147 156 enum cmd_fsm_state_e { 148 enum cmd_fsm_state_e 149 { 157 150 CMD_IDLE, 158 151 CMD_INS_MISS, … … 166 159 }; 167 160 168 enum rsp_fsm_state_e { 161 enum rsp_fsm_state_e 162 { 169 163 RSP_IDLE, 170 164 RSP_INS_MISS, … … 176 170 }; 177 171 178 enum cc_receive_fsm_state_e { 172 enum cc_receive_fsm_state_e 173 { 179 174 CC_RECEIVE_IDLE, 180 175 CC_RECEIVE_CLACK, … … 188 183 }; 189 184 190 enum cc_send_fsm_state_e { 185 enum cc_send_fsm_state_e 186 { 191 187 CC_SEND_IDLE, 192 188 CC_SEND_CLEANUP_1, … … 224 220 225 221 // cc_send_type 226 typedef enum { 222 typedef enum 223 { 227 224 CC_TYPE_CLEANUP, 228 225 CC_TYPE_MULTI_ACK, … … 230 227 231 228 // cc_receive_type 232 typedef enum { 229 typedef enum 230 { 233 231 CC_TYPE_CLACK, 234 232 CC_TYPE_BRDCAST, … … 238 236 239 237 // TLB Mode : ITLB / DTLB / ICACHE / DCACHE 240 enum { 238 enum 239 { 241 240 INS_TLB_MASK = 0x8, 242 241 DATA_TLB_MASK = 0x4, … … 298 297 soclib::common::AddressDecodingTable<uint32_t, bool> m_cacheability_table; 299 298 300 const vci_srcid_tm_srcid;299 const size_t m_srcid; 301 300 const size_t m_cc_global_id; 302 301 const size_t m_nline_width; … … 330 329 331 330 ///////////////////////////////////////////// 332 // debug variables (for each FSM)331 // debug variables 333 332 ///////////////////////////////////////////// 334 bool m_debug_previous_hit; 335 bool m_idebug_previous_hit; 336 bool m_debug_dcache_fsm; 337 bool m_debug_icache_fsm; 338 bool m_debug_inval_itlb_fsm; 339 bool m_debug_inval_dtlb_fsm; 333 bool m_debug_previous_i_hit; 334 bool m_debug_previous_d_hit; 335 bool m_debug_activated; 340 336 341 337 /////////////////////////////// … … 404 400 sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) 405 401 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) 406 sc_signal< vci_be_t> r_dcache_save_be; // byte enable (from proc)402 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 407 403 sc_signal<paddr_t> r_dcache_save_paddr; // physical address 408 404 sc_signal<bool> r_dcache_save_cacheable; // address cacheable … … 425 421 sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL 426 422 sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC 427 sc_signal< vci_data_t>r_dcache_vci_sc_data; // SC data (command)423 sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) 428 424 429 425 // register used for XTN inval … … 482 478 483 479 // dcache directory extension 484 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 485 bool *r_dcache_contains_ptd; // cache line contains a PTD 480 bool *r_dcache_in_tlb; // copy exist in dtlb or itlb 481 bool *r_dcache_contains_ptd; // cache line contains a PTD 482 483 // Physical address extension for data access 484 sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) 486 485 487 486 /////////////////////////////////// … … 489 488 /////////////////////////////////// 490 489 sc_signal<int> r_vci_cmd_fsm; 491 sc_signal<size_t> r_vci_cmd_min; // used for write bursts492 sc_signal<size_t> r_vci_cmd_max; // used for write bursts493 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts494 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss490 sc_signal<size_t> r_vci_cmd_min; // used for write bursts 491 sc_signal<size_t> r_vci_cmd_max; // used for write bursts 492 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts 493 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss 495 494 496 495 /////////////////////////////////// … … 501 500 sc_signal<bool> r_vci_rsp_ins_error; 502 501 sc_signal<bool> r_vci_rsp_data_error; 503 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM504 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM502 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 503 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 505 504 506 505 /////////////////////////////////// 507 506 // CC_SEND FSM REGISTER 508 507 /////////////////////////////////// 509 sc_signal<int> r_cc_send_fsm; // state register510 sc_signal<bool> r_cc_send_last_client; // round robin flip-flop :0 dcache / 1 icache508 sc_signal<int> r_cc_send_fsm; // state register 509 sc_signal<bool> r_cc_send_last_client; // 0 dcache / 1 icache 511 510 512 511 /////////////////////////////////// 513 512 // CC_RECEIVE FSM REGISTER 514 513 /////////////////////////////////// 515 sc_signal<int> r_cc_receive_fsm; // state register516 sc_signal<bool> r_cc_receive_data_ins; // request concerning: 0 dcache / 1 icache517 518 // communication cc updt FIFObetween CC_RECEIVE FSM and ICACHE/DCACHE FSM519 sc_signal<size_t> r_cc_receive_word_idx; // word index514 sc_signal<int> r_cc_receive_fsm; // state register 515 sc_signal<bool> r_cc_receive_data_ins; // request to : 0 dcache / 1 icache 516 517 // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM 518 sc_signal<size_t> r_cc_receive_word_idx; // word index 520 519 GenericFifo<uint32_t> r_cc_receive_updt_fifo_be; 521 520 GenericFifo<uint32_t> r_cc_receive_updt_fifo_data; … … 523 522 524 523 // communication between CC_RECEIVE FSM and ICACHE FSM 525 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request526 sc_signal<cc_receive_t> r_cc_receive_icache_type; // cc_receive type of coherencerequest527 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way528 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set524 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request 525 sc_signal<cc_receive_t> r_cc_receive_icache_type; // cc_receive type of request 526 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way 527 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set 529 528 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index 530 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address529 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address 531 530 532 531 // communication between CC_RECEIVE FSM and DCACHE FSM 533 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request534 sc_signal<cc_receive_t> r_cc_receive_dcache_type; // cc_receive type of coherencerequest535 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way536 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set532 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request 533 sc_signal<cc_receive_t> r_cc_receive_dcache_type; // cc_receive type of request 534 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way 535 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set 537 536 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index 538 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address537 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 539 538 540 539 ////////////////////////////////////////////////////////////////// … … 714 713 void print_trace(size_t mode = 0); 715 714 void cache_monitor(paddr_t addr); 716 inline void iss_set_debug_mask(uint v) { 717 r_iss.set_debug_mask(v); 715 inline void iss_set_debug_mask(uint v) 716 { 717 r_iss.set_debug_mask(v); 718 718 } 719 719
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