Ignore:
Timestamp:
Jul 26, 2013, 5:03:12 PM (9 years ago)
Author:
lgarcia
Message:

Reintroducing RWT branch merging the last modifications of the
trunk (CLACK channel)
WARNING: bugs remaining (with 1c16p and small caches (L2:16*16; L1:4*4))

Location:
branches/RWT
Files:
2 added
1 edited
1 copied

Legend:

Unmodified
Added
Removed
  • branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r468 r477  
    115115        DCACHE_XTN_IT_INVAL,
    116116        DCACHE_XTN_DC_FLUSH,
     117        DCACHE_XTN_DC_FLUSH_DATA,
    117118        DCACHE_XTN_DC_FLUSH_GO,
    118119        DCACHE_XTN_DC_INVAL_VA,
     
    120121        DCACHE_XTN_DC_INVAL_END,
    121122        DCACHE_XTN_DC_INVAL_GO,
     123        DCACHE_XTN_DC_INVAL_DATA,
    122124        DCACHE_XTN_DT_INVAL,
    123125        //handling dirty bit update
     
    127129        DCACHE_MISS_SELECT,
    128130        DCACHE_MISS_CLEAN,
     131        DCACHE_MISS_DATA,
    129132        DCACHE_MISS_WAIT,
    130133        DCACHE_MISS_DATA_UPDT,
     
    138141        DCACHE_CC_UPDT,
    139142        DCACHE_CC_INVAL,
     143        DCACHE_CC_INVAL_DATA,
    140144        // handling TLB inval (after a coherence or XTN request)
    141145        DCACHE_INVAL_TLB_SCAN,
     
    188192        CC_SEND_CLEANUP_1,
    189193        CC_SEND_CLEANUP_2,
     194        CC_SEND_CLEANUP_DATA_UPDT,
    190195        CC_SEND_MULTI_ACK,
    191196    };
     
    283288        TYPE_INS_MISS     = 0x3,
    284289    };
     290
     291    //////////////////MODIFIED////////////////
     292    enum content_line_cache_status_e
     293    {
     294        LINE_CACHE_DATA_NOT_DIRTY,
     295        LINE_CACHE_DATA_DIRTY,
     296        LINE_CACHE_IN_TLB,
     297        LINE_CACHE_CONTAINS_PTD,
     298    };
     299    //////////////////////////////////////////
    285300
    286301public:
     
    390405    // communication between ICACHE FSM and CC_SEND FSM
    391406    sc_signal<bool>         r_icache_cc_send_req;           // ICACHE cc_send request
    392     sc_signal<cc_send_t>    r_icache_cc_send_type;          // ICACHE cc_send request type
     407    sc_signal<int>          r_icache_cc_send_type;          // ICACHE cc_send request type
    393408    sc_signal<paddr_t>      r_icache_cc_send_nline;         // ICACHE cc_send nline
    394409    sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
     
    429444    sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
    430445
     446    //RWT: local cas
     447    sc_signal<bool>         r_cas_islocal;
     448    sc_signal<size_t>       r_cas_local_way;
     449    sc_signal<size_t>       r_cas_local_set;
     450    sc_signal<size_t>       r_cas_local_word;
     451
    431452    // register used for XTN inval
    432453    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
     
    447468    sc_signal<size_t>       r_dcache_cc_way;                // selected way for cc update/inval
    448469    sc_signal<size_t>       r_dcache_cc_set;                // selected set for cc update/inval
     470    sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
    449471    sc_signal<size_t>       r_dcache_cc_word;               // word counter for cc update
    450472    sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
     473    sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
     474    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt; 
    451475
    452476    // coherence clack handling
     
    483507    // communication between DCACHE FSM and CC_SEND FSM
    484508    sc_signal<bool>         r_dcache_cc_send_req;           // DCACHE cc_send request
    485     sc_signal<cc_send_t>    r_dcache_cc_send_type;          // DCACHE cc_send request type
     509    sc_signal<int>          r_dcache_cc_send_type;          // DCACHE cc_send request type
    486510    sc_signal<paddr_t>      r_dcache_cc_send_nline;         // DCACHE cc_send nline
    487511    sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
    488512    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
    489 
     513   
     514    // special registers for ODCCP/RWT
     515    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
     516    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
     517    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
     518    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
     519    sc_signal<bool>         r_dcache_dirty_save;             
     520    sc_signal<uint32_t>     r_cc_send_cpt_word;
     521    sc_signal<uint32_t>     r_dcache_miss_data_cpt;
     522    sc_signal<paddr_t>      r_dcache_miss_data_addr;
     523    sc_signal<uint32_t>     r_dcache_xtn_flush_data_cpt;
     524    sc_signal<paddr_t>      r_dcache_xtn_flush_addr_data;
     525    sc_signal<int>          r_dcache_xtn_state;
     526    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
     527    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
    490528    // dcache directory extension
    491     bool                    *r_dcache_in_tlb;               // copy exist in dtlb or itlb
    492     bool                    *r_dcache_contains_ptd;         // cache line contains a PTD
    493 
     529    ///////////////////////////MODIFIED///////////////////////////////////////////////////
     530    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
     531    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
     532    int                     *r_dcache_content_state;    // content state of one cache line
     533    int                     *r_dcache_dirty_word;    // content state of one cache line
     534    //////////////////////////////////////////////////////////////////////////////////////
     535
     536    //RWT
     537    sc_signal<bool>         r_dcache_read_state;
     538   
     539     ///////////////////////////////////
    494540    // Physical address extension for data access
    495541    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
     
    513559    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;              // response FIFO to ICACHE FSM
    514560    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;              // response FIFO to DCACHE FSM
     561   
     562
     563    //RWT
     564    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
     565
     566    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
    515567
    516568    ///////////////////////////////////
     
    534586    // communication between CC_RECEIVE FSM and ICACHE FSM
    535587    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
    536     sc_signal<cc_receive_t> r_cc_receive_icache_type;       // cc_receive type of request
     588    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
    537589    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
    538590    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
     
    542594    // communication between CC_RECEIVE FSM and DCACHE FSM
    543595    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
    544     sc_signal<cc_receive_t> r_cc_receive_dcache_type;       // cc_receive type of request
     596    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
    545597    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
    546598    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
     
    593645    uint32_t m_cpt_data_read;               // total number of read data
    594646    uint32_t m_cpt_data_write;              // total number of write data
     647    uint32_t m_cpt_data_write_back;
     648    uint32_t m_cpt_data_cleanup;
     649    uint32_t m_cpt_data_sc;
    595650    uint32_t m_cpt_data_miss;               // number of read miss
    596651    uint32_t m_cpt_ins_miss;                // number of instruction miss
     
    608663    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
    609664    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
     665    uint32_t m_cpt_dunc_transaction;         // number of VCI uncached read transactions
     666    uint32_t m_cpt_ll_transaction;         // number of VCI uncached read transactions
    610667    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
    611668    uint32_t m_cpt_icache_unc_transaction;
     
    673730    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
    674731    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
     732    uint32_t m_cpt_cleanup_data_not_dirty;
     733    uint32_t m_cpt_cleanup_data_dirty_word;
    675734
    676735    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
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