Changeset 48 for trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
- Timestamp:
- Jun 13, 2010, 8:29:15 AM (14 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r37 r48 440 440 441 441 uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen 442 uint32_t m_cpt_total_cycles; // total number of cycles 442 uint32_t m_cpt_total_cycles; // total number of cycles 443 uint32_t m_cpt_dcache_frz_cycles; // number of cycles where the data cache is frozen 443 444 444 445 // Cache activity counters … … 460 461 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 461 462 uint32_t m_cpt_write_transaction; // number of VCI write transactions 463 uint32_t m_cpt_icache_unc_transaction; 462 464 463 465 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions … … 465 467 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 466 468 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 469 uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions 467 470 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions 468 471 … … 470 473 uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read 471 474 uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss 472 uint32_t m_cpt_ins_tlb_write_et; // number of instruction tlb write ET 473 475 uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc 474 476 uint32_t m_cpt_data_tlb_read; // number of data tlb read 475 477 uint32_t m_cpt_data_tlb_miss; // number of data tlb miss 476 uint32_t m_cpt_data_tlb_write_et; // number of data tlb write ET 477 uint32_t m_cpt_data_tlb_write_dirty; // number of data tlb write dirty 478 uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc 479 uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty 480 uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache 481 uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache 482 uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line 483 uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line 484 uint32_t m_cpt_tlb_occupy_dcache; 478 485 479 486 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss 480 487 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss 481 482 uint32_t m_cost_ins_waste_wait_frz; // number of frozen cycles related to ins wait coherence operate 483 uint32_t m_cost_ins_tlb_sw_frz; // number of frozen cycles related to ins context switch 484 uint32_t m_cost_ins_cache_flush_frz; // number of frozen cycles related to ins cache flush 485 486 uint32_t m_cpt_ins_tlb_cleanup; // number of ins tlb cleanup 487 uint32_t m_cost_data_waste_wait_frz; // number of frozen cycles related to data wait coherence operate 488 uint32_t m_cost_data_tlb_sw_frz; // number of frozen cycles related to data context switch 489 uint32_t m_cost_data_cache_flush_frz; // number of frozen cycles related to data cache flush 490 491 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions 492 uint32_t m_cpt_itlb_write_transaction; // number of itlb write ET transactions 493 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions 494 uint32_t m_cpt_dtlb_write_transaction; // number of dtlb write ET and dirty transactions 495 496 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 497 uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions 498 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 499 uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions 500 501 uint32_t m_cpt_cc_update; // number of coherence update packets 502 uint32_t m_cpt_cc_inval; // number of coherence inval packets 503 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets 488 uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc 489 uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc 490 uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty 491 uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache 492 uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache 493 494 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions 495 uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions 496 uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions 497 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions 498 uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions 499 uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions 500 uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions 501 uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions 502 503 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 504 uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions 505 uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions 506 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 507 uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions 508 uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions 509 uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions 510 uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions 511 512 uint32_t m_cpt_cc_update_data; // number of coherence update data packets 513 uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets 514 uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets 515 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets 504 516 505 517 uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate
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