Changeset 48 for trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h
- Timestamp:
- Jun 13, 2010, 8:29:15 AM (14 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h
r38 r48 313 313 sc_signal<size_t> r_dcache_way; 314 314 sc_signal<size_t> r_dcache_set; 315 sc_signal<bool> r_dcache_cleanup_check_req;316 315 sc_signal<bool> r_dcache_cleanup_req; 317 316 sc_signal<data_t> r_dcache_cleanup_line; … … 347 346 sc_signal<size_t> r_icache_way; 348 347 sc_signal<size_t> r_icache_set; 349 sc_signal<bool> r_icache_cleanup_check_req;350 348 sc_signal<bool> r_icache_cleanup_req; 351 349 sc_signal<data_t> r_icache_cleanup_line; … … 383 381 sc_signal<bool> r_tgt_icache_req; 384 382 sc_signal<bool> r_tgt_dcache_req; 385 sc_signal<bool> r_tgt_icache_tlb_req;386 sc_signal<bool> r_tgt_dcache_tlb_req;387 383 sc_signal<bool> r_tgt_icache_rsp; 388 384 sc_signal<bool> r_tgt_dcache_rsp; … … 440 436 uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read of cache 441 437 uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss of cache 442 uint32_t m_cost_cc_wait_frz; // number of frozen cycles related to cc check443 438 444 439 uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions … … 446 441 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 447 442 uint32_t m_cpt_write_transaction; // number of VCI write transactions 443 uint32_t m_cpt_icache_unc_transaction; // number of VCI instruction uncached transactions 448 444 449 445 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions 450 446 uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions 451 447 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 448 uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions 452 449 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 453 450 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions … … 456 453 uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read 457 454 uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss 458 uint32_t m_cpt_ins_tlb_write_et; // number of instruction tlb write ET 459 455 uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update acc 460 456 uint32_t m_cpt_data_tlb_read; // number of data tlb read 461 457 uint32_t m_cpt_data_tlb_miss; // number of data tlb miss 462 uint32_t m_cpt_data_tlb_ write_et; // number of data tlb write ET463 uint32_t m_cpt_data_tlb_ write_dirty; // number of data tlb write dirty458 uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update acc 459 uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty 464 460 465 461 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss 466 462 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss 467 uint32_t m_cost_ins_tlb_flush_frz; // number of cycles for instruction tlb flush 468 uint32_t m_cost_data_tlb_flush_frz; // number of cycles for data tlb flush 469 uint32_t m_cost_ins_cache_flush_frz; // number of cycles for instruction cache flush 470 uint32_t m_cost_data_cache_flush_frz; // number of cycles for data cache flush 471 uint32_t m_cost_data_waste_wait_frz; 463 uint32_t m_cost_ins_tlb_update_acc_frz; // number of cycles for instruction tlb flush 464 uint32_t m_cost_data_tlb_update_acc_frz; // number of cycles for data tlb flush 465 uint32_t m_cost_data_tlb_update_dirty_frz; // number of cycles for instruction cache flush 472 466 473 467 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions 474 uint32_t m_cpt_itlb_write_transaction; // number of itlb write ET transactions 468 uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions 469 uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions 475 470 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions 476 uint32_t m_cpt_dtlb_write_transaction; // number of dtlb write ET and dirty transactions 471 uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions 472 uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions 473 uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions 474 uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions 477 475 478 476 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 479 uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions 477 uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions 478 uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions 480 479 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 481 uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions 482 483 uint32_t m_cpt_cc_update; // number of coherence update packets 484 uint32_t m_cpt_cc_inval; // number of coherence inval packets 485 uint32_t m_cpt_cc_broadcast; // number of coherence inval packets 486 487 uint32_t m_cost_cc_update_frz; // number of waiting cycles for coherence update 488 uint32_t m_cost_cc_inval_frz; // number of waiting cycles for coherence invalidate 480 uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions 481 uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions 482 uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions 483 uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions 484 485 uint32_t m_cpt_cc_cleanup_ins; 486 uint32_t m_cpt_cc_cleanup_data; 487 uint32_t m_cpt_icleanup_transaction; 488 uint32_t m_cpt_dcleanup_transaction; 489 uint32_t m_cost_icleanup_transaction; 490 uint32_t m_cost_dcleanup_transaction; 491 492 uint32_t m_cpt_cc_update_data; // number of coherence update data packets 493 uint32_t m_cpt_cc_inval_ins; // number of coherence inval instruction packets 494 uint32_t m_cpt_cc_inval_data; // number of coherence inval data packets 495 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast packets 489 496 490 497 protected:
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