Changeset 48 for trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp
- Timestamp:
- Jun 13, 2010, 8:29:15 AM (14 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp
r38 r48 320 320 << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl 321 321 << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl 322 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl323 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl324 322 << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl 325 323 << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 326 324 << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl 327 << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl 328 << "- DMISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 329 << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl 325 << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 326 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 330 327 << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl 331 << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl 332 << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl 333 << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl 334 << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl 328 << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 329 << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 335 330 << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl 336 331 << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl 332 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl 333 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl 334 << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl 335 << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl 336 << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 337 << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl 338 << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl 339 << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl 340 << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl 341 << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl 342 << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl 337 343 << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl 338 << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl 339 << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl 340 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl 341 << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl 342 << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl; 344 << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; 343 345 } 344 346 … … 396 398 r_dcache_xtn_req = false; 397 399 398 r_icache_cleanup_check_req = false; 400 r_dcache_dirty_save = false; 401 r_dcache_hit_p_save = false; 402 r_dcache_cached_save = false; 403 404 r_icache_buf_unc_valid = false; 405 r_dcache_buf_unc_valid = false; 406 407 r_vci_rsp_ins_error = false; 408 r_vci_rsp_data_error = false; 409 410 r_icache_id1_save = 0; 411 r_icache_ppn_save = 0; 412 r_icache_vpn_save = 0; 413 r_itlb_translation_valid = false; 414 415 r_dcache_id1_save = 0; 416 r_dcache_ppn_save = 0; 417 r_dcache_vpn_save = 0; 418 r_dtlb_translation_valid = false; 419 420 r_icache_ptba_ok = false; 421 r_dcache_ptba_ok = false; 422 423 r_icache_error_type = MMU_NONE; 424 r_dcache_error_type = MMU_NONE; 425 399 426 r_icache_cleanup_req = false; 400 427 r_icache_cleanup_type = NONE; 401 428 402 r_dcache_cleanup_check_req = false;403 429 r_dcache_cleanup_req = false; 404 430 r_dcache_cleanup_type = NONE; … … 428 454 r_dcache_inval_tlb_rsp = false; 429 455 430 r_dcache_dirty_save = false;431 r_dcache_hit_p_save = false;432 433 r_icache_buf_unc_valid = false;434 r_dcache_buf_unc_valid = false;435 436 r_vci_rsp_ins_error = false;437 r_vci_rsp_data_error = false;438 439 r_icache_id1_save = 0;440 r_icache_ppn_save = 0;441 r_icache_vpn_save = 0;442 r_itlb_translation_valid = false;443 444 r_dcache_id1_save = 0;445 r_dcache_ppn_save = 0;446 r_dcache_vpn_save = 0;447 r_dtlb_translation_valid = false;448 449 r_icache_ptba_ok = false;450 r_dcache_ptba_ok = false;451 452 r_icache_error_type = MMU_NONE;453 r_dcache_error_type = MMU_NONE;454 455 456 // activity counters 456 457 m_cpt_dcache_data_read = 0; … … 479 480 m_cost_ins_miss_frz = 0; 480 481 481 m_cpt_imiss_transaction = 0; 482 m_cpt_dmiss_transaction = 0; 483 m_cpt_unc_transaction = 0; 484 m_cpt_write_transaction = 0; 485 486 m_cost_imiss_transaction = 0; 487 m_cost_dmiss_transaction = 0; 488 m_cost_unc_transaction = 0; 489 m_cost_write_transaction = 0; 490 m_length_write_transaction = 0; 482 m_cpt_imiss_transaction = 0; 483 m_cpt_dmiss_transaction = 0; 484 m_cpt_unc_transaction = 0; 485 m_cpt_write_transaction = 0; 486 m_cpt_icache_unc_transaction = 0; 487 488 m_cost_imiss_transaction = 0; 489 m_cost_dmiss_transaction = 0; 490 m_cost_unc_transaction = 0; 491 m_cost_write_transaction = 0; 492 m_cost_icache_unc_transaction = 0; 493 m_length_write_transaction = 0; 491 494 492 495 m_cpt_ins_tlb_read = 0; 493 496 m_cpt_ins_tlb_miss = 0; 494 m_cpt_ins_tlb_write_et = 0; 495 496 m_cpt_data_tlb_read = 0; 497 m_cpt_data_tlb_miss = 0; 498 m_cpt_data_tlb_write_et = 0; 499 m_cpt_data_tlb_write_dirty = 0; 500 501 m_cost_ins_tlb_miss_frz = 0; 502 m_cost_data_tlb_miss_frz = 0; 503 504 m_cpt_itlbmiss_transaction = 0; 505 m_cpt_itlb_write_transaction = 0; 506 m_cpt_dtlbmiss_transaction = 0; 507 m_cpt_dtlb_write_transaction = 0; 497 m_cpt_ins_tlb_update_acc = 0; 498 499 m_cpt_data_tlb_read = 0; 500 m_cpt_data_tlb_miss = 0; 501 m_cpt_data_tlb_update_acc = 0; 502 m_cpt_data_tlb_update_dirty = 0; 503 504 m_cost_ins_tlb_miss_frz = 0; 505 m_cost_data_tlb_miss_frz = 0; 506 m_cost_ins_tlb_update_acc_frz = 0; 507 m_cost_data_tlb_update_acc_frz = 0; 508 m_cost_data_tlb_update_dirty_frz = 0; 509 510 m_cpt_itlbmiss_transaction = 0; 511 m_cpt_itlb_ll_transaction = 0; 512 m_cpt_itlb_sc_transaction = 0; 513 m_cpt_dtlbmiss_transaction = 0; 514 m_cpt_dtlb_ll_transaction = 0; 515 m_cpt_dtlb_sc_transaction = 0; 516 m_cpt_dtlb_ll_dirty_transaction = 0; 517 m_cpt_dtlb_sc_dirty_transaction = 0; 508 518 509 m_cost_itlbmiss_transaction = 0; 510 m_cost_itlb_write_transaction = 0; 511 m_cost_dtlbmiss_transaction = 0; 512 m_cost_dtlb_write_transaction = 0; 519 m_cost_itlbmiss_transaction = 0; 520 m_cost_itlb_ll_transaction = 0; 521 m_cost_itlb_sc_transaction = 0; 522 m_cost_dtlbmiss_transaction = 0; 523 m_cost_dtlb_ll_transaction = 0; 524 m_cost_dtlb_sc_transaction = 0; 525 m_cost_dtlb_ll_dirty_transaction = 0; 526 m_cost_dtlb_sc_dirty_transaction = 0; 527 528 m_cpt_cc_cleanup_ins = 0; 529 m_cpt_cc_cleanup_data = 0; 530 m_cpt_icleanup_transaction = 0; 531 m_cpt_dcleanup_transaction = 0; 532 m_cost_icleanup_transaction = 0; 533 m_cost_dcleanup_transaction = 0; 534 535 m_cpt_cc_update_data = 0; 536 m_cpt_cc_inval_ins = 0; 537 m_cpt_cc_inval_data = 0; 538 m_cpt_cc_broadcast = 0; 513 539 return; 514 540 } … … 630 656 r_tgt_update = false; 631 657 r_vci_tgt_fsm = TGT_REQ_DCACHE; 632 m_cpt_cc_inval ++ ;658 m_cpt_cc_inval_data++ ; 633 659 } 634 660 else if (cell == 4) // update … … 642 668 r_tgt_update = true; 643 669 r_vci_tgt_fsm = TGT_UPDT_WORD; 644 m_cpt_cc_update ++ ;670 m_cpt_cc_update_data++ ; 645 671 } 646 672 else if (cell == 8) … … 654 680 r_tgt_update = false; 655 681 r_vci_tgt_fsm = TGT_REQ_ICACHE; 656 m_cpt_cc_inval ++ ;682 m_cpt_cc_inval_ins++ ; 657 683 } 658 684 } // end if address … … 853 879 if (r_dcache_xtn_req) 854 880 { 855 if ( ireq.valid ) m_cost_ins_miss_frz++;856 857 881 if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR) 858 882 { … … 889 913 if ( r_tgt_icache_req ) 890 914 { 891 if ( ireq.valid ) m_cost_ins_miss_frz++;892 915 r_icache_fsm = ICACHE_CC_INVAL; 893 916 r_icache_fsm_save = r_icache_fsm; … … 1011 1034 r_icache_vaddr_req = ireq.addr; 1012 1035 r_icache_fsm = ICACHE_BIS; 1013 m_cost_ins_ miss_frz++;1036 m_cost_ins_tlb_miss_frz++; 1014 1037 } 1015 1038 else // cached or uncached access with a correct speculative physical address … … 1089 1112 r_icache_fsm = ICACHE_MISS_WAIT; 1090 1113 m_cpt_ins_miss++; 1091 m_cost_ins_miss_frz++;1092 1114 } 1093 1115 else … … 1116 1138 { 1117 1139 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1118 1119 1140 // external cache invalidate request 1120 1141 if ( r_tgt_icache_req ) … … 1166 1187 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1167 1188 r_icache_cleanup_type = TLB_CLEANUP; 1189 m_cpt_cc_cleanup_ins++; 1168 1190 } 1169 1191 else // PTE … … 1183 1205 r_icache_tlb_ll_req = true; 1184 1206 r_icache_fsm = ICACHE_TLB1_LL_WAIT; 1185 m_cpt_ins_tlb_write_et++; 1207 m_cpt_ins_tlb_update_acc++; 1208 m_cost_ins_tlb_update_acc_frz++; 1186 1209 } 1187 1210 } … … 1198 1221 r_icache_tlb_ll_req = true; 1199 1222 r_icache_fsm = ICACHE_TLB1_LL_WAIT; 1200 m_cpt_ins_tlb_write_et++; 1223 m_cpt_ins_tlb_update_acc++; 1224 m_cost_ins_tlb_update_acc_frz++; 1201 1225 } 1202 1226 } … … 1226 1250 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1227 1251 r_icache_cleanup_type = TLB_CLEANUP; 1252 m_cpt_cc_cleanup_ins++; 1228 1253 r_icache_fsm = ICACHE_IDLE; 1229 1254 } … … 1235 1260 case ICACHE_TLB1_LL_WAIT: 1236 1261 { 1262 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1263 m_cost_ins_tlb_update_acc_frz++; 1264 1237 1265 // external cache invalidate request 1238 1266 if ( r_tgt_icache_req ) … … 1281 1309 case ICACHE_TLB1_SC_WAIT: 1282 1310 { 1311 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1312 m_cost_ins_tlb_update_acc_frz++; 1313 1283 1314 // external cache invalidate request 1284 1315 if ( r_tgt_icache_req ) … … 1341 1372 r_icache_cleanup_line = victim_index; 1342 1373 r_icache_cleanup_type = TLB_CLEANUP; 1374 m_cpt_cc_cleanup_ins++; 1343 1375 r_icache_fsm = ICACHE_IDLE; 1344 1376 } … … 1401 1433 r_icache_tlb_ll_req = true; 1402 1434 r_icache_fsm = ICACHE_TLB2_LL_WAIT; 1403 m_cpt_ins_tlb_write_et++; 1435 m_cpt_ins_tlb_update_acc++; 1436 m_cost_ins_tlb_update_acc_frz++; 1404 1437 } 1405 1438 } … … 1416 1449 r_icache_tlb_ll_req = true; 1417 1450 r_icache_fsm = ICACHE_TLB2_LL_WAIT; 1418 m_cpt_ins_tlb_write_et++; 1451 m_cpt_ins_tlb_update_acc++; 1452 m_cost_ins_tlb_update_acc_frz++; 1419 1453 } 1420 1454 } … … 1445 1479 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1446 1480 r_icache_cleanup_type = TLB_CLEANUP; 1481 m_cpt_cc_cleanup_ins++; 1447 1482 r_icache_fsm = ICACHE_IDLE; 1448 1483 } … … 1454 1489 case ICACHE_TLB2_LL_WAIT: 1455 1490 { 1491 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1492 m_cost_ins_tlb_update_acc_frz++; 1493 1456 1494 // external cache invalidate request 1457 1495 if ( r_tgt_icache_req ) … … 1500 1538 case ICACHE_TLB2_SC_WAIT: 1501 1539 { 1540 if ( ireq.valid ) m_cost_ins_tlb_miss_frz++; 1541 m_cost_ins_tlb_update_acc_frz++; 1542 1502 1543 // external cache invalidate request 1503 1544 if ( r_tgt_icache_req ) … … 1561 1602 r_icache_cleanup_line = victim_index; 1562 1603 r_icache_cleanup_type = TLB_CLEANUP; 1604 m_cpt_cc_cleanup_ins++; 1563 1605 r_icache_fsm = ICACHE_IDLE; 1564 1606 } … … 1594 1636 r_icache_cleanup_line = victim_index; 1595 1637 r_icache_cleanup_type = TLB_CLEANUP; 1638 m_cpt_cc_cleanup_ins++; 1596 1639 r_icache_way = way + ((set+1)/m_itlb_sets); 1597 1640 r_icache_set = (set+1) % m_itlb_sets; … … 1627 1670 size_t set = r_icache_set; 1628 1671 bool clean = false; 1629 1630 m_cost_ins_cache_flush_frz++;1631 1672 1632 1673 // cache flush and send cleanup to external … … 1644 1685 r_icache_cleanup_line = victim_index; 1645 1686 r_icache_cleanup_type = CACHE_CLEANUP; 1687 m_cpt_cc_cleanup_ins++; 1646 1688 r_icache_way = way + ((set+1)/m_icache_sets); 1647 1689 r_icache_set = (set+1) % m_icache_sets; … … 1670 1712 r_icache_cleanup_type = TLB_CLEANUP; 1671 1713 r_icache_cleanup_line = victim_index; 1714 m_cpt_cc_cleanup_ins++; 1672 1715 r_dcache_xtn_req = false; 1673 1716 r_itlb_translation_valid = false; … … 1708 1751 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1709 1752 r_icache_cleanup_type = CACHE_CLEANUP; 1753 m_cpt_cc_cleanup_ins++; 1710 1754 } 1711 1755 r_dcache_xtn_req = false; … … 1733 1777 r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2); 1734 1778 r_icache_cleanup_type = CACHE_CLEANUP; 1779 m_cpt_cc_cleanup_ins++; 1735 1780 r_dcache_xtn_req = false; 1736 1781 r_icache_fsm = ICACHE_IDLE; … … 1770 1815 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1771 1816 r_icache_cleanup_type = CACHE_CLEANUP; 1817 m_cpt_cc_cleanup_ins++; 1772 1818 r_icache_fsm = ICACHE_IDLE; 1773 1819 r_icache_inval_tlb_rsp = false; 1774 1820 if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; 1775 m_cost_ins_tlb_miss_frz++;1776 1821 break; 1777 1822 } … … 1783 1828 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1784 1829 r_icache_cleanup_type = CACHE_CLEANUP; 1830 m_cpt_cc_cleanup_ins++; 1785 1831 r_icache_fsm = ICACHE_IDLE; 1786 1832 r_icache_inval_rsp = false; … … 1794 1840 case ICACHE_UNC_WAIT: 1795 1841 { 1796 m_cost_ins_miss_frz++;1797 1842 // external cache invalidate request 1798 1843 if ( r_tgt_icache_req ) … … 1846 1891 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1847 1892 r_icache_cleanup_type = CACHE_CLEANUP; 1893 m_cpt_cc_cleanup_ins++; 1848 1894 r_icache_inval_tlb_rsp = false; 1849 1895 if ( r_icache_inval_rsp ) r_icache_inval_rsp = false; … … 1859 1905 r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 1860 1906 r_icache_cleanup_type = CACHE_CLEANUP; 1907 m_cpt_cc_cleanup_ins++; 1861 1908 r_icache_inval_rsp = false; 1862 1909 r_icache_fsm = ICACHE_IDLE; … … 1871 1918 r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index); 1872 1919 r_icache_cleanup_line = victim_index; 1873 r_icache_cleanup_type = CACHE_CLEANUP; 1920 r_icache_cleanup_type = CACHE_CLEANUP; 1921 m_cpt_cc_cleanup_ins++; 1874 1922 r_icache_fsm = ICACHE_IDLE; 1875 1923 } … … 1890 1938 case ICACHE_CC_INVAL: 1891 1939 { 1892 if ( ireq.valid ) m_cost_ins_miss_frz++;1893 1940 m_cpt_icache_dir_read += m_icache_ways; 1894 1941 1895 // invalidate cache 1942 /* activity counter */ 1943 if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) 1944 { 1945 m_cost_ins_miss_frz++; 1946 } 1947 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 1948 ( r_icache_fsm_save == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_LL_WAIT ) || 1949 ( r_icache_fsm_save == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_SC_WAIT ) || 1950 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) 1951 { 1952 m_cost_ins_tlb_miss_frz++; 1953 } 1954 1896 1955 if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && 1897 1956 ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) … … 1921 1980 case ICACHE_TLB_CC_INVAL: 1922 1981 { 1923 if ( ireq.valid ) m_cost_ins_miss_frz++; 1982 /* activity counter */ 1983 if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) ) 1984 { 1985 m_cost_ins_miss_frz++; 1986 } 1987 1988 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 1989 ( r_icache_fsm_save == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_LL_WAIT ) || 1990 ( r_icache_fsm_save == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_SC_WAIT ) || 1991 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) 1992 { 1993 m_cost_ins_tlb_miss_frz++; 1994 } 1924 1995 1925 1996 if ( r_icache_tlb_inval_req ) break; … … 1988 2059 1989 2060 // r_tgt_addr is number of line 1990 bool tlb_hit = icache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2)),way, set, &way, &set, &end); 1991 2061 bool tlb_hit = icache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2)),way, set, &way, &set, &end); 1992 2062 if ( tlb_hit ) 1993 2063 { … … 2007 2077 case INVAL_ITLB_INVAL: 2008 2078 { 2009 //m_cost_ins_tlb_inval_frz++;2010 2011 2079 icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set); 2012 2080 … … 2128 2196 r_dcache_fsm = DCACHE_CC_CHECK; 2129 2197 r_dcache_fsm_save = DCACHE_IDLE; 2130 if ( dreq.valid ) m_cost_data_miss_frz++;2131 2198 break; 2132 2199 } … … 2509 2576 r_dcache_hit_p_save = dcache_hit_p; 2510 2577 r_dcache_fsm = DCACHE_BIS; 2511 m_cost_data_ miss_frz++;2578 m_cost_data_tlb_miss_frz++; 2512 2579 } 2513 2580 else // cached or uncached access with a correct speculative physical address … … 2545 2612 m_cpt_write++; 2546 2613 if ( dcache_cached ) m_cpt_write_cached++; 2614 m_cost_write_frz++; 2547 2615 2548 2616 if ( dcache_hit_c && dcache_cached ) // cache update required … … 2553 2621 else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required 2554 2622 { 2623 m_cpt_data_tlb_update_dirty++; 2624 m_cost_data_tlb_update_dirty_frz++; 2555 2625 if (dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set)) 2556 2626 { … … 2559 2629 r_dcache_tlb_ll_dirty_req = true; 2560 2630 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2561 m_cpt_data_tlb_write_dirty++;2562 2631 } 2563 2632 else … … 2569 2638 r_dcache_tlb_ll_dirty_req = true; 2570 2639 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2571 m_cpt_data_tlb_write_dirty++;2572 2640 } 2573 2641 else // get PTBA to calculate the physical address of PTE … … 2581 2649 } 2582 2650 } 2583 m_cost_data_tlb_miss_frz++;2584 2651 } 2585 2652 else // no cache update, not dirty bit update … … 2685 2752 else if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) ) // dirty bit update required 2686 2753 { 2754 m_cpt_data_tlb_update_dirty++; 2755 m_cost_data_tlb_update_dirty_frz++; 2687 2756 if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 2688 2757 { … … 2691 2760 r_dcache_tlb_ll_dirty_req = true; 2692 2761 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2693 m_cpt_data_tlb_write_dirty++;2694 2762 } 2695 2763 else … … 2701 2769 r_dcache_tlb_ll_dirty_req = true; 2702 2770 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2703 m_cpt_data_tlb_write_dirty++;2704 2771 } 2705 2772 else … … 2713 2780 } 2714 2781 } 2715 m_cost_data_tlb_miss_frz++;2716 2782 } 2717 2783 else // no cache update, not dirty bit update … … 2735 2801 case DCACHE_LL_DIRTY_WAIT: 2736 2802 { 2803 m_cost_data_tlb_update_dirty_frz++; 2804 2737 2805 // external cache invalidate request 2738 2806 if ( r_tgt_dcache_req ) … … 2740 2808 r_dcache_fsm = DCACHE_CC_CHECK; 2741 2809 r_dcache_fsm_save = r_dcache_fsm; 2742 //m_cost_data_waste_wait_frz++;2743 2810 break; 2744 2811 } … … 2784 2851 r_dcache_inval_tlb_rsp = false; 2785 2852 r_dcache_fsm = DCACHE_IDLE; 2786 m_cost_data_tlb_miss_frz++;2787 2853 } 2788 2854 else if ( r_dcache_inval_rsp ) … … 2804 2870 case DCACHE_SC_DIRTY_WAIT: 2805 2871 { 2872 m_cost_data_tlb_update_dirty_frz++; 2806 2873 // external cache invalidate request 2807 2874 if ( r_tgt_dcache_req ) … … 2809 2876 r_dcache_fsm = DCACHE_CC_CHECK; 2810 2877 r_dcache_fsm_save = r_dcache_fsm; 2811 //m_cost_data_waste_wait_frz++;2812 2878 break; 2813 2879 } … … 2839 2905 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 2840 2906 r_dcache_fsm = DCACHE_IDLE; 2841 m_cost_data_tlb_miss_frz++;2842 2907 } 2843 2908 else if ( r_dcache_inval_rsp ) … … 2902 2967 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 2903 2968 r_dcache_cleanup_type = TLB_CLEANUP; 2969 m_cpt_cc_cleanup_data++; 2904 2970 r_dcache_inval_tlb_rsp = false; 2905 2971 break; … … 2932 2998 r_dcache_tlb_ll_dirty_req = true; 2933 2999 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2934 m_cpt_data_tlb_ write_dirty++;3000 m_cpt_data_tlb_update_dirty_frz++; 2935 3001 } 2936 3002 else … … 2945 3011 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 2946 3012 r_dcache_cleanup_type = TLB_CLEANUP; 3013 m_cpt_cc_cleanup_data++; 2947 3014 2948 3015 } … … 2962 3029 r_dcache_tlb_ll_acc_req = true; 2963 3030 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 2964 m_cpt_ins_tlb_write_et++; 3031 m_cpt_data_tlb_update_acc++; 3032 m_cost_data_tlb_update_acc_frz++; 2965 3033 } 2966 3034 } … … 2977 3045 r_dcache_tlb_ll_acc_req = true; 2978 3046 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 2979 m_cpt_ins_tlb_write_et++; 3047 m_cpt_data_tlb_update_acc++; 3048 m_cost_data_tlb_update_acc_frz++; 2980 3049 } 2981 3050 } … … 2987 3056 case DCACHE_TLB1_LL_WAIT: 2988 3057 { 3058 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3059 m_cost_data_tlb_update_acc_frz++; 3060 2989 3061 // external cache invalidate request 2990 3062 if ( r_tgt_dcache_req ) … … 3033 3105 r_dcache_inval_tlb_rsp = false; 3034 3106 r_dcache_fsm = DCACHE_IDLE; 3035 m_cost_data_tlb_miss_frz++;3036 3107 } 3037 3108 else … … 3048 3119 case DCACHE_TLB1_SC_WAIT: 3049 3120 { 3121 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3122 m_cost_data_tlb_update_acc_frz++; 3123 3050 3124 // external cache invalidate request 3051 3125 if ( r_tgt_dcache_req ) … … 3081 3155 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3082 3156 r_dcache_fsm = DCACHE_IDLE; 3083 m_cost_data_tlb_miss_frz++;3084 3157 } 3085 3158 else if ( r_dcache_tlb_sc_fail ) … … 3107 3180 r_dcache_fsm = DCACHE_CC_CHECK; 3108 3181 r_dcache_fsm_save = r_dcache_fsm; 3109 //m_cost_data_waste_wait_frz++;3110 3182 break; 3111 3183 } … … 3118 3190 r_dcache_cleanup_line = victim_index; 3119 3191 r_dcache_cleanup_type = TLB_CLEANUP; 3192 m_cpt_cc_cleanup_data++; 3120 3193 r_dcache_fsm = DCACHE_IDLE; 3121 3194 } … … 3169 3242 r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 3170 3243 r_dcache_cleanup_type = TLB_CLEANUP; 3244 m_cpt_cc_cleanup_data++; 3171 3245 r_dcache_inval_tlb_rsp = false; 3172 3246 break; … … 3205 3279 r_dcache_tlb_ll_acc_req = true; 3206 3280 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3207 m_cpt_ins_tlb_write_et++; 3281 m_cpt_data_tlb_update_acc++; 3282 m_cost_data_tlb_update_acc_frz++; 3208 3283 } 3209 3284 } … … 3220 3295 r_dcache_tlb_ll_acc_req = true; 3221 3296 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3222 m_cpt_ins_tlb_write_et++; 3297 m_cpt_data_tlb_update_acc++; 3298 m_cost_data_tlb_update_acc_frz++; 3223 3299 } 3224 3300 } … … 3230 3306 case DCACHE_TLB2_LL_WAIT: 3231 3307 { 3308 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3309 m_cost_data_tlb_update_acc_frz++; 3310 3232 3311 // external cache invalidate request 3233 3312 if ( r_tgt_dcache_req ) … … 3276 3355 r_dcache_inval_tlb_rsp = false; 3277 3356 r_dcache_fsm = DCACHE_IDLE; 3278 m_cost_data_tlb_miss_frz++;3279 3357 } 3280 3358 else … … 3291 3369 case DCACHE_TLB2_SC_WAIT: 3292 3370 { 3371 if ( dreq.valid ) m_cost_data_tlb_miss_frz++; 3372 m_cost_data_tlb_update_acc_frz++; 3373 3293 3374 // external cache invalidate request 3294 3375 if ( r_tgt_dcache_req ) … … 3324 3405 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3325 3406 r_dcache_fsm = DCACHE_IDLE; 3326 m_cost_data_tlb_miss_frz++;3327 3407 } 3328 3408 else if ( r_dcache_tlb_sc_fail ) … … 3360 3440 r_dcache_cleanup_line = victim_index; 3361 3441 r_dcache_cleanup_type = TLB_CLEANUP; 3442 m_cpt_cc_cleanup_data++; 3362 3443 r_dcache_fsm = DCACHE_IDLE; 3363 3444 } … … 3377 3458 size_t set = r_dcache_set; 3378 3459 bool clean = false; 3379 3380 m_cost_data_tlb_flush_frz++;3381 3460 3382 3461 // 4K page size TLB flush leads to cleanup req … … 3394 3473 r_dcache_cleanup_line = victim_index; 3395 3474 r_dcache_cleanup_type = TLB_CLEANUP; 3475 m_cpt_cc_cleanup_data++; 3396 3476 r_dcache_way = way + ((set+1)/m_dtlb_sets); 3397 3477 r_dcache_set = (set+1) % m_dtlb_sets; … … 3435 3515 r_dcache_fsm = DCACHE_CC_CHECK; 3436 3516 r_dcache_fsm_save = r_dcache_fsm; 3437 m_cost_data_waste_wait_frz++;3438 3517 break; 3439 3518 } … … 3456 3535 r_dcache_cleanup_line = victim_index; 3457 3536 r_dcache_cleanup_type = CACHE_CLEANUP; 3537 m_cpt_cc_cleanup_data++; 3458 3538 r_dcache_way = way + ((set+1)/m_dcache_sets); 3459 3539 r_dcache_set = (set+1) % m_dcache_sets; … … 3482 3562 r_dcache_cleanup_req = dcache_tlb.inval1(r_dcache_wdata_save, &victim_index); 3483 3563 r_dcache_cleanup_type = TLB_CLEANUP; 3564 m_cpt_cc_cleanup_data++; 3484 3565 r_dcache_cleanup_line = victim_index; 3485 3566 r_dtlb_translation_valid = false; … … 3498 3579 r_dcache_fsm = DCACHE_CC_CHECK; 3499 3580 r_dcache_fsm_save = r_dcache_fsm; 3500 m_cost_data_waste_wait_frz++;3501 3581 break; 3502 3582 } … … 3523 3603 r_dcache_cleanup_req = r_dcache.inval(dpaddr); 3524 3604 r_dcache_cleanup_type = CACHE_CLEANUP; 3605 m_cpt_cc_cleanup_data++; 3525 3606 r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); 3526 3607 } … … 3538 3619 r_dcache_fsm = DCACHE_CC_CHECK; 3539 3620 r_dcache_fsm_save = r_dcache_fsm; 3540 m_cost_data_waste_wait_frz++;3541 3621 break; 3542 3622 } … … 3549 3629 r_dcache_cleanup_req = r_dcache.inval(dpaddr); 3550 3630 r_dcache_cleanup_type = CACHE_CLEANUP; 3631 m_cpt_cc_cleanup_data++; 3551 3632 r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2); 3552 3633 r_dcache_fsm = DCACHE_IDLE; … … 3569 3650 case DCACHE_MISS_WAIT: 3570 3651 { 3652 if (dreq.valid) m_cost_data_miss_frz++; 3571 3653 // external cache invalidate request 3572 3654 if ( r_tgt_dcache_req ) … … 3574 3656 r_dcache_fsm = DCACHE_CC_CHECK; 3575 3657 r_dcache_fsm_save = r_dcache_fsm; 3576 m_cost_cc_wait_frz++;3577 3658 break; 3578 3659 } … … 3596 3677 r_dcache_cleanup_req = true; 3597 3678 r_dcache_cleanup_type = CACHE_CLEANUP; 3679 m_cpt_cc_cleanup_data++; 3598 3680 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 3599 3681 r_dcache_fsm = DCACHE_IDLE; … … 3608 3690 r_dcache_cleanup_req = true; 3609 3691 r_dcache_cleanup_type = CACHE_CLEANUP; 3692 m_cpt_cc_cleanup_data++; 3610 3693 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 3611 3694 r_dcache_fsm = DCACHE_IDLE; … … 3621 3704 case DCACHE_MISS_UPDT: 3622 3705 { 3706 if (dreq.valid) m_cost_data_miss_frz++; 3623 3707 // external cache invalidate request 3624 3708 if ( r_tgt_dcache_req ) … … 3634 3718 r_dcache_cleanup_req = true; 3635 3719 r_dcache_cleanup_type = CACHE_CLEANUP; 3720 m_cpt_cc_cleanup_data++; 3636 3721 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 3637 3722 r_dcache_inval_tlb_rsp = false; … … 3647 3732 r_dcache_cleanup_req = true; 3648 3733 r_dcache_cleanup_type = CACHE_CLEANUP; 3734 m_cpt_cc_cleanup_data++; 3649 3735 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2); 3650 3736 r_dcache_inval_rsp = false; 3651 3737 r_dcache_fsm = DCACHE_IDLE; 3652 m_cost_data_tlb_miss_frz++;3653 3738 break; 3654 3739 } … … 3657 3742 { 3658 3743 paddr_t victim_index = 0; 3744 m_cpt_dcache_data_write++; 3745 m_cpt_dcache_dir_write++; 3659 3746 r_dcache_cleanup_req = r_dcache.update(r_dcache_paddr_save.read(), r_dcache_miss_buf, &victim_index); 3660 3747 r_dcache_cleanup_line = victim_index; 3661 3748 r_dcache_cleanup_type = CACHE_CLEANUP; 3749 m_cpt_cc_cleanup_data++; 3662 3750 r_dcache_fsm = DCACHE_IDLE; 3663 3751 } … … 3667 3755 case DCACHE_UNC_WAIT: 3668 3756 { 3757 if ( dreq.valid ) m_cost_unc_read_frz++; 3669 3758 // external cache invalidate request 3670 3759 if ( r_tgt_dcache_req ) … … 3697 3786 r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save); 3698 3787 r_dcache_cleanup_type = CACHE_CLEANUP; 3788 m_cpt_cc_cleanup_data++; 3699 3789 r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2); 3700 3790 } … … 3708 3798 case DCACHE_WRITE_UPDT: 3709 3799 { 3800 m_cpt_dcache_data_write++; 3710 3801 bool write_hit = false; 3711 3802 data_t mask = vci_param::be2mask(r_dcache_be_save.read()); … … 3716 3807 if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) ) 3717 3808 { 3809 m_cpt_data_tlb_update_dirty++; 3810 m_cost_data_tlb_update_dirty_frz++; 3718 3811 if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) ) // 2M page size, one level page table 3719 3812 { … … 3722 3815 r_dcache_tlb_ll_dirty_req = true; 3723 3816 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3724 m_cpt_data_tlb_write_dirty++;3725 3817 } 3726 3818 else … … 3732 3824 r_dcache_tlb_ll_dirty_req = true; 3733 3825 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3734 m_cpt_data_tlb_write_dirty++;3735 3826 } 3736 3827 else … … 3756 3847 case DCACHE_WRITE_DIRTY: 3757 3848 { 3758 m_cost_data_tlb_ miss_frz++;3849 m_cost_data_tlb_update_dirty_frz++; 3759 3850 3760 3851 // external cache invalidate request … … 3763 3854 r_dcache_fsm = DCACHE_CC_CHECK; 3764 3855 r_dcache_fsm_save = r_dcache_fsm; 3765 //m_cost_data_waste_wait_frz++;3766 3856 break; 3767 3857 } … … 3795 3885 m_cpt_dcache_data_read += m_dcache_ways; 3796 3886 3797 m_cost_cc_wait_frz++; 3887 /* activity counter */ 3888 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 3889 { 3890 m_cost_data_miss_frz++; 3891 } 3892 if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 3893 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 3894 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 3895 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 3896 { 3897 m_cost_data_tlb_miss_frz++; 3898 } 3798 3899 3799 3900 if(( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/ … … 3841 3942 case DCACHE_CC_UPDT: // update directory and data cache 3842 3943 { 3944 /* activity counter */ 3945 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 3946 { 3947 m_cost_data_miss_frz++; 3948 } 3949 if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 3950 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 3951 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 3952 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 3953 { 3954 m_cost_data_tlb_miss_frz++; 3955 } 3956 3843 3957 m_cpt_dcache_dir_write++; 3844 3958 m_cpt_dcache_data_write++; 3845 m_cost_cc_wait_frz++;3846 3959 3847 3960 data_t* buf = r_tgt_buf; … … 3858 3971 case DCACHE_CC_INVAL: // invalidate a cache line 3859 3972 { 3860 m_cost_cc_wait_frz++; 3973 /* activity counter */ 3974 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 3975 { 3976 m_cost_data_miss_frz++; 3977 } 3978 if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 3979 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 3980 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 3981 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 3982 { 3983 m_cost_data_tlb_miss_frz++; 3984 } 3985 3861 3986 r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read()); 3862 3987 if ( r_tgt_broadcast ) … … 3875 4000 case DCACHE_CC_NOP: // no external hit 3876 4001 { 3877 m_cost_cc_wait_frz++; 4002 /* activity counter */ 4003 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4004 { 4005 m_cost_data_miss_frz++; 4006 } 4007 if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4008 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4009 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4010 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4011 { 4012 m_cost_data_tlb_miss_frz++; 4013 } 4014 3878 4015 r_tgt_dcache_rsp = r_tgt_update; 3879 4016 if ( r_tgt_broadcast ) … … 3892 4029 case DCACHE_TLB_CC_INVAL: 3893 4030 { 4031 /* activity counter */ 4032 if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) ) 4033 { 4034 m_cost_data_miss_frz++; 4035 } 4036 if( (( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4037 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4038 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4039 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )) && (dreq.valid) ) 4040 { 4041 m_cost_data_tlb_miss_frz++; 4042 } 4043 3894 4044 paddr_t dcache_tlb_nline = 0; 3895 if ( dreq.valid ) m_cost_data_tlb_miss_frz++;3896 4045 3897 4046 if ( r_dcache_tlb_inval_req ) break; … … 4052 4201 { 4053 4202 r_vci_cmd_fsm = CMD_INS_CLEANUP; 4203 m_cpt_icleanup_transaction++; 4054 4204 } 4055 4205 else if (r_dcache_cleanup_req) 4056 4206 { 4057 4207 r_vci_cmd_fsm = CMD_DATA_CLEANUP; 4208 m_cpt_dcleanup_transaction++; 4058 4209 } 4059 4210 else if (r_icache_tlb_read_req) … … 4065 4216 { 4066 4217 r_vci_cmd_fsm = CMD_ITLB_ACC_LL; 4067 //m_cpt_itlb_write_transaction++;4218 m_cpt_itlb_ll_transaction++; 4068 4219 } 4069 4220 else if (r_icache_tlb_sc_req) 4070 4221 { 4071 4222 r_vci_cmd_fsm = CMD_ITLB_ACC_SC; 4072 //m_cpt_itlb_write_transaction++;4223 m_cpt_itlb_sc_transaction++; 4073 4224 } 4074 4225 else if (r_icache_miss_req) … … 4080 4231 { 4081 4232 r_vci_cmd_fsm = CMD_INS_UNC; 4082 m_cpt_i miss_transaction++;4233 m_cpt_icache_unc_transaction++; 4083 4234 } 4084 4235 else if (r_dcache_tlb_read_req) … … 4090 4241 { 4091 4242 r_vci_cmd_fsm = CMD_DTLB_ACC_LL; 4092 m_cpt_dtlb_ write_transaction++;4243 m_cpt_dtlb_ll_transaction++; 4093 4244 } 4094 4245 else if (r_dcache_tlb_sc_acc_req) 4095 4246 { 4096 4247 r_vci_cmd_fsm = CMD_DTLB_ACC_SC; 4097 m_cpt_dtlb_ write_transaction++;4248 m_cpt_dtlb_sc_transaction++; 4098 4249 } 4099 4250 else if (r_dcache_tlb_ll_dirty_req) 4100 4251 { 4101 4252 r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL; 4102 m_cpt_dtlb_ write_transaction++;4253 m_cpt_dtlb_ll_dirty_transaction++; 4103 4254 } 4104 4255 else if (r_dcache_tlb_sc_dirty_req) 4105 4256 { 4106 4257 r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC; 4107 m_cpt_dtlb_ write_transaction++;4258 m_cpt_dtlb_sc_dirty_transaction++; 4108 4259 } 4109 4260 else if (r_dcache_write_req) … … 4249 4400 "illegal VCI response packet for data read uncached"); 4250 4401 } 4251 /*4252 4402 else 4253 4403 { … … 4255 4405 "The VCI response packet for instruction miss is too short"); 4256 4406 } 4257 */ 4407 4258 4408 r_icache_tlb_read_req = false; 4259 4409 r_icache_tlb_first_req = false; … … 4267 4417 4268 4418 case RSP_ITLB_ACC_LL: 4419 m_cost_itlb_ll_transaction++; 4269 4420 if ( ! p_vci_ini_rw.rspval.read() ) 4270 4421 break; … … 4286 4437 4287 4438 case RSP_ITLB_ACC_SC: 4439 m_cost_itlb_sc_transaction++; 4288 4440 if ( ! p_vci_ini_rw.rspval.read() ) 4289 4441 break; … … 4328 4480 4329 4481 case RSP_INS_UNC: 4330 m_cost_i miss_transaction++;4482 m_cost_icache_unc_transaction++; 4331 4483 if ( ! p_vci_ini_rw.rspval.read() ) 4332 4484 break; … … 4360 4512 "illegal VCI response packet for data read uncached"); 4361 4513 } 4362 /*4363 4514 else 4364 4515 { … … 4366 4517 "The VCI response packet for instruction miss is too short"); 4367 4518 } 4368 */ 4519 4369 4520 r_dcache_tlb_read_req = false; 4370 4521 r_dcache_tlb_first_req = false; … … 4378 4529 4379 4530 case RSP_DTLB_ACC_LL: 4531 m_cost_dtlb_ll_transaction++; 4380 4532 if ( ! p_vci_ini_rw.rspval.read() ) 4381 4533 break; … … 4397 4549 4398 4550 case RSP_DTLB_ACC_SC: 4551 m_cost_dtlb_sc_transaction++; 4399 4552 if ( ! p_vci_ini_rw.rspval.read() ) 4400 4553 break; … … 4416 4569 4417 4570 case RSP_DTLB_DIRTY_LL: 4571 m_cost_dtlb_ll_dirty_transaction++; 4418 4572 if ( ! p_vci_ini_rw.rspval.read() ) 4419 4573 break; … … 4435 4589 4436 4590 case RSP_DTLB_DIRTY_SC: 4591 m_cost_dtlb_sc_dirty_transaction++; 4437 4592 if ( ! p_vci_ini_rw.rspval.read() ) 4438 4593 break; … … 4515 4670 case RSP_INS_CLEANUP: 4516 4671 case RSP_DATA_CLEANUP: 4672 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 4673 { 4674 m_cost_icleanup_transaction++; 4675 } 4676 else 4677 { 4678 m_cost_dcleanup_transaction++; 4679 } 4680 4517 4681 if ( ! p_vci_ini_c.rspval.read() ) 4518 4682 break;
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