Ignore:
Timestamp:
Sep 16, 2013, 4:27:16 PM (9 years ago)
Author:
haoliu
Message:

bug fixed in the component memcache(RWT):
There was some confusions when use the ivt and upt table

File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r495 r525  
    19251925#if DEBUG_MEMC_CONFIG
    19261926if(m_debug)
    1927           m_trt.print(0);
    19281927std::cout << "  <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:"
    19291928          << " address = " << std::hex << r_config_address.read()
     
    23332332                  << "CC_SEND req = " << r_read_to_cc_send_req.read() << std::endl
    23342333                  << "CLENAUP req = " <<r_read_to_cleanup_req.read() << std::endl;*/
    2335         if(m_upt.search_inval(nline, index) or m_upt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
     2334        if(m_ivt.search_inval(nline, index) or m_ivt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
    23362335        {
    23372336          r_read_fsm = READ_WAIT;
     
    23632362          //std::cout << "cleanup req (read) on line " << nline << " /on proc " << r_read_copy.read() << std::endl;
    23642363
    2365           m_upt.set(false,  // it's an inval transaction
    2366                           false,     // it's not a broadcast
    2367                           false,     // it needs a read response
    2368                           false,     // no acknowledge required
    2369                           m_cmd_read_srcid_fifo.read(),
    2370                           m_cmd_read_trdid_fifo.read(),
    2371                           m_cmd_read_pktid_fifo.read(),
    2372                           nline,
    2373                           0x1, //Expect only one answer
    2374                           index);
     2364          m_ivt.set(false,     // it's an inval transaction
     2365                    false,     // it's not a broadcast
     2366                    false,     // it needs a read response
     2367                    false,     // no acknowledge required
     2368                    m_cmd_read_srcid_fifo.read(),
     2369                    m_cmd_read_trdid_fifo.read(),
     2370                    m_cmd_read_pktid_fifo.read(),
     2371                    nline,
     2372                    0x1, //Expect only one answer
     2373                    index);
    23752374
    23762375          cmd_read_fifo_get = true;
     
    27872786#if DEBUG_MEMC_READ
    27882787if(m_debug)
    2789           m_trt.print(0);
    27902788std::cout << "  <MEMC " << name() << " READ_TRT_SET> Set a GET in TGT:"
    27912789          << " address = " << std::hex << m_cmd_read_addr_fifo.read()
     
    30893087
    30903088        //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl;
    3091 
    3092         match_inval = m_upt.search_inval(nline, index);
     3089        //if there is a matched updt req, we should wait until it is over. Because
     3090        //we need the lastest updt data.
     3091        match_inval = m_ivt.search_inval(nline, index);
     3092       
    30933093        assert ((r_write_count.read() == 1) and "NCC to CC req without copy");
    30943094        if(!match_inval and !r_write_to_cc_send_req.read())
     
    31003100          r_write_to_cleanup_nline = nline;
    31013101
    3102           m_upt.set(false,  // it's an inval transaction
    3103                           false,     // it's not a broadcast
    3104                           true,      // it needs no read response
    3105                           false,     // no acknowledge required
    3106                           m_cmd_write_srcid_fifo.read(), //never read, used for debug
    3107                           m_cmd_write_trdid_fifo.read(), //never read, used for debug
    3108                           m_cmd_write_pktid_fifo.read(), //never read, used for debug
    3109                           nline,
    3110                           0x1, //Expect only one answer
    3111                           index);
     3102          m_ivt.set(false,  // it's an inval transaction
     3103                    false,     // it's not a broadcast
     3104                    true,      // it needs no read response
     3105                    false,     // no acknowledge required
     3106                    m_cmd_write_srcid_fifo.read(), //never read, used for debug
     3107                    m_cmd_write_trdid_fifo.read(), //never read, used for debug
     3108                    m_cmd_write_pktid_fifo.read(), //never read, used for debug
     3109                    nline,
     3110                    0x1, //Expect only one answer
     3111                    index);
    31123112        }
    31133113        r_write_fsm = WRITE_WAIT;
     
    31593159      // owner is true when the  the first registered copy is the writer itself
    31603160      bool owner = (((r_write_copy.read() == r_write_srcid.read())
    3161 #if L1_MULTI_CACHE
    3162                      and(r_write_copy_cache.read() ==r_write_pktid.read())
    3163 #endif
    31643161                    ) and not r_write_copy_inst.read());
    31653162
     
    35403537    }
    35413538    ///////////////////////// RWT
    3542     case WRITE_MISS_IVT_LOCK: // Miss : check UPT
     3539    case WRITE_MISS_IVT_LOCK:
    35433540    {
    35443541      if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
    35453542      {
    35463543        size_t index;
    3547         if(m_upt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))
     3544        if(m_ivt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))
    35483545        {
    35493546          r_write_fsm = WRITE_WAIT;
     
    36263623        }
    36273624        m_trt.set(r_write_trt_index.read(),
    3628                               true,     // read request to XRAM
    3629                               m_nline[(addr_t)(r_write_address.read())],
    3630                               r_write_srcid.read(),
    3631                               r_write_trdid.read(),
    3632                               r_write_pktid.read(),
    3633                               false,      // not a processor read
    3634                               0,        // not a single word
    3635                               0,            // word index
    3636                               be_vector,
    3637                               data_vector);
     3625                  true,     // read request to XRAM
     3626                  m_nline[(addr_t)(r_write_address.read())],
     3627                  r_write_srcid.read(),
     3628                  r_write_trdid.read(),
     3629                  r_write_pktid.read(),
     3630                  false,      // not a processor read
     3631                  0,        // not a single word
     3632                  0,            // word index
     3633                  be_vector,
     3634                  data_vector);
    36383635        r_write_fsm = WRITE_MISS_XRAM_REQ;
    36393636
    36403637#if DEBUG_MEMC_WRITE
    36413638if(m_debug)
    3642         m_trt.print(0);
    36433639std::cout << "  <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
    36443640#endif
     
    38533849#if DEBUG_MEMC_WRITE
    38543850if(m_debug)
    3855           m_trt.print(0);
    38563851std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
    38573852          << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
     
    47384733 #if DEBUG_MEMC_XRAM_RSP
    47394734if(m_debug)
    4740             m_trt.print(0);
    47414735std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>"
    47424736          << " Set TRT entry for the put transaction"
     
    47444738#endif
    47454739       
    4746         if( not r_xram_rsp_victim_coherent )
    4747             std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl;
     4740//        if( not r_xram_rsp_victim_coherent )
     4741//            std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl;
    47484742        if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
    47494743        else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
     
    53685362        bool   match_inval;
    53695363
    5370         match_inval = m_upt.search_inval(r_cleanup_nline.read(), index);
     5364        match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index);
    53715365        assert (match_inval && "VCI MEM CACHE ERROR: In CLEANUP_IVT_LOCK_DATA, NO CORRESPONDING INVAL");
    5372         r_cleanup_read_srcid    = m_upt.srcid(index);
    5373         r_cleanup_read_trdid    = m_upt.trdid(index);
    5374         r_cleanup_read_pktid    = 0x0 + m_upt.pktid(index);
    5375         r_cleanup_read_need_rsp = !m_upt.need_rsp(index);
     5366        r_cleanup_read_srcid    = m_ivt.srcid(index);
     5367        r_cleanup_read_trdid    = m_ivt.trdid(index);
     5368        r_cleanup_read_pktid    = 0x0 + m_ivt.pktid(index);
     5369        r_cleanup_read_need_rsp = !m_ivt.need_rsp(index);
    53765370        r_cleanup_index         = index;
    53775371
     
    53935387    case CLEANUP_IVT_CLEAR_DATA://RWT
    53945388    {
    5395       m_upt.clear(r_cleanup_index.read());
     5389      m_ivt.clear(r_cleanup_index.read());
    53965390      assert ((r_cleanup_read_need_rsp.read() == (r_read_to_cleanup_req.read() && (r_cleanup_nline.read() == r_read_to_cleanup_nline.read()))) && "condition pending read");
    53975391      if (r_cleanup_read_need_rsp.read())
     
    58965890      if(m_debug)
    58975891      {
    5898         m_trt.print(0);
    58995892        std::cout
    59005893            << "  <MEMC " << name()
     
    65536546#if DEBUG_MEMC_CAS
    65546547if(m_debug)
    6555         m_trt.print(0);
    65566548std::cout << "  <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:"
    65576549          << " address = " << m_cmd_cas_addr_fifo.read() << std::endl;
     
    67146706        if(m_debug)
    67156707        {
    6716           m_trt.print(0);
    67176708          std::cout << "  <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
    67186709                    << " / nline = " << m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]
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