Ignore:
Timestamp:
Oct 30, 2013, 11:03:43 AM (11 years ago)
Author:
alain
Message:

Introducing CP2 registers mnemonics in mips32_registers.h
Supporting 40 bits physical addresses, multi-clusters TSAR
architectures: XICUs are accessed using the physical address
extension mechanism.

File:
1 edited

Legend:

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Added
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  • trunk/softs/tsar_boot/include/mips32_registers.h

    r292 r567  
    5454#define CP0_EBASE       $15,1
    5555
     56/* CP2 registers */
     57
     58#define CP2_PTPR             $0
     59#define CP2_MODE             $1
     60#define CP2_ICACHE_FLUSH     $2
     61#define CP2_DCACHE_FLUSH     $3
     62#define CP2_ITLB_INVAL       $4
     63#define CP2_DTLB_INVAL       $5
     64#define CP2_ICACHE_INVAL     $6
     65#define CP2_DCACHE_INVAL     $7
     66#define CP2_ICACHE_PREFETCH  $8
     67#define CP2_DCACHE_PREFETCH  $9
     68#define CP2_SYNC             $10
     69#define CP2_IETR             $11
     70#define CP2_DETR             $12
     71#define CP2_IBVAR            $13
     72#define CP2_DBVAR            $14
     73#define CP2_PARAMS           $15
     74#define CP2_RELEASE          $16
     75#define CP2_DATA_LO          $17     
     76#define CP2_DATA_HI          $18         
     77#define CP2_ICACHE_INVAL_PA  $19         
     78#define CP2_DCACHE_INVAL_PA  $20
     79#define CP2_PADDR_EXT        $24
     80
    5681#endif
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