Ignore:
Timestamp:
Oct 30, 2013, 11:19:23 AM (11 years ago)
Author:
cfuguet
Message:

Adding support for TSAR platforms using the vci_io_bridge component.

In this case (USE_IOB=1), when a block is read from the disk controller,
the buffer containing the read data must be invalidated in the Memory
Cache as the transfer is done between the disk controller and the RAM.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/softs/tsar_boot/src/boot_ioc.c

    r554 r568  
    145145// SOCLIB version of the boot_ioc_read function
    146146
     147void boot_buf_invalidate (
     148        const void * buffer,
     149        unsigned int line_size,
     150        unsigned int size);
     151
     152void boot_mcc_invalidate (
     153        const void * buffer,
     154        unsigned int size);
     155
    147156int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count)
    148157{
     
    179188    _boot_ioc_completed();
    180189
    181 #if (CACHE_COHERENCE == 0)
    182     boot_dbuf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
     190#if (CACHE_COHERENCE == 0) || (USE_IOB == 1)
     191    boot_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
     192#endif
     193
     194#if (USE_IOB == 1)
     195    boot_mcc_invalidate(buffer, count * 512);
    183196#endif
    184197
     
    252265 * buffer (identified by an address and a size).
    253266 */
    254 #if (CACHE_COHERENCE == 0)
    255 void boot_dbuf_invalidate (
     267#if (CACHE_COHERENCE == 0) || (USE_IOB == 1)
     268void boot_buf_invalidate (
    256269        const void * buffer,
    257270        unsigned int line_size,
     
    271284#endif
    272285
     286/**
     287 * boot_mcc_inval()
     288 *
     289 * Invalidate all data cache lines corresponding to a memory
     290 * buffer (identified by an address and a size).
     291 */
     292#if (USE_IOB == 1)
     293void boot_mcc_invalidate (
     294        const void * buffer,
     295        unsigned int size)
     296{
     297    unsigned int * mcc_address = (unsigned int *)MCC_BASE;
     298
     299    // get the hard lock assuring exclusive access to MEMC
     300    while (ioread32(&mcc_address[MCC_LOCK]));
     301
     302    // write invalidate paremeters on the memory cache
     303    // this preloader use only the cluster 0 and then the HI bits are not used
     304   
     305    iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer);
     306    iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0);
     307    iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size);
     308    iowrite32(&mcc_address[MCC_CMD]    , (unsigned int) MCC_CMD_INVAL);
     309
     310    // release the lock protecting MEMC
     311    iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0);
     312}
     313#endif
     314
    273315/*
    274316 * vim: tabstop=4 : shiftwidth=4 : expandtab
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