Changeset 693 for trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
- Timestamp:
- May 17, 2014, 11:54:12 AM (10 years ago)
- File:
-
- 1 edited
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trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r607 r693 22 22 #include "vci_simple_ram.h" 23 23 #include "vci_xicu.h" 24 #include "vci_local_crossbar.h" 24 25 #include "dspin_local_crossbar.h" 25 26 #include "vci_dspin_initiator_wrapper.h" … … 32 33 #include "vci_io_bridge.h" 33 34 34 namespace soclib { namespace caba 35 namespace soclib { namespace caba { 35 36 36 37 /////////////////////////////////////////////////////////////////////////// … … 48 49 public: 49 50 50 51 sc_in<bool> 52 sc_in<bool> 51 // Ports 52 sc_in<bool> p_clk; 53 sc_in<bool> p_resetn; 53 54 54 55 // Thes two ports are used to connect IOB to IOX nework in top cell … … 64 65 65 66 // These arrays of ports are used to connect the INT & RAM networks in top cell 66 67 67 soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; 68 soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; 68 69 soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; 69 70 soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; 70 71 71 72 72 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; 73 soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; 73 74 soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; 74 75 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; 75 76 76 77 // interrupt signals 77 sc_signal<bool> signal_false; 78 sc_signal<bool> signal_proc_it[8]; 79 sc_signal<bool> signal_irq_mdma[8]; 80 sc_signal<bool> signal_irq_memc; 81 82 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 83 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 84 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 85 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 86 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 87 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 88 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 89 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 90 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 91 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 92 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 93 94 // INT network VCI signals between VCI components and VCI/DSPIN wrappers 95 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 96 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 97 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 98 99 VciSignals<vci_param_int> signal_int_vci_tgt_memc; 100 VciSignals<vci_param_int> signal_int_vci_tgt_xicu; 101 VciSignals<vci_param_int> signal_int_vci_tgt_mdma; 102 VciSignals<vci_param_int> signal_int_vci_tgt_iobx; 103 104 // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN wrappers 105 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8]; 106 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8]; 107 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i; 108 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i; 109 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i; 110 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i; 111 112 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t; 113 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t; 114 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t; 115 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t; 116 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t; 117 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t; 118 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t; 119 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t; 120 121 // Coherence DSPIN signals between DSPIN local crossbars and CC components 122 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 123 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; 124 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; 125 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; 126 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; 127 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; 128 129 // RAM network VCI signals between VCI components and VCI/DSPIN wrappers 130 VciSignals<vci_param_ext> signal_ram_vci_ini_memc; 131 VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; 132 VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; 78 sc_signal<bool> signal_false; 79 sc_signal<bool> signal_proc_it[8]; 80 sc_signal<bool> signal_irq_mdma[8]; 81 sc_signal<bool> signal_irq_memc; 82 83 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 84 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 85 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 86 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 87 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 88 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 89 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 90 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 91 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 92 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 93 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 94 95 // INT network VCI signals between VCI components and VCI local crossbar 96 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 97 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 98 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 99 100 VciSignals<vci_param_int> signal_int_vci_tgt_memc; 101 VciSignals<vci_param_int> signal_int_vci_tgt_xicu; 102 VciSignals<vci_param_int> signal_int_vci_tgt_mdma; 103 VciSignals<vci_param_int> signal_int_vci_tgt_iobx; 104 105 VciSignals<vci_param_int> signal_int_vci_l2g; 106 VciSignals<vci_param_int> signal_int_vci_g2l; 107 108 // Coherence DSPIN signals between DSPIN local crossbars and CC components 109 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 110 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; 111 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; 112 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; 113 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; 114 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; 115 116 // RAM network VCI signals between VCI components and VCI/DSPIN wrappers 117 VciSignals<vci_param_ext> signal_ram_vci_ini_memc; 118 VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; 119 VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; 133 120 134 121 // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 135 136 137 138 122 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 123 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; 124 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; 125 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; 139 126 140 127 ////////////////////////////////////// … … 146 133 GdbServer<Mips32ElIss> >* proc[8]; 147 134 148 VciDspinInitiatorWrapper<vci_param_int,149 dspin_int_cmd_width,150 dspin_int_rsp_width>* proc_wi[8];151 152 135 VciMemCache<vci_param_int, 153 136 vci_param_ext, … … 155 138 dspin_int_cmd_width>* memc; 156 139 157 VciDspinTargetWrapper<vci_param_int,158 dspin_int_cmd_width,159 dspin_int_rsp_width>* memc_int_wt;160 161 140 VciDspinInitiatorWrapper<vci_param_ext, 162 141 dspin_ram_cmd_width, 163 142 dspin_ram_rsp_width>* memc_ram_wi; 164 143 165 VciXicu<vci_param_int>* xicu; 144 VciXicu<vci_param_int>* xicu; 145 146 VciMultiDma<vci_param_int>* mdma; 147 148 VciLocalCrossbar<vci_param_int>* int_xbar_d; 149 150 VciDspinInitiatorWrapper<vci_param_int, 151 dspin_int_cmd_width, 152 dspin_int_rsp_width>* int_wi_gate_d; 166 153 167 154 VciDspinTargetWrapper<vci_param_int, 168 155 dspin_int_cmd_width, 169 dspin_int_rsp_width>* xicu_int_wt; 170 171 VciMultiDma<vci_param_int>* mdma; 172 173 VciDspinInitiatorWrapper<vci_param_int, 174 dspin_int_cmd_width, 175 dspin_int_rsp_width>* mdma_int_wi; 176 177 VciDspinTargetWrapper<vci_param_int, 178 dspin_int_cmd_width, 179 dspin_int_rsp_width>* mdma_int_wt; 180 181 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d; 182 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d; 156 dspin_int_rsp_width>* int_wt_gate_d; 157 183 158 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; 184 159 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; 185 160 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; 186 161 187 VirtualDspinRouter<dspin_int_cmd_width>* 162 VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; 188 163 VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; 189 164 … … 193 168 dspin_ram_cmd_width, 194 169 dspin_ram_rsp_width>* xram_ram_wt; 195 196 DspinRouterTsar<dspin_ram_cmd_width>* 170 171 DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; 197 172 DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; 198 173 199 174 // IO Network Components (not instanciated in all clusters) 200 175 201 176 VciIoBridge<vci_param_int, 202 177 vci_param_ext>* iob; 203 204 VciDspinInitiatorWrapper<vci_param_int,205 dspin_int_cmd_width,206 dspin_int_rsp_width>* iob_int_wi;207 208 VciDspinTargetWrapper<vci_param_int,209 dspin_int_cmd_width,210 dspin_int_rsp_width>* iob_int_wt;211 178 212 179 VciDspinInitiatorWrapper<vci_param_ext, 213 180 dspin_ram_cmd_width, 214 181 dspin_ram_rsp_width>* iob_ram_wi; 215 182 216 183 // cluster constructor 217 184 TsarIobCluster( sc_module_name insname, 218 185 size_t nb_procs, 219 186 size_t nb_dmas, … … 227 194 const soclib::common::MappingTable &mt_iox, 228 195 229 size_t 230 size_t 231 size_t 232 233 size_t 234 size_t 235 size_t 236 size_t 196 size_t x_width, // x field bits 197 size_t y_width, // y field bits 198 size_t l_width, // l field bits 199 200 size_t int_memc_tgtid, 201 size_t int_xicu_tgtid, 202 size_t int_mdma_tgtid, 203 size_t int_iobx_tgtid, 237 204 238 205 size_t int_proc_srcid, … … 250 217 size_t l1_i_sets, 251 218 size_t l1_d_ways, 252 size_t l1_d_sets, 219 size_t l1_d_sets, 253 220 size_t xram_latency, 254 221
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