Changeset 767 for branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

Timestamp:

Aug 25, 2014, 5:58:16 PM (10 years ago)

Author:

devigne

Message:

RWT commit :

• Merge with trunk.

• Cosmetic

• Bugfix in state WRITE_IVT_LOCK_HIT_WB.

MemCache? records invalidation in IVT in this state but we do not check that
the IVT was full. Thus invalidation was issued without actually recorded in the
query IVT ...

• Bugfix :

When a NCC line owned by a L1 cache with srcid != 0 was removed from MemCache?,
the owner field was reset to 0. If this same L1 cache was sending a read to
retrieve this line the MemCache? sent this line on CC mode.

• Bugfix :

The MemCache? reset the 'inst' field to 0 when solving a
invalidation due to a change of state of line (NCC to CC).
But a line can be NCC (ie contained in a DATA cache) then asked by INST cache,
this read triggers a transition NCC to CC but we must save the nature of this read.
Now this information is stored in a register (r_read_to_cleanup_inst).

• Add a counter for the number of minimum inputs available

in the heap. This counter indicates whether the heap size of 4096 is relevant.

File:

• branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h (modified) (2 diffs)

branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -426 +426 @@
     void write_rsp(const size_t      index,
                    const size_t      word,
-                   const wide_data_t data)
+                   const wide_data_t data,
+                   const bool        rerror)
     {
         data_t  value;
@@ -442 +443 @@
         assert( (tab[index].xram_read ) and
         "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
+
+        if ( rerror )
+        {
+            tab[index].rerror = true;
+            return;
+        }
 
         // first 32 bits word