Changeset 806 for branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
- Timestamp:
- Sep 17, 2014, 1:17:56 PM (10 years ago)
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branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r748 r806 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.h 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 … … 37 37 38 38 /////////////////////////////////////////////////////////////////////////// 39 template<typename vci_param_int, 39 template<typename vci_param_int, 40 40 typename vci_param_ext, 41 size_t dspin_int_cmd_width, 41 size_t dspin_int_cmd_width, 42 42 size_t dspin_int_rsp_width, 43 43 size_t dspin_ram_cmd_width, 44 44 size_t dspin_ram_rsp_width> 45 class TsarIobCluster 45 class TsarIobCluster 46 46 /////////////////////////////////////////////////////////////////////////// 47 47 : public soclib::caba::BaseModule … … 56 56 // Thes two ports are used to connect IOB to IOX nework in top cell 57 57 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; 58 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 58 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 59 59 60 60 // These arrays of ports are used to connect the INT & RAM networks in top cell … … 74 74 sc_signal<bool> signal_irq_mdma[8]; 75 75 sc_signal<bool> signal_irq_memc; 76 76 77 77 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 78 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 79 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 78 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 79 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 80 80 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 81 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 81 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 82 82 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 83 83 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 84 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 85 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 84 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 85 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 86 86 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 87 87 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 88 88 89 89 // INT network VCI signals between VCI components and VCI local crossbar 90 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 91 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 92 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 90 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 91 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 92 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 93 93 94 94 VciSignals<vci_param_int> signal_int_vci_tgt_memc; … … 101 101 VciSignals<vci_param_int> signal_int_vci_g2l; 102 102 103 // Coherence DSPIN signals between DSPIN local crossbars and CC components 103 // Coherence DSPIN signals between DSPIN local crossbars and CC components 104 104 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 105 105 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; … … 115 115 116 116 // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar 117 // and routers 117 // and routers 118 118 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 119 119 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; … … 126 126 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false; 127 127 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false; 128 128 129 129 ////////////////////////////////////// 130 130 // Hardwate Components (pointers) 131 131 ////////////////////////////////////// 132 VciCcVCacheWrapper<vci_param_int, 132 VciCcVCacheWrapper<vci_param_int, 133 133 dspin_int_cmd_width, 134 134 dspin_int_rsp_width, … … 136 136 137 137 VciMemCache<vci_param_int, 138 vci_param_ext, 139 dspin_int_rsp_width, 138 vci_param_ext, 139 dspin_int_rsp_width, 140 140 dspin_int_cmd_width>* memc; 141 141 … … 151 151 152 152 VciLocalCrossbar<vci_param_int>* int_xbar_d; 153 153 154 154 VciDspinInitiatorWrapper<vci_param_int, 155 155 dspin_int_cmd_width, … … 172 172 dspin_ram_cmd_width, 173 173 dspin_ram_rsp_width>* xram_ram_wt; 174 174 175 175 DspinRouter<dspin_ram_cmd_width>* ram_router_cmd; 176 176 DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; … … 178 178 DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; 179 179 DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; 180 180 181 181 182 182 // IO Network Components (not instanciated in all clusters) … … 191 191 // cluster constructor 192 192 TsarIobCluster( sc_module_name insname, 193 size_t nb_procs, 194 size_t nb_dmas, 193 size_t nb_procs, 194 size_t nb_dmas, 195 195 size_t x, // x coordinate 196 196 size_t y, // y coordinate 197 size_t xmax, 198 size_t ymax, 197 size_t x_size, 198 size_t y_size, 199 200 size_t p_width, // pid field bits 199 201 200 202 const soclib::common::MappingTable &mt_int, … … 226 228 size_t memc_sets, 227 229 size_t l1_i_ways, 228 size_t l1_i_sets, 230 size_t l1_i_sets, 229 231 size_t l1_d_ways, 230 size_t l1_d_sets, 231 size_t xram_latency, 232 size_t l1_d_sets, 233 size_t xram_latency, 232 234 size_t xcu_nb_inputs, 233 235 … … 236 238 const Loader &loader, // loader for XRAM 237 239 238 uint32_t frozen_cycles, 240 uint32_t frozen_cycles, 239 241 uint32_t start_debug_cycle, 240 bool memc_debug_ok, 241 bool proc_debug_ok, 242 bool iob0_debug_ok ); 242 bool memc_debug_ok, 243 bool proc_debug_ok, 244 bool iob0_debug_ok ); 243 245 244 246 protected: … … 247 249 248 250 void init(); 249 251 250 252 251 253 };
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