- Timestamp:
- Sep 24, 2014, 3:48:50 PM (10 years ago)
- Location:
- branches/RWT/modules/vci_mem_cache
- Files:
-
- 2 edited
-
. (modified) (1 prop)
-
caba/source/src/vci_mem_cache.cpp (modified) (133 diffs)
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branches/RWT/modules/vci_mem_cache
- Property svn:mergeinfo changed
/trunk/modules/vci_mem_cache (added) merged: 597,599,601,603,605,617
- Property svn:mergeinfo changed
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branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r787 r814 135 135 "MULTI_ACK_UPT_LOCK", 136 136 "MULTI_ACK_UPT_CLEAR", 137 "MULTI_ACK_WRITE_RSP" ,137 "MULTI_ACK_WRITE_RSP" 138 138 }; 139 139 const char *config_fsm_str[] = … … 496 496 #if MONITOR_MEMCACHE_FSM == 1 497 497 , 498 p_read_fsm("p_read_fsm"), 499 p_write_fsm("p_write_fsm"), 500 p_xram_rsp_fsm("p_xram_rsp_fsm"), 501 p_cas_fsm("p_cas_fsm"), 502 p_cleanup_fsm("p_cleanup_fsm"), 503 p_config_fsm("p_config_fsm"), 504 p_alloc_heap_fsm("p_alloc_heap_fsm"), 505 p_alloc_dir_fsm("p_alloc_dir_fsm"), 506 p_alloc_trt_fsm("p_alloc_trt_fsm"), 507 p_alloc_upt_fsm("p_alloc_upt_fsm"), 508 p_alloc_ivt_fsm("p_alloc_ivt_fsm"), 509 p_tgt_cmd_fsm("p_tgt_cmd_fsm"), 510 p_tgt_rsp_fsm("p_tgt_rsp_fsm"), 511 p_ixr_cmd_fsm("p_ixr_cmd_fsm"), 512 p_ixr_rsp_fsm("p_ixr_rsp_fsm"), 513 p_cc_send_fsm("p_cc_send_fsm"), 498 p_read_fsm("p_read_fsm"), 499 p_write_fsm("p_write_fsm"), 500 p_xram_rsp_fsm("p_xram_rsp_fsm"), 501 p_cas_fsm("p_cas_fsm"), 502 p_cleanup_fsm("p_cleanup_fsm"), 503 p_config_fsm("p_config_fsm"), 504 p_alloc_heap_fsm("p_alloc_heap_fsm"), 505 p_alloc_dir_fsm("p_alloc_dir_fsm"), 506 p_alloc_trt_fsm("p_alloc_trt_fsm"), 507 p_alloc_upt_fsm("p_alloc_upt_fsm"), 508 p_alloc_ivt_fsm("p_alloc_ivt_fsm"), 509 p_tgt_cmd_fsm("p_tgt_cmd_fsm"), 510 p_tgt_rsp_fsm("p_tgt_rsp_fsm"), 511 p_ixr_cmd_fsm("p_ixr_cmd_fsm"), 512 p_ixr_rsp_fsm("p_ixr_rsp_fsm"), 513 p_cc_send_fsm("p_cc_send_fsm"), 514 514 p_cc_receive_fsm("p_cc_receive_fsm"), 515 515 p_multi_ack_fsm("p_multi_ack_fsm") … … 629 629 { 630 630 m_debug_data[word] = m_cache_data.read(way, set, word); 631 if ( m_debug_previous_valid and 631 if ( m_debug_previous_valid and 632 632 (m_debug_data[word] != m_debug_previous_data[word]) ) 633 633 { … … 647 647 << " / VAL = " << std::dec << entry.valid 648 648 << " / WAY = " << way 649 << " / COUNT = " << entry.count 649 << " / COUNT = " << entry.count 650 650 << " / DIRTY = " << entry.dirty 651 << " / DATA_CHANGE = " << data_change 651 << " / DATA_CHANGE = " << data_change 652 652 << std::endl; 653 653 std::cout << std::hex << " /0:" << m_debug_data[0] … … 672 672 m_debug_previous_valid = entry.valid; 673 673 m_debug_previous_dirty = entry.dirty; 674 for( size_t word=0 ; word<m_words ; word++ ) 674 for( size_t word=0 ; word<m_words ; word++ ) 675 675 m_debug_previous_data[word] = m_debug_data[word]; 676 676 } … … 840 840 } 841 841 842 842 843 843 ///////////////////////////////////////// 844 844 tmpl(void)::reset_counters() … … 874 874 m_cpt_update_remote = 0; 875 875 m_cpt_update_cost = 0; 876 876 877 877 m_cpt_minval = 0; 878 878 m_cpt_minval_local = 0; … … 893 893 m_cpt_write_miss = 0; 894 894 m_cpt_write_dirty = 0; 895 895 896 896 m_cpt_trt_rb = 0; 897 897 m_cpt_trt_full = 0; … … 1329 1329 // The READ/WRITE commands accepted in the configuration segment are targeting 1330 1330 // configuration or status registers. They must contain one single flit. 1331 // - For almost all addressable registers, the response is returned immediately. 1331 // - For almost all addressable registers, the response is returned immediately. 1332 1332 // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. 1333 1333 //////////////////////////////////////////////////////////////////////////////////// … … 1366 1366 else r_tgt_cmd_fsm = TGT_CMD_CONFIG; 1367 1367 } 1368 else //////////// memory access 1368 else //////////// memory access 1369 1369 { 1370 1370 if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ ) … … 1411 1411 1412 1412 if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; 1413 else r_tgt_cmd_fsm = TGT_CMD_WRITE; 1413 else r_tgt_cmd_fsm = TGT_CMD_WRITE; 1414 1414 } 1415 1415 else … … 1509 1509 m_config_func_idx_mask; 1510 1510 1511 bool need_rsp; 1512 int error; 1511 bool need_rsp; 1512 int error; 1513 1513 uint32_t rdata = 0; // default value 1514 1514 uint32_t wdata = p_vci_tgt.wdata.read(); … … 1617 1617 1618 1618 break; 1619 1619 1620 1620 default: 1621 1621 error = 1; … … 1719 1719 size_t cell = (address - seg_base)/vci_param_int::B; 1720 1720 1721 bool need_rsp; 1722 size_t error; 1721 bool need_rsp; 1722 size_t error; 1723 1723 uint32_t rdata = 0; // default value 1724 uint32_t wdata = p_vci_tgt.wdata.read(); 1724 uint32_t wdata = p_vci_tgt.wdata.read(); 1725 1725 1726 1726 if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock … … 1830 1830 << " read command packet must contain one single flit" << std::endl; 1831 1831 exit(0); 1832 } 1832 } 1833 1833 // check plen for LL 1834 if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 1834 if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 1835 1835 (p_vci_tgt.plen.read() != 8) ) 1836 1836 { … … 1867 1867 } 1868 1868 else { 1869 if (is_local_req(p_vci_tgt.srcid.read())) 1869 if (is_local_req(p_vci_tgt.srcid.read())) 1870 1870 { 1871 1871 m_cpt_read_local++; … … 1910 1910 m_cpt_write_flits_local++; 1911 1911 } 1912 else 1912 else 1913 1913 { 1914 1914 m_cpt_write_flits_remote++; … … 1926 1926 m_cpt_sc_local++; 1927 1927 } 1928 else 1928 else 1929 1929 { 1930 1930 m_cpt_sc_remote++; … … 1932 1932 } 1933 1933 else { 1934 if (is_local_req(p_vci_tgt.srcid.read())) 1934 if (is_local_req(p_vci_tgt.srcid.read())) 1935 1935 { 1936 1936 m_cpt_write_local++; … … 1973 1973 if (p_vci_tgt.eop) { 1974 1974 // <Activity counters> 1975 if (is_local_req(p_vci_tgt.srcid.read())) 1975 if (is_local_req(p_vci_tgt.srcid.read())) 1976 1976 { 1977 1977 m_cpt_cas_local++; … … 1993 1993 // MULTI_ACK FSM 1994 1994 ///////////////////////////////////////////////////////////////////////// 1995 // This FSM controls the response to the multicast update requests sent 1995 // This FSM controls the response to the multicast update requests sent 1996 1996 // by the memory cache to the L1 caches and update the UPT. 1997 1997 // … … 2133 2133 ///////////////////////// 2134 2134 case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM 2135 // Wait if pending request 2135 // Wait if pending request 2136 2136 { 2137 2137 if ( r_multi_ack_to_tgt_rsp_req.read() ) break; … … 2168 2168 2169 2169 // 2170 // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 2170 // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 2171 2171 // 2172 2172 // all cache lines covered by the buffer. The various lines of a given buffer 2173 2173 // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send 2174 // the command for line (n+1). It decrements the r_config_cmd_lines counter until 2174 // the command for line (n+1). It decrements the r_config_cmd_lines counter until 2175 2175 // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). 2176 2176 // The r_config_rsp_lines counter contains the number of expected responses from … … 2180 2180 // be concurently accessed by those three FSMs, it is implemented as an [incr/decr] 2181 2181 // counter. 2182 // 2182 // 2183 2183 // - INVAL request: 2184 // For each line, it access to the DIR. 2185 // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 2184 // For each line, it access to the DIR. 2185 // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 2186 2186 // In case of hit, with no copies in L1 caches, the line is invalidated and 2187 2187 // a response is requested to TGT_RSP FSM. … … 2195 2195 // This constraint can be released, but it requires to make 2 PUT transactions 2196 2196 // for the first and the last line... 2197 // 2197 // 2198 2198 // - SYNC request: 2199 // For each line, it access to the DIR. 2200 // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 2199 // For each line, it access to the DIR. 2200 // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 2201 2201 // In case of hit, a PUT transaction is registered in TRT and a request is sent 2202 2202 // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter … … 2205 2205 // 2206 2206 // From the software point of view, a configuration request is a sequence 2207 // of 6 atomic accesses in an uncached segment. A dedicated lock is used 2207 // of 6 atomic accesses in an uncached segment. A dedicated lock is used 2208 2208 // to handle only one configuration command at a given time: 2209 2209 // - Read MEMC_LOCK : Get the lock … … 2218 2218 { 2219 2219 ///////////////// 2220 case CONFIG_IDLE: // waiting a config request 2221 { 2222 if ( r_config_cmd.read() != MEMC_CMD_NOP ) 2220 case CONFIG_IDLE: // waiting a config request 2221 { 2222 if ( r_config_cmd.read() != MEMC_CMD_NOP ) 2223 2223 { 2224 2224 r_config_fsm = CONFIG_LOOP; … … 2226 2226 #if DEBUG_MEMC_CONFIG 2227 2227 if(m_debug) 2228 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 2228 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 2229 2229 << " address = " << std::hex << r_config_address.read() 2230 2230 << " / nlines = " << std::dec << r_config_cmd_lines.read() … … 2235 2235 } 2236 2236 ///////////////// 2237 case CONFIG_LOOP: // test last line to be handled 2237 case CONFIG_LOOP: // test last line to be handled 2238 2238 { 2239 2239 if ( r_config_cmd_lines.read() == 0 ) … … 2249 2249 #if DEBUG_MEMC_CONFIG 2250 2250 if(m_debug) 2251 std::cout << " <MEMC " << name() << " CONFIG_LOOP>" 2252 << " address = " << std::hex << r_config_address.read() 2253 << " / nlines = " << std::dec << r_config_cmd_lines.read() 2251 std::cout << " <MEMC " << name() << " CONFIG_LOOP>" 2252 << " address = " << std::hex << r_config_address.read() 2253 << " / nlines = " << std::dec << r_config_cmd_lines.read() 2254 2254 << " / command = " << r_config_cmd.read() << std::endl; 2255 2255 #endif … … 2257 2257 } 2258 2258 ///////////////// 2259 case CONFIG_WAIT: // wait completion (last response) 2259 case CONFIG_WAIT: // wait completion (last response) 2260 2260 { 2261 2261 if ( r_config_rsp_lines.read() == 0 ) // last response received … … 2266 2266 #if DEBUG_MEMC_CONFIG 2267 2267 if(m_debug) 2268 std::cout << " <MEMC " << name() << " CONFIG_WAIT>" 2268 std::cout << " <MEMC " << name() << " CONFIG_WAIT>" 2269 2269 << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; 2270 2270 #endif … … 2272 2272 } 2273 2273 //////////////// 2274 case CONFIG_RSP: // request TGT_RSP FSM to return response 2274 case CONFIG_RSP: // request TGT_RSP FSM to return response 2275 2275 { 2276 2276 if ( not r_config_to_tgt_rsp_req.read() ) … … 2329 2329 2330 2330 if (entry.valid and // hit & inval command 2331 (r_config_cmd.read() == MEMC_CMD_INVAL)) 2331 (r_config_cmd.read() == MEMC_CMD_INVAL)) 2332 2332 { 2333 2333 r_config_fsm = CONFIG_IVT_LOCK; … … 2336 2336 entry.dirty and 2337 2337 (r_config_cmd.read() == MEMC_CMD_SYNC) ) 2338 { 2338 { 2339 2339 r_config_fsm = CONFIG_TRT_LOCK; 2340 2340 } 2341 else // return to LOOP 2341 else // return to LOOP 2342 2342 { 2343 2343 r_config_cmd_lines = r_config_cmd_lines.read() - 1; … … 2359 2359 ///////////////////// 2360 2360 case CONFIG_TRT_LOCK: // enter this state in case of SYNC command 2361 // to a dirty cache line 2361 // to a dirty cache line 2362 2362 // keep DIR lock, and try to get TRT lock 2363 2363 // return to LOOP state if TRT full … … 2423 2423 std::vector<data_t> data_vector; 2424 2424 data_vector.clear(); 2425 for(size_t word=0; word<m_words; word++) 2425 for(size_t word=0; word<m_words; word++) 2426 2426 { 2427 2427 uint32_t data = m_cache_data.read( way, set, word ); … … 2439 2439 0, // read_length: unused 2440 2440 0, // word_index: unused 2441 std::vector<be_t>(m_words,0xF), // byte-enable: unused 2441 std::vector<be_t>(m_words,0xF), // byte-enable: unused 2442 2442 data_vector, // data to be written 2443 2443 0, // ll_key: unused … … 2470 2470 if(m_debug) 2471 2471 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM" 2472 << " / address = " << std::hex << r_config_address.read() << std::endl; 2472 << " / address = " << std::hex << r_config_address.read() << std::endl; 2473 2473 #endif 2474 2474 } … … 2480 2480 // Return to LOOP state if IVT full. 2481 2481 // Register inval in IVT, and invalidate the 2482 // directory if IVT not full. 2482 // directory if IVT not full. 2483 2483 { 2484 2484 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and … … 2515 2515 2516 2516 wok = m_ivt.set(false, // it's an inval transaction 2517 broadcast, 2517 broadcast, 2518 2518 false, // no response required 2519 2519 true, // acknowledge required … … 2558 2558 case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM 2559 2559 { 2560 if( not r_config_to_cc_send_multi_req.read() and 2560 if( not r_config_to_cc_send_multi_req.read() and 2561 2561 not r_config_to_cc_send_brdcast_req.read() ) 2562 2562 { … … 2575 2575 if(m_debug) 2576 2576 std::cout << " <MEMC " << name() << " CONFIG_BC_SEND>" 2577 << " Post a broadcast inval request to CC_SEND FSM" 2577 << " Post a broadcast inval request to CC_SEND FSM" 2578 2578 << " / address = " << r_config_address.read() <<std::endl; 2579 2579 #endif … … 2584 2584 case CONFIG_INVAL_SEND: // Post a multi inval request to CC_SEND FSM 2585 2585 { 2586 if( not r_config_to_cc_send_multi_req.read() and 2586 if( not r_config_to_cc_send_multi_req.read() and 2587 2587 not r_config_to_cc_send_brdcast_req.read() ) 2588 2588 { … … 2612 2612 if(m_debug) 2613 2613 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 2614 << " Post multi inval request to CC_SEND FSM" 2615 << " / address = " << std::hex << r_config_address.read() 2616 << " / copy = " << r_config_dir_copy_srcid.read() 2614 << " Post multi inval request to CC_SEND FSM" 2615 << " / address = " << std::hex << r_config_address.read() 2616 << " / copy = " << r_config_dir_copy_srcid.read() 2617 2617 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; 2618 2618 #endif … … 2640 2640 { 2641 2641 HeapEntry entry = m_heap.read( r_config_heap_next.read() ); 2642 bool last_copy = (entry.next == r_config_heap_next.read()); 2642 bool last_copy = (entry.next == r_config_heap_next.read()); 2643 2643 2644 2644 config_to_cc_send_fifo_srcid = entry.owner.srcid; … … 2660 2660 if(m_debug) 2661 2661 std::cout << " <MEMC " << name() << " CONFIG_HEAP_SCAN>" 2662 << " Post multi inval request to CC_SEND FSM" 2663 << " / address = " << std::hex << r_config_address.read() 2664 << " / copy = " << entry.owner.srcid 2662 << " Post multi inval request to CC_SEND FSM" 2663 << " / address = " << std::hex << r_config_address.read() 2664 << " / copy = " << entry.owner.srcid 2665 2665 << " / inst = " << std::dec << entry.owner.inst << std::endl; 2666 2666 #endif … … 2681 2681 } 2682 2682 else 2683 { 2683 { 2684 2684 last_entry.next = free_pointer; 2685 2685 } … … 2799 2799 2800 2800 // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request) 2801 if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 2801 if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 2802 2802 { 2803 2803 // test if we need to register a new copy in the heap … … 2851 2851 { 2852 2852 std::cout 2853 << " <MEMC " << name() << " READ_IVT_LOCK>" 2853 << " <MEMC " << name() << " READ_IVT_LOCK>" 2854 2854 << " Wait cleanup completion" 2855 2855 << std::endl; … … 2862 2862 r_read_to_cc_send_dest = r_read_copy.read(); 2863 2863 r_read_to_cc_send_nline = nline; 2864 r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2864 r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2865 2865 r_read_to_cleanup_req = true; 2866 2866 r_read_to_cleanup_nline = nline; 2867 2867 r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read(); 2868 r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2868 r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 2869 2869 r_read_to_cleanup_length = m_cmd_read_length_fifo.read(); 2870 2870 r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()]; … … 2920 2920 break; 2921 2921 } 2922 /////////////////// 2922 /////////////////// 2923 2923 case READ_DIR_HIT: // read data in cache & update the directory 2924 2924 // we enter this state in 3 cases: … … 3024 3024 bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); 3025 3025 3026 if (!r_read_coherent.read()) 3027 { 3028 std::cout << "Address = " << std::hex << (m_cmd_read_addr_fifo.read()) << std::dec << " |count = " << r_read_count.read() << std::endl; 3029 } 3030 assert (r_read_coherent.read() && "accÚs au heap sur ncc"); 3026 assert (r_read_coherent.read() && "Heap access on line NCC"); 3031 3027 // read data in the cache 3032 3028 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; … … 3135 3131 m_heap.set_full(); 3136 3132 } 3137 3133 3138 3134 // <Activity counters> 3139 3135 m_cpt_heap_slot_available--; … … 3418 3414 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 3419 3415 << " / address = " << std::hex << m_cmd_write_addr_fifo.read() 3420 << " / data = " << m_cmd_write_data_fifo.read() 3421 << " / pktid = " << m_cmd_write_pktid_fifo.read() 3416 << " / data = " << m_cmd_write_data_fifo.read() 3417 << " / pktid = " << m_cmd_write_pktid_fifo.read() 3422 3418 << std::endl; 3423 3419 #endif … … 3431 3427 3432 3428 // check that the next word is in the same cache line 3433 assert((m_nline[(addr_t)(r_write_address.read())] == 3429 assert((m_nline[(addr_t)(r_write_address.read())] == 3434 3430 m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) && 3435 3431 "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); … … 3482 3478 // test address and key match of the SC command on the 3483 3479 // LL/SC table without removing reservation. The reservation 3484 // will be erased after in this FSM. 3480 // will be erased after in this FSM. 3485 3481 bool sc_success = m_llsc_table.check(r_write_address.read(), 3486 3482 r_write_sc_key.read()); … … 3493 3489 else 3494 3490 { 3495 // write burst 3491 // write burst 3496 3492 #define L2 soclib::common::uint32_log2 3497 3493 addr_t min = r_write_address.read(); … … 3594 3590 addr_t nline = m_nline[(addr_t)(r_write_address.read())]; 3595 3591 3596 //if there is a matched updt req, we should wait until it is over. Because 3592 //if there is a matched updt req, we should wait until it is over. Because 3597 3593 //we need the lastest updt data. 3598 3594 match_inval = m_ivt.search_inval(nline, index); … … 3600 3596 assert ((r_write_count.read() == 1) and "NCC to CC req without copy"); 3601 3597 3602 if( not match_inval and 3598 if( not match_inval and 3603 3599 not m_ivt.is_full() and 3604 3600 not r_write_to_cc_send_req.read() and … … 3676 3672 // no_update is true when there is no need for coherence transaction 3677 3673 bool no_update = ( (r_write_count.read() == 0) or 3678 (owner and (r_write_count.read() == 1) and 3674 (owner and (r_write_count.read() == 1) and 3679 3675 ((r_write_pktid.read() & 0x7) != TYPE_SC))); 3680 3676 … … 3682 3678 if(no_update) 3683 3679 { 3684 // SC command but zero copies 3680 // SC command but zero copies 3685 3681 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 3686 3682 { … … 3726 3722 if(no_update) 3727 3723 { 3728 std::cout << " <MEMC " << name() 3724 std::cout << " <MEMC " << name() 3729 3725 << " WRITE_DIR_HIT> Write into cache / No coherence transaction" 3730 3726 << std::endl; … … 3761 3757 true, // response required 3762 3758 false, // no acknowledge required 3763 srcid, 3759 srcid, 3764 3760 trdid, 3765 3761 pktid, … … 3792 3788 if(wok) 3793 3789 { 3794 std::cout << " <MEMC " << name() 3790 std::cout << " <MEMC " << name() 3795 3791 << " WRITE_UPT_LOCK> Register the multicast update in UPT / " 3796 3792 << " nb_copies = " << r_write_count.read() << std::endl; … … 3814 3810 #if DEBUG_MEMC_WRITE 3815 3811 if(m_debug) 3816 std::cout << " <MEMC " << name() 3812 std::cout << " <MEMC " << name() 3817 3813 << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl; 3818 3814 #endif … … 3906 3902 3907 3903 // put the next srcid in the fifo 3908 if ((entry.owner.srcid != r_write_srcid.read()) or 3904 if ((entry.owner.srcid != r_write_srcid.read()) or 3909 3905 ((r_write_pktid.read() & 0x7) == TYPE_SC) or 3910 3906 entry.owner.inst) … … 4026 4022 4027 4023 r_write_sc_key = m_cmd_write_data_fifo.read(); 4028 } 4024 } 4029 4025 4030 4026 // initialize the be field for all words … … 4049 4045 { 4050 4046 std::cout << " <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM" 4051 << " : rsrcid = " << std::hex << r_write_srcid.read() 4052 << " : rpktid = " << std::hex << r_write_pktid.read() 4047 << " : rsrcid = " << std::hex << r_write_srcid.read() 4048 << " : rpktid = " << std::hex << r_write_pktid.read() 4053 4049 << " : sc_fail= " << std::hex << r_write_sc_fail.read() 4054 4050 << std::endl; … … 4058 4054 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() 4059 4055 << " / address = " << m_cmd_write_addr_fifo.read() 4060 << " / data = " << m_cmd_write_data_fifo.read() 4061 << " / pktid = " << m_cmd_write_pktid_fifo.read() 4056 << " / data = " << m_cmd_write_data_fifo.read() 4057 << " / pktid = " << m_cmd_write_pktid_fifo.read() 4062 4058 << std::endl; 4063 4059 } … … 4068 4064 } 4069 4065 ///////////////////////// RWT 4070 case WRITE_MISS_IVT_LOCK: 4066 case WRITE_MISS_IVT_LOCK: 4071 4067 { 4072 4068 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) … … 4224 4220 #if DEBUG_MEMC_WRITE 4225 4221 if(m_debug) 4226 std::cout << " <MEMC " << name() 4222 std::cout << " <MEMC " << name() 4227 4223 << " WRITE_MISS_XRAM_REQ> Post a GET request to the" 4228 4224 << " IXR_CMD FSM" << std::endl; … … 4282 4278 #if DEBUG_MEMC_WRITE 4283 4279 if(m_debug) 4284 std::cout 4280 std::cout 4285 4281 << " <MEMC " << name() 4286 4282 << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl; … … 4476 4472 // 4477 4473 // - It sends a single flit VCI read to the XRAM in case of 4478 // GET request posted by the READ, WRITE or CAS FSMs. 4474 // GET request posted by the READ, WRITE or CAS FSMs. 4479 4475 // - It sends a multi-flit VCI write in case of PUT request posted by 4480 4476 // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. … … 4535 4531 else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4536 4532 else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4537 break; 4533 break; 4538 4534 ///////////////////////// 4539 4535 case IXR_CMD_CONFIG_IDLE: … … 4597 4593 } 4598 4594 ///////////////////// 4599 case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET 4595 case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET 4600 4596 { 4601 4597 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) … … 4624 4620 } 4625 4621 ////////////////////// 4626 case IXR_CMD_XRAM_TRT: // access TRT for a PUT 4622 case IXR_CMD_XRAM_TRT: // access TRT for a PUT 4627 4623 { 4628 4624 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) … … 4646 4642 } 4647 4643 ////////////////////// 4648 case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT 4644 case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT 4649 4645 { 4650 4646 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) … … 4866 4862 // The FSM takes the lock protecting the TRT, and the corresponding 4867 4863 // entry is erased. If an acknowledge was required (in case of software SYNC) 4868 // the r_config_rsp_lines counter is decremented. 4864 // the r_config_rsp_lines counter is decremented. 4869 4865 // 4870 4866 // - A response to a GET request is a multi-cell VCI packet. … … 4873 4869 // The FSM takes the lock protecting the TRT to store the line in the TRT 4874 4870 // (taking into account the write requests already stored in the TRT). 4875 // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] 4871 // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] 4876 4872 // signal is set to inform the XRAM_RSP FSM. 4877 4873 /////////////////////////////////////////////////////////////////////////////// … … 4902 4898 << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; 4903 4899 #endif 4904 } 4905 } 4900 } 4901 } 4906 4902 break; 4907 4903 } … … 4919 4915 if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) 4920 4916 { 4921 size_t index = r_ixr_rsp_trt_index.read(); 4917 size_t index = r_ixr_rsp_trt_index.read(); 4922 4918 if (m_trt.is_config(index)) // it's a config transaction 4923 4919 { … … 4977 4973 // The cache line has been written in the TRT by the IXR_CMD_FSM. 4978 4974 // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, 4979 // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number 4975 // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number 4980 4976 // of entries in the TRT, that are handled with a round-robin priority... 4981 4977 // … … 5018 5014 break; 5019 5015 } 5020 } 5016 } 5021 5017 break; 5022 5018 } … … 5074 5070 r_xram_rsp_victim_inval = inval ; 5075 5071 // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry 5076 r_xram_rsp_victim_dirty = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); 5072 r_xram_rsp_victim_dirty = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); 5077 5073 5078 5074 5079 5075 // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache. 5080 if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) 5076 if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) 5081 5077 { 5082 5078 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; … … 5090 5086 #endif 5091 5087 } 5092 else if( not r_xram_rsp_trt_buf.rerror ) 5088 else if( not r_xram_rsp_trt_buf.rerror ) 5093 5089 { 5094 5090 r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; 5095 5091 } 5096 else 5092 else 5097 5093 { 5098 5094 r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; … … 5111 5107 } 5112 5108 /////////////////////// 5113 case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock 5109 case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock 5114 5110 // to check a possible pending inval 5115 5111 { … … 5241 5237 bool wok = m_ivt.set(false, // it's an inval transaction 5242 5238 broadcast, // set broadcast bit 5243 false, // no response required 5244 false, // no acknowledge required 5239 false, // no response required 5240 false, // no acknowledge required 5245 5241 0, // srcid 5246 5242 0, // trdid … … 5252 5248 r_xram_rsp_ivt_index = index; 5253 5249 assert( wok and 5254 "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); 5250 "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); 5255 5251 5256 5252 } … … 5313 5309 0, // unused 5314 5310 0, // unused 5315 std::vector<be_t>(m_words,0xF), 5311 std::vector<be_t>(m_words,0xF), 5316 5312 data_vector); 5317 5313 #if DEBUG_MEMC_XRAM_RSP … … 5411 5407 m_cpt_write_dirty++; 5412 5408 5413 bool multi_req = not r_xram_rsp_victim_is_cnt.read() and 5409 bool multi_req = not r_xram_rsp_victim_is_cnt.read() and 5414 5410 r_xram_rsp_victim_inval.read(); 5415 5411 bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); … … 5540 5536 // acknowledged before signaling another one. 5541 5537 // Therefore, when there is an active error, and other 5542 // errors arrive, these are not considered 5538 // errors arrive, these are not considered 5543 5539 5544 5540 if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() … … 5639 5635 r_cleanup_inst = (type == DspinRwtParam::TYPE_CLEANUP_INST); 5640 5636 r_cleanup_srcid = srcid; 5641 r_cleanup_ncc = 5637 r_cleanup_ncc = 5642 5638 DspinRwtParam::dspin_get( 5643 5639 flit, … … 5738 5734 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); 5739 5735 5740 uint32_t data = 5736 uint32_t data = 5741 5737 DspinRwtParam::dspin_get (flit, DspinRwtParam::CLEANUP_DATA_UPDT); 5742 5738 … … 5809 5805 //RWT 5810 5806 size_t set = m_y[(addr_t)(cleanup_address)]; 5811 m_cache_data.read_line(way, set, r_cleanup_old_data); 5807 m_cache_data.read_line(way, set, r_cleanup_old_data); 5812 5808 r_cleanup_coherent = entry.cache_coherent; 5813 5809 … … 5911 5907 entry.lock = r_cleanup_lock.read(); 5912 5908 entry.ptr = r_cleanup_ptr.read(); 5913 if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ 5909 if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ 5914 5910 { 5915 5911 if (r_read_to_cleanup_cached_read.read()) … … 5937 5933 5938 5934 #if REVERT_CC_MECANISM 5939 // Revert CC to NCC if : 5935 // Revert CC to NCC if : 5940 5936 // - no more copy in L1 caches 5941 5937 // - this line is not in counter mode (broadcast) … … 5948 5944 5949 5945 #if REVERT_BC_MECANISM 5950 if ((r_cleanup_count.read() - 1) == 0) 5946 if ((r_cleanup_count.read() - 1) == 0) 5951 5947 { 5952 5948 entry.is_cnt = false; … … 6082 6078 { 6083 6079 r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read(); 6084 } 6080 } 6085 6081 } 6086 6082 … … 6354 6350 ////////////////////// 6355 6351 case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending 6356 // invalidate transaction matching the cleanup 6352 // invalidate transaction matching the cleanup 6357 6353 { 6358 6354 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; … … 6432 6428 } 6433 6429 /////////////////////// 6434 case CLEANUP_IVT_CLEAR: // Clear IVT entry 6430 case CLEANUP_IVT_CLEAR: // Clear IVT entry 6435 6431 { 6436 6432 assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and … … 6473 6469 r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); 6474 6470 r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); 6475 r_cleanup_to_tgt_rsp_type = true; 6471 r_cleanup_to_tgt_rsp_type = true; 6476 6472 6477 6473 if (r_cleanup_ncc.read() ) … … 6503 6499 { 6504 6500 size_t index = 0; 6505 bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); 6501 bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); 6506 6502 6507 6503 assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT"); … … 6510 6506 6511 6507 if (r_cleanup_contains_data.read()) 6512 { 6508 { 6513 6509 std::vector<data_t> data_vector; 6514 6510 data_vector.clear(); … … 6587 6583 << " nline = " << std::hex << r_cleanup_nline.read() 6588 6584 << " / way = " << std::dec << r_cleanup_way.read() 6589 << " / srcid = " << std::dec << r_cleanup_srcid.read() 6585 << " / srcid = " << std::dec << r_cleanup_srcid.read() 6590 6586 << std::endl; 6591 6587 #endif … … 6805 6801 if(m_debug) 6806 6802 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>" 6807 << " Broacast Inval required" 6803 << " Broacast Inval required" 6808 6804 << " / copies = " << r_cas_count.read() << std::endl; 6809 6805 #endif … … 6817 6813 if(m_debug) 6818 6814 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>" 6819 << " Multi Inval required" 6815 << " Multi Inval required" 6820 6816 << " / copies = " << r_cas_count.read() << std::endl; 6821 6817 #endif … … 6874 6870 wok = m_upt.set(true, // it's an update transaction 6875 6871 false, // it's not a broadcast 6876 true, // response required 6872 true, // response required 6877 6873 false, // no acknowledge required 6878 6874 srcid, … … 7137 7133 { 7138 7134 if(i == word) // first modified word 7139 data_vector.push_back( r_cas_wdata.read() ); 7135 data_vector.push_back( r_cas_wdata.read() ); 7140 7136 else if((i == word+1) and (r_cas_cpt.read() == 4)) // second modified word 7141 7137 data_vector.push_back( m_cmd_cas_wdata_fifo.read() ); … … 7144 7140 } 7145 7141 m_trt.set( r_cas_trt_index.read(), 7146 false, // PUT request 7142 false, // PUT request 7147 7143 m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())], 7148 7144 0, … … 7364 7360 // 7365 7361 // It implements a round-robin priority between the four possible client FSMs 7366 // XRAM_RSP > CAS > READ > WRITE > CONFIG 7362 // XRAM_RSP > CAS > READ > WRITE > CONFIG 7367 7363 // 7368 7364 // Each FSM can request the next services: … … 7375 7371 // - r_config_to_cc_send_multi_req : multi-inval 7376 7372 // r_config_to_cc_send_brdcast_req : broadcast-inval 7377 // 7373 // 7378 7374 // An inval request is a double DSPIN flit command containing: 7379 7375 // 1. the index of the line to be invalidated. … … 7517 7513 } 7518 7514 /////////////////////////// 7519 case CC_SEND_READ_IDLE: 7515 case CC_SEND_READ_IDLE: 7520 7516 { 7521 7517 // WRITE … … 8264 8260 } 8265 8261 else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8266 else if(r_cleanup_to_tgt_rsp_req) 8262 else if(r_cleanup_to_tgt_rsp_req) 8267 8263 { 8268 8264 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; … … 8809 8805 // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets 8810 8806 // a new entry in the IVT 8811 // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 8807 // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 8812 8808 // - The CLEANUP FSM complete those trasactions and erase the IVT entry. 8813 8809 // The resource is always allocated. … … 8844 8840 ////////////////////////// 8845 8841 case ALLOC_IVT_READ: // allocated to READ FSM 8846 if (r_read_fsm.read() != READ_IVT_LOCK) 8842 if (r_read_fsm.read() != READ_IVT_LOCK) 8847 8843 { 8848 8844 if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) … … 9231 9227 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9232 9228 9233 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9229 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9234 9230 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9235 9231 … … 9268 9264 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9269 9265 9270 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9266 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9271 9267 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9272 9268 … … 9304 9300 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9305 9301 9306 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9302 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9307 9303 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9308 9304 … … 9338 9334 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9339 9335 9340 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9336 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9341 9337 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9342 9338 … … 9369 9365 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9370 9366 9371 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9367 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9372 9368 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9373 9369 … … 9404 9400 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 9405 9401 { 9406 if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9402 if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9407 9403 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9408 9404 … … 9506 9502 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9507 9503 9508 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9504 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 9509 9505 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9510 9506 } … … 9698 9694 ///////////////////////////////////////////////////////////////////// 9699 9695 9700 m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9696 m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9701 9697 p_vci_tgt.address.read() ); 9702 m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9698 m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9703 9699 p_vci_tgt.plen.read()>>2 ); 9704 m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9700 m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9705 9701 p_vci_tgt.srcid.read() ); 9706 m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9702 m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9707 9703 p_vci_tgt.trdid.read() ); 9708 m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9704 m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 9709 9705 p_vci_tgt.pktid.read() ); 9710 9706 … … 9773 9769 9774 9770 m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, 9775 cc_receive_to_multi_ack_fifo_put, 9771 cc_receive_to_multi_ack_fifo_put, 9776 9772 p_dspin_p2m.data.read() ); 9777 9773 … … 9817 9813 // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs 9818 9814 //////////////////////////////////////////////////////////////////////////////////// 9819 if ( config_rsp_lines_incr and not 9815 if ( config_rsp_lines_incr and not 9820 9816 (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) 9821 9817 { 9822 9818 r_config_rsp_lines = r_config_rsp_lines.read() + 1; 9823 9819 } 9824 if ( not config_rsp_lines_incr and 9820 if ( not config_rsp_lines_incr and 9825 9821 (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) 9826 9822 { … … 9830 9826 //////////////////////////////////////////////////////////////////////////////////// 9831 9827 // Update min m_cpt_heap_min_slot_available. 9832 // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs 9828 // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs 9833 9829 //////////////////////////////////////////////////////////////////////////////////// 9834 9830 assert((m_cpt_heap_slot_available <= m_heap_size) and "m_cpt_heap_slot_available > m_heap_size"); … … 9868 9864 // DATA width is 8 bytes 9869 9865 // The following values are not transmitted to XRAM 9870 // p_vci_ixr.be 9871 // p_vci_ixr.pktid 9872 // p_vci_ixr.cons 9873 // p_vci_ixr.wrap 9874 // p_vci_ixr.contig 9875 // p_vci_ixr.clen 9876 // p_vci_ixr.cfixed 9866 // p_vci_ixr.be 9867 // p_vci_ixr.pktid 9868 // p_vci_ixr.cons 9869 // p_vci_ixr.wrap 9870 // p_vci_ixr.contig 9871 // p_vci_ixr.clen 9872 // p_vci_ixr.cfixed 9877 9873 9878 9874 p_vci_ixr.plen = 64; … … 9880 9876 p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); 9881 9877 p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); 9882 p_vci_ixr.be = 0xFF; 9878 p_vci_ixr.be = 0xFF; 9883 9879 p_vci_ixr.pktid = 0; 9884 9880 p_vci_ixr.cons = false; … … 9916 9912 p_vci_ixr.cmdval = true; 9917 9913 p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); 9918 p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | 9914 p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | 9919 9915 ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32)); 9920 9916 p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_index.read(); … … 9933 9929 if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or 9934 9930 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ) 9935 { 9931 { 9936 9932 p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); 9937 9933 } … … 10109 10105 p_vci_tgt.rspval = true; 10110 10106 10111 if( is_ll and not r_tgt_rsp_key_sent.read() ) 10107 if( is_ll and not r_tgt_rsp_key_sent.read() ) 10112 10108 { 10113 10109 // LL response first flit 10114 10110 p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); 10115 10111 } 10116 else 10112 else 10117 10113 { 10118 10114 // LL response second flit or READ response … … 10275 10271 m_broadcast_boundaries, 10276 10272 DspinRwtParam::BROADCAST_BOX); 10277 10273 10278 10274 DspinRwtParam::dspin_set( flit, 10279 10275 1,
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