Changeset 919 for branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

Timestamp:

Jan 9, 2015, 11:55:11 PM (9 years ago)

Author:

cfuguet

Message:

reconf: implement the CC_TEST FSM in the cc_vcache_wrapper

• Watchdog on the CC_TEST FSM is still missing

File:

• branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (6 diffs)

branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -123 +123 @@
         DCACHE_XTN_DC_INVAL_GO,
         DCACHE_XTN_DT_INVAL,
+        DCACHE_XTN_CC_TEST,
         //handling dirty bit update
         DCACHE_DIRTY_GET_PTE,
@@ -184 +185 @@
         CC_RECEIVE_INS_UPDT_DATA,
         CC_RECEIVE_DATA_UPDT_DATA,
+        CC_RECEIVE_TEST_HEADER,
+        CC_RECEIVE_TEST_SIGNATURE,
     };
 
@@ -192 +195 @@
         CC_SEND_CLEANUP_2,
         CC_SEND_MULTI_ACK,
+        CC_SEND_TEST_HEADER,
+        CC_SEND_TEST_SIGNATURE,
+    };
+
+    enum cc_test_fsm_state_e
+    {
+        CC_TEST_IDLE,
+        CC_TEST_P2M_REQ,
+        CC_TEST_P2M_WAIT,
+        CC_TEST_ACK_WAIT,
     };
 
@@ -279 +292 @@
 
     // this enumeration type extends the ExternalAcessTypes defined in iss2.h
+    // XTN_CC_TEST:
+    //    When XTN_WRITE: triggers the CC_TEST. The target MEMC is in dreq.wdata
+    //    When XTN_READ: returns the CC_TEST result
     enum xtn_cop2_extension_e {
         XTN_WDT_MAX = 26,              // Read & Write the watchdog timer threshold
+        XTN_CC_TEST = 27,              // Trigger coherence network test
     };
 
@@ -516 +533 @@
     sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
 
+    // communication between DCACHE FSM and CC_TEST FSM
+    sc_signal<bool>         r_dcache_to_cc_test_req;
+    sc_signal<uint32_t>     r_dcache_to_cc_test_dest;
+
     ///////////////////////////////////
     // VCI_CMD FSM REGISTERS
@@ -574 +595 @@
     sc_signal<bool>         r_dspin_clack_req;
     sc_signal<uint64_t>     r_dspin_clack_flit;
+    sc_signal<bool>         r_dspin_clack_test;
+
+    ///////////////////////////////////
+    //  CC_TEST FSM REGISTER
+    ///////////////////////////////////
+    enum cc_test_result_e
+    {
+        CC_TEST_SUCCESS = 0,
+        CC_TEST_FAILURE = 1,
+    };
+
+    sc_signal<int>          r_cc_test_fsm;
+    sc_signal<bool>         r_cc_test_to_cc_send_req;
+    sc_signal<bool>         r_cc_test_m2p_req;
+    sc_signal<uint64_t>     r_cc_test_m2p_sign;
+    sc_signal<bool>         r_cc_test_clack_req;
+    sc_signal<uint64_t>     r_cc_test_clack_sign;
+    sc_signal<int>          r_cc_test_to_dcache_result;
 
     //////////////////////////////////////////////////////////////////