[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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[445] | 4 | * Author Alain Greiner (2016,2017,2018) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[457] | 24 | #include <hal_kernel_types.h> |
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[1] | 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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| 27 | #include <printk.h> |
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| 28 | #include <bits.h> |
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| 29 | #include <process.h> |
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| 30 | #include <kmem.h> |
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| 31 | #include <thread.h> |
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| 32 | #include <cluster.h> |
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| 33 | #include <ppm.h> |
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| 34 | #include <page.h> |
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| 35 | |
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| 36 | //////////////////////////////////////////////////////////////////////////////////////// |
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[401] | 37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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[1] | 38 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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[629] | 40 | #define TSAR_PTE_MAPPED 0x80000000 |
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| 41 | #define TSAR_PTE_SMALL 0x40000000 |
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| 42 | #define TSAR_PTE_LOCAL 0x20000000 |
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| 43 | #define TSAR_PTE_REMOTE 0x10000000 |
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| 44 | #define TSAR_PTE_CACHABLE 0x08000000 |
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| 45 | #define TSAR_PTE_WRITABLE 0x04000000 |
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| 46 | #define TSAR_PTE_EXECUTABLE 0x02000000 |
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| 47 | #define TSAR_PTE_USER 0x01000000 |
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| 48 | #define TSAR_PTE_GLOBAL 0x00800000 |
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| 49 | #define TSAR_PTE_DIRTY 0x00400000 |
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[1] | 50 | |
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[629] | 51 | #define TSAR_PTE_COW 0x00000001 // only for small pages |
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| 52 | #define TSAR_PTE_SWAP 0x00000004 // only for small pages |
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| 53 | #define TSAR_PTE_LOCKED 0x00000008 // only for small pages |
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[1] | 54 | |
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| 55 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 57 | // - IX1 on 11 bits |
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| 58 | // - IX2 on 9 bits |
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| 59 | // - PPN on 28 bits |
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| 60 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 63 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 64 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 65 | |
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[401] | 66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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| 67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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| 68 | |
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[1] | 69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 71 | |
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[315] | 72 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 73 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 75 | |
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| 76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 78 | |
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[401] | 79 | |
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| 80 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 81 | // This static function translates the GPT attributes to the TSAR attributes |
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| 82 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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| 84 | { |
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| 85 | uint32_t tsar_attr = 0; |
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| 86 | |
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[629] | 87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_PTE_MAPPED; |
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| 88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_PTE_SMALL; |
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| 89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_PTE_WRITABLE; |
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| 90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_PTE_EXECUTABLE; |
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| 91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_PTE_CACHABLE; |
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| 92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_PTE_USER; |
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| 93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_PTE_DIRTY; |
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| 94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_PTE_LOCAL; |
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| 95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_PTE_GLOBAL; |
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| 96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_PTE_COW; |
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| 97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_PTE_SWAP; |
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| 98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_PTE_LOCKED; |
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[401] | 99 | |
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| 100 | return tsar_attr; |
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| 101 | } |
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| 102 | |
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| 103 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 104 | // This static function translates the TSAR attributes to the GPT attributes |
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| 105 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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| 107 | { |
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| 108 | uint32_t gpt_attr = 0; |
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| 109 | |
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[629] | 110 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_MAPPED; |
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| 111 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_READABLE; |
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| 112 | if( tsar_attr & TSAR_PTE_SMALL ) gpt_attr |= GPT_SMALL; |
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| 113 | if( tsar_attr & TSAR_PTE_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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| 114 | if( tsar_attr & TSAR_PTE_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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| 115 | if( tsar_attr & TSAR_PTE_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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| 116 | if( tsar_attr & TSAR_PTE_USER ) gpt_attr |= GPT_USER; |
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| 117 | if( tsar_attr & TSAR_PTE_DIRTY ) gpt_attr |= GPT_DIRTY; |
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| 118 | if( tsar_attr & TSAR_PTE_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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| 119 | if( tsar_attr & TSAR_PTE_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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| 120 | if( tsar_attr & TSAR_PTE_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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| 121 | if( tsar_attr & TSAR_PTE_COW ) gpt_attr |= GPT_COW; |
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| 122 | if( tsar_attr & TSAR_PTE_SWAP ) gpt_attr |= GPT_SWAP; |
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| 123 | if( tsar_attr & TSAR_PTE_LOCKED ) gpt_attr |= GPT_LOCKED; |
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[401] | 124 | |
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| 125 | return gpt_attr; |
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| 126 | } |
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| 127 | |
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[1] | 128 | ///////////////////////////////////// |
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| 129 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 130 | { |
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| 131 | page_t * page; |
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[315] | 132 | xptr_t page_xp; |
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[1] | 133 | |
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[587] | 134 | thread_t * this = CURRENT_THREAD; |
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| 135 | |
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[443] | 136 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 137 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 138 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[611] | 139 | printk("\n[%s] : thread[%x,%x] enter / cycle %d\n", |
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[587] | 140 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 141 | #endif |
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[406] | 142 | |
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[623] | 143 | // check page size |
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| 144 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "for TSAR, the page size must be 4 Kbytes\n" ); |
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[1] | 145 | |
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| 146 | // allocates 2 physical pages for PT1 |
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| 147 | kmem_req_t req; |
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| 148 | req.type = KMEM_PAGE; |
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| 149 | req.size = 1; // 2 small pages |
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| 150 | req.flags = AF_KERNEL | AF_ZERO; |
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| 151 | page = (page_t *)kmem_alloc( &req ); |
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| 152 | |
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[406] | 153 | if( page == NULL ) |
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[1] | 154 | { |
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[587] | 155 | printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n", |
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| 156 | __FUNCTION__, this->process->pid, local_cxy ); |
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[1] | 157 | return ENOMEM; |
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[406] | 158 | } |
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[1] | 159 | |
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| 160 | // initialize generic page table descriptor |
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[315] | 161 | page_xp = XPTR( local_cxy , page ); |
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| 162 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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| 163 | gpt->ppn = ppm_page2ppn( page_xp ); |
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| 164 | |
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[443] | 165 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 166 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 167 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[611] | 168 | printk("\n[%s] : thread[%x,%x] exit / cycle %d\n", |
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[587] | 169 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 170 | #endif |
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[406] | 171 | |
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[1] | 172 | return 0; |
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[406] | 173 | |
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[1] | 174 | } // end hal_gpt_create() |
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| 175 | |
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| 176 | /////////////////////////////////// |
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| 177 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 178 | { |
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| 179 | uint32_t ix1; |
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| 180 | uint32_t ix2; |
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| 181 | uint32_t * pt1; |
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| 182 | uint32_t pte1; |
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| 183 | ppn_t pt2_ppn; |
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| 184 | uint32_t * pt2; |
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| 185 | uint32_t attr; |
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| 186 | kmem_req_t req; |
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| 187 | |
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[443] | 188 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 189 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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| 190 | thread_t * this = CURRENT_THREAD; |
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[443] | 191 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[611] | 192 | printk("\n[%s] : thread[%x,%x] enter / cycle %d\n", |
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[587] | 193 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 194 | #endif |
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| 195 | |
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[1] | 196 | // get pointer on PT1 |
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| 197 | pt1 = (uint32_t *)gpt->ptr; |
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| 198 | |
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| 199 | // scan the PT1 |
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| 200 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 201 | { |
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| 202 | pte1 = pt1[ix1]; |
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[629] | 203 | |
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| 204 | if( (pte1 & TSAR_PTE_MAPPED) != 0 ) // PTE1 mapped |
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[1] | 205 | { |
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[629] | 206 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page |
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[1] | 207 | { |
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[629] | 208 | printk("\n[WARNING] in %s : mapped big page / ix1 %x\n", |
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| 209 | __FUNCTION__ , ix1 ); |
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[1] | 210 | } |
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[629] | 211 | else // PT2 exist |
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[1] | 212 | { |
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[315] | 213 | // get local pointer on PT2 |
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[1] | 214 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 215 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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[587] | 216 | pt2 = GET_PTR( base_xp ); |
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[1] | 217 | |
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[629] | 218 | // scan the PT2 |
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| 219 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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[1] | 220 | { |
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[629] | 221 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 222 | |
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| 223 | if( (attr & TSAR_PTE_MAPPED) != 0 ) // PTE2 mapped |
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[1] | 224 | { |
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[629] | 225 | printk("\n[WARNING] in %s : mapped small page / ix1 %x / ix2 %x\n", |
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| 226 | __FUNCTION__ , ix1, ix2 ); |
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[1] | 227 | } |
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| 228 | } |
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| 229 | |
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[629] | 230 | // release the page allocated for the PT2 |
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[1] | 231 | req.type = KMEM_PAGE; |
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[315] | 232 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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[1] | 233 | kmem_free( &req ); |
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| 234 | } |
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| 235 | } |
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| 236 | } |
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| 237 | |
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| 238 | // release the PT1 |
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| 239 | req.type = KMEM_PAGE; |
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[315] | 240 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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[1] | 241 | kmem_free( &req ); |
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| 242 | |
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[443] | 243 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 244 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 245 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[611] | 246 | printk("\n[%s] : thread[%x,%x] exit / cycle %d\n", |
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[587] | 247 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 248 | #endif |
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| 249 | |
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[1] | 250 | } // end hal_gpt_destroy() |
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| 251 | |
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[629] | 252 | /* |
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| 253 | |
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| 254 | ///////////////////////////////////////////////////////////////////////////////////// |
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| 255 | // This static function can be used for debug. |
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| 256 | ///////////////////////////////////////////////////////////////////////////////////// |
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| 257 | static void hal_gpt_display( process_t * process ) |
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[1] | 258 | { |
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[407] | 259 | gpt_t * gpt; |
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[1] | 260 | uint32_t ix1; |
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| 261 | uint32_t ix2; |
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| 262 | uint32_t * pt1; |
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| 263 | uint32_t pte1; |
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| 264 | ppn_t pt2_ppn; |
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| 265 | uint32_t * pt2; |
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| 266 | uint32_t pte2_attr; |
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| 267 | ppn_t pte2_ppn; |
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[406] | 268 | vpn_t vpn; |
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[1] | 269 | |
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[623] | 270 | // check argument |
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| 271 | assert( (process != NULL) , "NULL process pointer\n"); |
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[1] | 272 | |
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[407] | 273 | // get pointer on gpt |
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| 274 | gpt = &(process->vmm.gpt); |
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| 275 | |
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| 276 | // get pointer on PT1 |
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[1] | 277 | pt1 = (uint32_t *)gpt->ptr; |
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| 278 | |
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[623] | 279 | printk("\n***** Tsar Page Table for process %x : &gpt = %x / &pt1 = %x\n\n", |
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[407] | 280 | process->pid , gpt , pt1 ); |
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[406] | 281 | |
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[1] | 282 | // scan the PT1 |
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| 283 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 284 | { |
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| 285 | pte1 = pt1[ix1]; |
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[629] | 286 | if( (pte1 & TSAR_PTE_MAPPED) != 0 ) |
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[1] | 287 | { |
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[629] | 288 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page |
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[1] | 289 | { |
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[406] | 290 | vpn = ix1 << 9; |
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| 291 | printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 ); |
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[1] | 292 | } |
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| 293 | else // SMALL pages |
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| 294 | { |
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| 295 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 296 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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[587] | 297 | pt2 = GET_PTR( base_xp ); |
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[1] | 298 | |
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| 299 | // scan the PT2 |
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| 300 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 301 | { |
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| 302 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 303 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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[406] | 304 | |
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[629] | 305 | if( (pte2_attr & TSAR_PTE_MAPPED) != 0 ) |
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[1] | 306 | { |
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[406] | 307 | vpn = (ix1 << 9) | ix2; |
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[408] | 308 | printk(" - SMALL : vpn %X / ppn %X / attr %X\n", |
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| 309 | vpn , pte2_ppn , tsar2gpt(pte2_attr) ); |
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[1] | 310 | } |
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| 311 | } |
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| 312 | } |
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| 313 | } |
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| 314 | } |
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[407] | 315 | } // end hal_gpt_display() |
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[1] | 316 | |
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[629] | 317 | */ |
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[1] | 318 | |
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[629] | 319 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[630] | 320 | // This static function returns in the <ptd1_value> buffer the current value of |
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| 321 | // the PT1 entry identified by the <pte1_xp> argument, that must contain a PTD1 |
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| 322 | // (i.e. a pointer on a PT2). If this PT1 entry is not mapped yet, it allocates a |
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| 323 | // new PT2 and updates the PT1 entry, using the TSAR_MMU_LOCKED attribute in PT1 |
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| 324 | // entry, to handle possible concurrent mappings of the missing PTD1: |
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| 325 | // 1) If the PT1 entry is unmapped, it tries to atomically lock this PTD1. |
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| 326 | // - if the atomic lock is successful it allocates a new PT1, and updates the PTD1. |
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| 327 | // - else, it simply waits, in a polling loop, the mapping done by another thread. |
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| 328 | // In both cases, returns the PTD1 value, when the mapping is completed. |
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| 329 | // 2) If the PT1 entry is already mapped, it returns the PTD1 value, and does |
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| 330 | // nothing else. |
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[629] | 331 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[630] | 332 | static error_t hal_gpt_allocate_pt2( xptr_t ptd1_xp, |
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| 333 | uint32_t * ptd1_value ) |
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[1] | 334 | { |
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[630] | 335 | cxy_t gpt_cxy; // target GPT cluster = GET_CXY( ptd1_xp ); |
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| 336 | uint32_t ptd1; // PTD1 value |
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[629] | 337 | ppn_t pt2_ppn; // PPN of page containing the new PT2 |
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| 338 | bool_t atomic; |
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| 339 | page_t * page; |
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| 340 | xptr_t page_xp; |
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| 341 | |
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| 342 | // get GPT cluster identifier |
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[630] | 343 | gpt_cxy = GET_CXY( ptd1_xp ); |
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[629] | 344 | |
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[630] | 345 | // get current ptd1 value |
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| 346 | ptd1 = hal_remote_l32( ptd1_xp ); |
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[629] | 347 | |
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[630] | 348 | if( (ptd1 & TSAR_PTE_MAPPED) == 0) // PTD1 unmapped and unlocked |
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[629] | 349 | { |
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[630] | 350 | // atomically lock the PTD1 to prevent concurrent PTD1 mappings |
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| 351 | atomic = hal_remote_atomic_cas( ptd1_xp, |
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| 352 | ptd1, |
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| 353 | ptd1 | TSAR_PTE_LOCKED ); |
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[629] | 354 | |
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[630] | 355 | if( atomic ) // PTD1 successfully locked |
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[629] | 356 | { |
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| 357 | // allocate one physical page for PT2 |
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| 358 | if( gpt_cxy == local_cxy ) |
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| 359 | { |
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| 360 | kmem_req_t req; |
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| 361 | req.type = KMEM_PAGE; |
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| 362 | req.size = 0; // 1 small page |
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| 363 | req.flags = AF_KERNEL | AF_ZERO; |
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| 364 | page = (page_t *)kmem_alloc( &req ); |
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| 365 | } |
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| 366 | else |
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| 367 | { |
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| 368 | rpc_pmem_get_pages_client( gpt_cxy , 0 , &page ); |
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| 369 | } |
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| 370 | |
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| 371 | if( page == NULL ) return -1; |
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| 372 | |
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| 373 | // get the PT2 PPN |
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| 374 | page_xp = XPTR( gpt_cxy , page ); |
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| 375 | pt2_ppn = ppm_page2ppn( page_xp ); |
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| 376 | |
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[630] | 377 | // build PTD1 |
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| 378 | ptd1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | pt2_ppn; |
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[629] | 379 | |
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| 380 | // set the PTD1 value in PT1 |
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[630] | 381 | hal_remote_s32( ptd1_xp , ptd1 ); |
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[629] | 382 | hal_fence(); |
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| 383 | |
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| 384 | #if DEBUG_HAL_GPT_ALLOCATE_PT2 |
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| 385 | thread_t * this = CURRENT_THREAD; |
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| 386 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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| 387 | if( DEBUG_HAL_GPT_ALLOCATE_PT2 < cycle ) |
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[630] | 388 | printk("\n[%s] : thread[%x,%x] map PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", |
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| 389 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, ptd1 ); |
---|
[629] | 390 | #endif |
---|
| 391 | } |
---|
[630] | 392 | else // PTD1 modified by another thread |
---|
[629] | 393 | { |
---|
[630] | 394 | // poll PTD1 until mapped by another thread |
---|
| 395 | while( (ptd1 & TSAR_PTE_MAPPED) == 0 ) ptd1 = hal_remote_l32( ptd1_xp ); |
---|
[629] | 396 | } |
---|
| 397 | } |
---|
[630] | 398 | else // PTD1 mapped => just use it |
---|
[629] | 399 | { |
---|
| 400 | |
---|
| 401 | #if DEBUG_HAL_GPT_ALLOCATE_PT2 |
---|
| 402 | thread_t * this = CURRENT_THREAD; |
---|
| 403 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 404 | if( DEBUG_HAL_GPT_ALLOCATE_PT2 < cycle ) |
---|
[630] | 405 | printk("\n[%s] : thread[%x,%x] PTD1 mapped / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", |
---|
| 406 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, ptd1 ); |
---|
[629] | 407 | #endif |
---|
| 408 | |
---|
| 409 | } |
---|
| 410 | |
---|
[630] | 411 | *ptd1_value = ptd1; |
---|
[629] | 412 | return 0; |
---|
| 413 | |
---|
| 414 | } // end hal_gpt_allocate_pt2 |
---|
| 415 | |
---|
| 416 | |
---|
| 417 | |
---|
| 418 | |
---|
| 419 | //////////////////////////////////////////// |
---|
| 420 | error_t hal_gpt_lock_pte( xptr_t gpt_xp, |
---|
| 421 | vpn_t vpn, |
---|
| 422 | uint32_t * attr, |
---|
| 423 | ppn_t * ppn ) |
---|
| 424 | { |
---|
| 425 | error_t error; |
---|
| 426 | uint32_t * pt1_ptr; // local pointer on PT1 base |
---|
| 427 | xptr_t pte1_xp; // extended pointer on PT1[x1] entry |
---|
| 428 | uint32_t pte1; // value of PT1[x1] entry |
---|
| 429 | |
---|
| 430 | ppn_t pt2_ppn; // PPN of page containing PT2 |
---|
| 431 | uint32_t * pt2_ptr; // local pointer on PT2 base |
---|
| 432 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 433 | uint32_t pte2_attr; // PT2[ix2].attr current value |
---|
| 434 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 435 | uint32_t pte2_ppn; // PT2[ix2].ppn current value |
---|
| 436 | bool_t atomic; |
---|
| 437 | |
---|
| 438 | // get cluster and local pointer on GPT |
---|
| 439 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 440 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 441 | |
---|
| 442 | // get indexes in PTI & PT2 |
---|
| 443 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 444 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 445 | |
---|
| 446 | // get local pointer on PT1 |
---|
| 447 | pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 448 | |
---|
| 449 | // build extended pointer on PTE1 == PT1[ix1] |
---|
| 450 | pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] ); |
---|
| 451 | |
---|
| 452 | // get PTE1 value from PT1 |
---|
| 453 | // allocate a new PT2 for this PTE1 if required |
---|
| 454 | error = hal_gpt_allocate_pt2( pte1_xp , &pte1 ); |
---|
| 455 | |
---|
| 456 | if( error ) |
---|
| 457 | { |
---|
| 458 | printk("\n[ERROR] in %s : cannot allocate memory for PT2\n", __FUNCTION__ ); |
---|
| 459 | return -1; |
---|
| 460 | } |
---|
| 461 | |
---|
| 462 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) |
---|
| 463 | { |
---|
| 464 | printk("\n[ERROR] in %s : cannot lock a small page\n", __FUNCTION__ ); |
---|
| 465 | return -1; |
---|
| 466 | } |
---|
| 467 | |
---|
| 468 | // get pointer on PT2 base from PTE1 |
---|
| 469 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 470 | pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
| 471 | |
---|
| 472 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
---|
| 473 | pte2_attr_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ); |
---|
| 474 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] ); |
---|
| 475 | |
---|
| 476 | // wait until PTE2 unlocked, get PTE2.attr and set lock |
---|
| 477 | do |
---|
| 478 | { |
---|
| 479 | // busy waiting until TSAR_MMU_LOCK == 0 |
---|
| 480 | do |
---|
| 481 | { |
---|
| 482 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
| 483 | } |
---|
| 484 | while( (pte2_attr & TSAR_PTE_LOCKED) != 0 ); |
---|
| 485 | |
---|
| 486 | // try to atomically set the TSAR_MMU_LOCK attribute |
---|
| 487 | atomic = hal_remote_atomic_cas( pte2_attr_xp, |
---|
| 488 | pte2_attr, |
---|
| 489 | (pte2_attr | TSAR_PTE_LOCKED) ); |
---|
| 490 | } |
---|
| 491 | while( atomic == 0 ); |
---|
| 492 | |
---|
| 493 | // get PTE2.ppn |
---|
| 494 | pte2_ppn = hal_remote_l32( pte2_ppn_xp ); |
---|
| 495 | |
---|
| 496 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
| 497 | thread_t * this = CURRENT_THREAD; |
---|
| 498 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 499 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 500 | printk("\n[%s] : thread[%x,%x] locks vpn %x / attr %x / ppn %x / cluster %x / cycle %d\n", |
---|
| 501 | __FUNCTION__, this->process->pid, this->trdid, vpn, attr, ppn, gpt_cxy, cycle ); |
---|
| 502 | #endif |
---|
| 503 | |
---|
| 504 | // return PPN and GPT attributes |
---|
| 505 | *ppn = hal_remote_l32( pte2_ppn_xp ) & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
| 506 | *attr = tsar2gpt( pte2_attr ); |
---|
| 507 | return 0; |
---|
| 508 | |
---|
| 509 | } // end hal_gpt_lock_pte() |
---|
| 510 | |
---|
| 511 | //////////////////////////////////////// |
---|
| 512 | void hal_gpt_unlock_pte( xptr_t gpt_xp, |
---|
| 513 | vpn_t vpn ) |
---|
| 514 | { |
---|
| 515 | uint32_t * pt1_ptr; // local pointer on PT1 base |
---|
| 516 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
| 517 | uint32_t pte1; // value of PT1[ix1] entry |
---|
| 518 | |
---|
| 519 | ppn_t pt2_ppn; // PPN of page containing PT2 |
---|
| 520 | uint32_t * pt2_ptr; // PT2 base address |
---|
| 521 | uint32_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 522 | |
---|
| 523 | uint32_t attr; // PTE2 attribute |
---|
| 524 | |
---|
| 525 | // get cluster and local pointer on GPT |
---|
| 526 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 527 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 528 | |
---|
| 529 | // compute indexes in P1 and PT2 |
---|
| 530 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 531 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 532 | |
---|
| 533 | // get local pointer on PT1 |
---|
| 534 | pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 535 | |
---|
| 536 | // build extended pointer on PTE1 == PT1[ix1] |
---|
| 537 | pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] ); |
---|
| 538 | |
---|
| 539 | // get current pte1 value |
---|
| 540 | pte1 = hal_remote_l32( pte1_xp ); |
---|
| 541 | |
---|
| 542 | // check PTE1 attributes |
---|
| 543 | assert( (((pte1 & TSAR_PTE_MAPPED) != 0) && ((pte1 & TSAR_PTE_SMALL) != 0)), |
---|
| 544 | "try to unlock a big or unmapped PTE1\n"); |
---|
| 545 | |
---|
| 546 | // get pointer on PT2 base from PTE1 |
---|
| 547 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 548 | pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
| 549 | |
---|
| 550 | // build extended pointers on PT2[ix2].attr |
---|
| 551 | pte2_attr_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ); |
---|
| 552 | |
---|
| 553 | // get PT2[ix2].attr |
---|
| 554 | attr = hal_remote_l32( pte2_attr_xp ); |
---|
| 555 | |
---|
| 556 | // reset TSAR_MMU_LOCK attribute |
---|
| 557 | hal_remote_s32( pte2_attr_xp , attr & ~TSAR_PTE_LOCKED ); |
---|
| 558 | |
---|
| 559 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
| 560 | thread_t * this = CURRENT_THREAD; |
---|
| 561 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 562 | if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 563 | printk("\n[%s] : thread[%x,%x] unlocks vpn %x / attr %x / ppn %x / cluster %x / cycle %d\n", |
---|
| 564 | __FUNCTION__, this->process->pid, this->trdid, vpn, attr, ppn, gpt_cxy, cycle ); |
---|
| 565 | #endif |
---|
| 566 | |
---|
| 567 | } // end hal_gpt_unlock_pte() |
---|
| 568 | |
---|
| 569 | /////////////////////////////////////// |
---|
| 570 | void hal_gpt_set_pte( xptr_t gpt_xp, |
---|
| 571 | vpn_t vpn, |
---|
| 572 | uint32_t attr, |
---|
| 573 | ppn_t ppn ) |
---|
| 574 | { |
---|
[587] | 575 | cxy_t gpt_cxy; // target GPT cluster |
---|
| 576 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
[629] | 577 | |
---|
| 578 | uint32_t * pt1_ptr; // local pointer on PT1 base |
---|
[587] | 579 | xptr_t pte1_xp; // extended pointer on PT1 entry |
---|
| 580 | uint32_t pte1; // PT1 entry value if PTE1 |
---|
[1] | 581 | |
---|
[401] | 582 | ppn_t pt2_ppn; // PPN of PT2 |
---|
[629] | 583 | uint32_t * pt2_ptr; // local pointer on PT2 base |
---|
| 584 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 585 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 586 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
[1] | 587 | |
---|
[401] | 588 | uint32_t ix1; // index in PT1 |
---|
| 589 | uint32_t ix2; // index in PT2 |
---|
[1] | 590 | |
---|
[401] | 591 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[629] | 592 | uint32_t small; // requested PTE is for a small page |
---|
[401] | 593 | |
---|
[587] | 594 | // get cluster and local pointer on GPT |
---|
| 595 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 596 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 597 | |
---|
[1] | 598 | // compute indexes in PT1 and PT2 |
---|
| 599 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 600 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 601 | |
---|
[587] | 602 | pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 603 | small = attr & GPT_SMALL; |
---|
[1] | 604 | |
---|
[432] | 605 | // compute tsar attributes from generic attributes |
---|
[401] | 606 | tsar_attr = gpt2tsar( attr ); |
---|
| 607 | |
---|
[587] | 608 | // build extended pointer on PTE1 = PT1[ix1] |
---|
| 609 | pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] ); |
---|
[406] | 610 | |
---|
[587] | 611 | // get current pte1 value |
---|
| 612 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[1] | 613 | |
---|
[629] | 614 | if( small == 0 ) ///////////////// map a big page in PT1 |
---|
[401] | 615 | { |
---|
[623] | 616 | |
---|
| 617 | // check PT1 entry not mapped |
---|
[629] | 618 | assert( (pte1 == 0) , "try to set a big page in an already mapped PTE1\n" ); |
---|
[623] | 619 | |
---|
| 620 | // check VPN aligned |
---|
| 621 | assert( (ix2 == 0) , "illegal vpn for a big page\n" ); |
---|
| 622 | |
---|
| 623 | // check PPN aligned |
---|
| 624 | assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" ); |
---|
| 625 | |
---|
[587] | 626 | // set the PTE1 value in PT1 |
---|
| 627 | pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
---|
| 628 | hal_remote_s32( pte1_xp , pte1 ); |
---|
[124] | 629 | hal_fence(); |
---|
[587] | 630 | |
---|
| 631 | #if DEBUG_HAL_GPT_SET_PTE |
---|
[629] | 632 | thread_t * this = CURRENT_THREAD; |
---|
| 633 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
[587] | 634 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 635 | printk("\n[%s] : thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", |
---|
[587] | 636 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 637 | #endif |
---|
| 638 | |
---|
[1] | 639 | } |
---|
[629] | 640 | else ///////////////// map a small page in PT2 |
---|
[587] | 641 | { |
---|
[1] | 642 | |
---|
[629] | 643 | // PTE1 must be mapped because PTE2 must be locked |
---|
| 644 | assert( (pte1 & TSAR_PTE_MAPPED), "PTE1 must be mapped\n" ); |
---|
[1] | 645 | |
---|
[629] | 646 | // get PT2 base from PTE1 |
---|
| 647 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 648 | pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[315] | 649 | |
---|
[629] | 650 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
---|
| 651 | pte2_attr_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ); |
---|
| 652 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] ); |
---|
[1] | 653 | |
---|
[629] | 654 | // get current value of PTE2.attr |
---|
| 655 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
[587] | 656 | |
---|
[629] | 657 | // PTE2 must be locked |
---|
| 658 | assert( (pte2_attr & TSAR_PTE_LOCKED), "PTE2 must be locked\n" ); |
---|
| 659 | |
---|
[587] | 660 | // set PTE2 in PT2 (in this order) |
---|
[629] | 661 | hal_remote_s32( pte2_ppn_xp , ppn ); |
---|
[587] | 662 | hal_fence(); |
---|
[629] | 663 | hal_remote_s32( pte2_attr_xp , tsar_attr ); |
---|
[587] | 664 | hal_fence(); |
---|
[1] | 665 | |
---|
[587] | 666 | #if DEBUG_HAL_GPT_SET_PTE |
---|
[629] | 667 | thread_t * this = CURRENT_THREAD; |
---|
| 668 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
[587] | 669 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 670 | printk("\n[%s] : thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", |
---|
[587] | 671 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2_ptr, tsar_attr, ppn ); |
---|
[432] | 672 | #endif |
---|
| 673 | |
---|
[587] | 674 | } |
---|
[1] | 675 | } // end of hal_gpt_set_pte() |
---|
| 676 | |
---|
[629] | 677 | /////////////////////////////////////// |
---|
| 678 | void hal_gpt_reset_pte( xptr_t gpt_xp, |
---|
| 679 | vpn_t vpn ) |
---|
[1] | 680 | { |
---|
[629] | 681 | cxy_t gpt_cxy; // target GPT cluster |
---|
| 682 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
[1] | 683 | |
---|
[629] | 684 | uint32_t ix1; // index in PT1 |
---|
| 685 | uint32_t ix2; // index in PT2 |
---|
[1] | 686 | |
---|
[629] | 687 | uint32_t * pt1_ptr; // PT1 base address |
---|
| 688 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
| 689 | uint32_t pte1; // PT1 entry value |
---|
[587] | 690 | |
---|
[629] | 691 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 692 | uint32_t * pt2_ptr; // PT2 base address |
---|
| 693 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 694 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 695 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
[1] | 696 | |
---|
[629] | 697 | // get cluster and local pointer on GPT |
---|
| 698 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 699 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[1] | 700 | |
---|
[629] | 701 | // get ix1 & ix2 indexes |
---|
| 702 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 703 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[1] | 704 | |
---|
[629] | 705 | // get local pointer on PT1 base |
---|
| 706 | pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[1] | 707 | |
---|
[629] | 708 | // build extended pointer on PTE1 = PT1[ix1] |
---|
| 709 | pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] ); |
---|
[1] | 710 | |
---|
[629] | 711 | // get current PTE1 value |
---|
| 712 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[1] | 713 | |
---|
[629] | 714 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped => do nothing |
---|
[1] | 715 | { |
---|
| 716 | return; |
---|
| 717 | } |
---|
| 718 | |
---|
[629] | 719 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 => unmap it from PT1 |
---|
[1] | 720 | { |
---|
[629] | 721 | hal_remote_s32( pte1_xp , 0 ); |
---|
[124] | 722 | hal_fence(); |
---|
[1] | 723 | |
---|
[629] | 724 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
| 725 | thread_t * this = CURRENT_THREAD; |
---|
| 726 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 727 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
| 728 | printk("\n[%s] : thread[%x,%x] unmap PTE1 / cxy %x / vpn %x / ix1 %x\n", |
---|
| 729 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix1 ); |
---|
| 730 | #endif |
---|
| 731 | |
---|
[1] | 732 | return; |
---|
| 733 | } |
---|
[629] | 734 | else // it's a PTE2 => unmap it from PT2 |
---|
[1] | 735 | { |
---|
| 736 | // compute PT2 base address |
---|
| 737 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[629] | 738 | pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 739 | |
---|
[629] | 740 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
| 741 | pte2_attr_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ); |
---|
| 742 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] ); |
---|
| 743 | |
---|
| 744 | // unmap the PTE2 |
---|
| 745 | hal_remote_s32( pte2_attr_xp , 0 ); |
---|
[391] | 746 | hal_fence(); |
---|
[629] | 747 | hal_remote_s32( pte2_ppn_xp , 0 ); |
---|
| 748 | hal_fence(); |
---|
[1] | 749 | |
---|
[629] | 750 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
| 751 | thread_t * this = CURRENT_THREAD; |
---|
| 752 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 753 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
| 754 | printk("\n[%s] : thread[%x,%x] unmap PTE2 / cxy %x / vpn %x / ix2 %x\n", |
---|
| 755 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix2 ); |
---|
| 756 | #endif |
---|
| 757 | |
---|
[1] | 758 | return; |
---|
| 759 | } |
---|
| 760 | } // end hal_gpt_reset_pte() |
---|
| 761 | |
---|
[629] | 762 | //////////////////////////////////////// |
---|
| 763 | void hal_gpt_get_pte( xptr_t gpt_xp, |
---|
| 764 | vpn_t vpn, |
---|
| 765 | uint32_t * attr, |
---|
| 766 | ppn_t * ppn ) |
---|
[624] | 767 | { |
---|
[629] | 768 | uint32_t * pt1; // local pointer on PT1 base |
---|
| 769 | uint32_t pte1; // PTE1 value |
---|
[624] | 770 | |
---|
[629] | 771 | uint32_t * pt2; // local pointer on PT2 base |
---|
| 772 | ppn_t pt2_ppn; // PPN of page containing the PT2 |
---|
| 773 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 774 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 775 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
| 776 | ppn_t pte2_ppn; // current value of PT2[ix2].ppn |
---|
[624] | 777 | |
---|
[629] | 778 | // get cluster and local pointer on GPT |
---|
| 779 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 780 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
[624] | 781 | |
---|
[629] | 782 | // compute indexes in PT1 and PT2 |
---|
| 783 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 784 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[624] | 785 | |
---|
[629] | 786 | // get PT1 base |
---|
| 787 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 788 | |
---|
| 789 | // get pte1 |
---|
| 790 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[624] | 791 | |
---|
[629] | 792 | // check PTE1 mapped |
---|
| 793 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped |
---|
[1] | 794 | { |
---|
[629] | 795 | *attr = 0; |
---|
| 796 | *ppn = 0; |
---|
| 797 | return; |
---|
[1] | 798 | } |
---|
| 799 | |
---|
[629] | 800 | // access GPT |
---|
| 801 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 |
---|
| 802 | { |
---|
| 803 | // get PPN & ATTR from PT1 |
---|
| 804 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
| 805 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
[1] | 806 | } |
---|
[629] | 807 | else // it's a PTE2 |
---|
[1] | 808 | { |
---|
[629] | 809 | // compute PT2 base address |
---|
| 810 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 811 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 812 | |
---|
[629] | 813 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
| 814 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 815 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[1] | 816 | |
---|
[629] | 817 | // get current value of PTE2.attr & PTE2.ppn |
---|
| 818 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
| 819 | pte2_ppn = hal_remote_l32( pte2_ppn_xp ); |
---|
[1] | 820 | |
---|
[629] | 821 | // return PPN & GPT attributes |
---|
| 822 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
| 823 | *attr = tsar2gpt( pte2_attr ); |
---|
[1] | 824 | } |
---|
[629] | 825 | } // end hal_gpt_get_pte() |
---|
[1] | 826 | |
---|
| 827 | |
---|
[408] | 828 | /////////////////////////////////////////// |
---|
| 829 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
[625] | 830 | vpn_t dst_vpn, |
---|
[408] | 831 | xptr_t src_gpt_xp, |
---|
[625] | 832 | vpn_t src_vpn, |
---|
[408] | 833 | bool_t cow, |
---|
| 834 | ppn_t * ppn, |
---|
| 835 | bool_t * mapped ) |
---|
[23] | 836 | { |
---|
[625] | 837 | uint32_t src_ix1; // index in SRC PT1 |
---|
| 838 | uint32_t src_ix2; // index in SRC PT2 |
---|
[1] | 839 | |
---|
[625] | 840 | uint32_t dst_ix1; // index in DST PT1 |
---|
| 841 | uint32_t dst_ix2; // index in DST PT2 |
---|
| 842 | |
---|
[408] | 843 | cxy_t src_cxy; // SRC GPT cluster |
---|
| 844 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
[1] | 845 | |
---|
[408] | 846 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
| 847 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
| 848 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
| 849 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
| 850 | |
---|
[587] | 851 | kmem_req_t req; // for PT2 allocation |
---|
[407] | 852 | |
---|
| 853 | uint32_t src_pte1; |
---|
| 854 | uint32_t dst_pte1; |
---|
| 855 | |
---|
[408] | 856 | uint32_t src_pte2_attr; |
---|
| 857 | uint32_t src_pte2_ppn; |
---|
[1] | 858 | |
---|
[23] | 859 | page_t * page; |
---|
[315] | 860 | xptr_t page_xp; |
---|
[1] | 861 | |
---|
[23] | 862 | ppn_t src_pt2_ppn; |
---|
| 863 | ppn_t dst_pt2_ppn; |
---|
[1] | 864 | |
---|
[587] | 865 | // get remote src_gpt cluster and local pointer |
---|
| 866 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
| 867 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
| 868 | |
---|
| 869 | #if DEBUG_HAL_GPT_COPY |
---|
| 870 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 871 | thread_t * this = CURRENT_THREAD; |
---|
| 872 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[625] | 873 | printk("\n[%s] : thread[%x,%x] enter / src_cxy %x / dst_cxy %x / cycle %d\n", |
---|
| 874 | __FUNCTION__, this->process->pid, this->trdid, src_cxy, local_cxy, cycle ); |
---|
[432] | 875 | #endif |
---|
[407] | 876 | |
---|
[408] | 877 | // get remote src_gpt cluster and local pointer |
---|
| 878 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
[587] | 879 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
[407] | 880 | |
---|
[408] | 881 | // get remote src_pt1 and local dst_pt1 |
---|
| 882 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
[23] | 883 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 884 | |
---|
[408] | 885 | // check src_pt1 and dst_pt1 existence |
---|
[492] | 886 | assert( (src_pt1 != NULL) , "src_pt1 does not exist\n"); |
---|
| 887 | assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n"); |
---|
[407] | 888 | |
---|
[625] | 889 | // compute SRC indexes |
---|
| 890 | src_ix1 = TSAR_MMU_IX1_FROM_VPN( src_vpn ); |
---|
| 891 | src_ix2 = TSAR_MMU_IX2_FROM_VPN( src_vpn ); |
---|
[407] | 892 | |
---|
[625] | 893 | // compute DST indexes |
---|
| 894 | dst_ix1 = TSAR_MMU_IX1_FROM_VPN( dst_vpn ); |
---|
| 895 | dst_ix2 = TSAR_MMU_IX2_FROM_VPN( dst_vpn ); |
---|
| 896 | |
---|
[408] | 897 | // get src_pte1 |
---|
[625] | 898 | src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[src_ix1] ) ); |
---|
[407] | 899 | |
---|
[408] | 900 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
[629] | 901 | if( (src_pte1 & TSAR_PTE_MAPPED) && (src_pte1 & TSAR_PTE_SMALL) ) |
---|
[408] | 902 | { |
---|
| 903 | // get dst_pt1 entry |
---|
[625] | 904 | dst_pte1 = dst_pt1[dst_ix1]; |
---|
[407] | 905 | |
---|
[408] | 906 | // map dst_pte1 if required |
---|
[629] | 907 | if( (dst_pte1 & TSAR_PTE_MAPPED) == 0 ) |
---|
[408] | 908 | { |
---|
| 909 | // allocate one physical page for a new PT2 |
---|
| 910 | req.type = KMEM_PAGE; |
---|
| 911 | req.size = 0; // 1 small page |
---|
| 912 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 913 | page = (page_t *)kmem_alloc( &req ); |
---|
[407] | 914 | |
---|
[408] | 915 | if( page == NULL ) |
---|
| 916 | { |
---|
| 917 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 918 | return -1; |
---|
| 919 | } |
---|
[407] | 920 | |
---|
[408] | 921 | // build extended pointer on page descriptor |
---|
| 922 | page_xp = XPTR( local_cxy , page ); |
---|
[407] | 923 | |
---|
[408] | 924 | // get PPN for this new PT2 |
---|
| 925 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
[407] | 926 | |
---|
[408] | 927 | // build the new dst_pte1 |
---|
[629] | 928 | dst_pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | dst_pt2_ppn; |
---|
[407] | 929 | |
---|
[408] | 930 | // register it in DST_GPT |
---|
[625] | 931 | dst_pt1[dst_ix1] = dst_pte1; |
---|
[408] | 932 | } |
---|
[407] | 933 | |
---|
[408] | 934 | // get pointer on src_pt2 |
---|
| 935 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 ); |
---|
[587] | 936 | src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[407] | 937 | |
---|
[408] | 938 | // get pointer on dst_pt2 |
---|
| 939 | dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 ); |
---|
[587] | 940 | dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
[407] | 941 | |
---|
[408] | 942 | // get attr and ppn from SRC_PT2 |
---|
[625] | 943 | src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2] ) ); |
---|
| 944 | src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2 + 1] ) ); |
---|
[407] | 945 | |
---|
[408] | 946 | // do nothing if src_pte2 not MAPPED |
---|
[629] | 947 | if( (src_pte2_attr & TSAR_PTE_MAPPED) != 0 ) |
---|
[408] | 948 | { |
---|
| 949 | // set PPN in DST PTE2 |
---|
[625] | 950 | dst_pt2[2 * dst_ix2 + 1] = src_pte2_ppn; |
---|
[408] | 951 | |
---|
| 952 | // set attributes in DST PTE2 |
---|
[629] | 953 | if( cow && (src_pte2_attr & TSAR_PTE_WRITABLE) ) |
---|
[407] | 954 | { |
---|
[629] | 955 | dst_pt2[2 * dst_ix2] = (src_pte2_attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
---|
[408] | 956 | } |
---|
| 957 | else |
---|
| 958 | { |
---|
[625] | 959 | dst_pt2[2 * dst_ix2] = src_pte2_attr; |
---|
[408] | 960 | } |
---|
[407] | 961 | |
---|
[408] | 962 | // return "successfully copied" |
---|
| 963 | *mapped = true; |
---|
| 964 | *ppn = src_pte2_ppn; |
---|
| 965 | |
---|
[587] | 966 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 967 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 968 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[625] | 969 | printk("\n[%s] : thread[%x,%x] exit / copy done for src_vpn %x / dst_vpn %x / cycle %d\n", |
---|
| 970 | __FUNCTION__, this->process->pid, this->trdid, src_vpn, dst_vpn, cycle ); |
---|
[432] | 971 | #endif |
---|
[407] | 972 | |
---|
[408] | 973 | hal_fence(); |
---|
[407] | 974 | |
---|
[408] | 975 | return 0; |
---|
| 976 | } // end if PTE2 mapped |
---|
| 977 | } // end if PTE1 mapped |
---|
| 978 | |
---|
| 979 | // return "nothing done" |
---|
| 980 | *mapped = false; |
---|
| 981 | *ppn = 0; |
---|
[432] | 982 | |
---|
[587] | 983 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 984 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 985 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[625] | 986 | printk("\n[%s] : thread[%x,%x] exit / nothing done / cycle %d\n", |
---|
| 987 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
---|
[432] | 988 | #endif |
---|
[408] | 989 | |
---|
[407] | 990 | hal_fence(); |
---|
| 991 | |
---|
| 992 | return 0; |
---|
| 993 | |
---|
[408] | 994 | } // end hal_gpt_pte_copy() |
---|
[407] | 995 | |
---|
[408] | 996 | ///////////////////////////////////////// |
---|
[432] | 997 | void hal_gpt_set_cow( xptr_t gpt_xp, |
---|
| 998 | vpn_t vpn_base, |
---|
| 999 | vpn_t vpn_size ) |
---|
[408] | 1000 | { |
---|
| 1001 | cxy_t gpt_cxy; |
---|
| 1002 | gpt_t * gpt_ptr; |
---|
[407] | 1003 | |
---|
[408] | 1004 | vpn_t vpn; |
---|
[407] | 1005 | |
---|
[408] | 1006 | uint32_t ix1; |
---|
| 1007 | uint32_t ix2; |
---|
[407] | 1008 | |
---|
[408] | 1009 | uint32_t * pt1; |
---|
| 1010 | uint32_t pte1; |
---|
[407] | 1011 | |
---|
[408] | 1012 | uint32_t * pt2; |
---|
| 1013 | ppn_t pt2_ppn; |
---|
[432] | 1014 | uint32_t attr; |
---|
[407] | 1015 | |
---|
[408] | 1016 | // get GPT cluster and local pointer |
---|
| 1017 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1018 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[407] | 1019 | |
---|
[408] | 1020 | // get local PT1 pointer |
---|
| 1021 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[407] | 1022 | |
---|
[408] | 1023 | // loop on pages |
---|
| 1024 | for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ ) |
---|
| 1025 | { |
---|
| 1026 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1027 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[407] | 1028 | |
---|
[408] | 1029 | // get PTE1 value |
---|
[570] | 1030 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[407] | 1031 | |
---|
[408] | 1032 | // only MAPPED & SMALL PTEs are modified |
---|
[629] | 1033 | if( (pte1 & TSAR_PTE_MAPPED) && (pte1 & TSAR_PTE_SMALL) ) |
---|
[408] | 1034 | { |
---|
| 1035 | // compute PT2 base address |
---|
| 1036 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1037 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[407] | 1038 | |
---|
[492] | 1039 | assert( (GET_CXY( ppm_ppn2base( pt2_ppn ) ) == gpt_cxy ), |
---|
[408] | 1040 | "PT2 and PT1 must be in the same cluster\n"); |
---|
| 1041 | |
---|
| 1042 | // get current PTE2 attributes |
---|
[570] | 1043 | attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
---|
[408] | 1044 | |
---|
| 1045 | // only MAPPED PTEs are modified |
---|
[629] | 1046 | if( attr & TSAR_PTE_MAPPED ) |
---|
[23] | 1047 | { |
---|
[629] | 1048 | attr = (attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
---|
[570] | 1049 | hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); |
---|
[432] | 1050 | } |
---|
| 1051 | } |
---|
[408] | 1052 | } // end loop on pages |
---|
[23] | 1053 | |
---|
[432] | 1054 | } // end hal_gpt_set_cow() |
---|
[315] | 1055 | |
---|
[408] | 1056 | ////////////////////////////////////////// |
---|
| 1057 | void hal_gpt_update_pte( xptr_t gpt_xp, |
---|
| 1058 | vpn_t vpn, |
---|
| 1059 | uint32_t attr, // generic GPT attributes |
---|
| 1060 | ppn_t ppn ) |
---|
| 1061 | { |
---|
| 1062 | uint32_t * pt1; // PT1 base addres |
---|
| 1063 | uint32_t pte1; // PT1 entry value |
---|
[23] | 1064 | |
---|
[408] | 1065 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 1066 | uint32_t * pt2; // PT2 base address |
---|
[23] | 1067 | |
---|
[408] | 1068 | uint32_t ix1; // index in PT1 |
---|
| 1069 | uint32_t ix2; // index in PT2 |
---|
[23] | 1070 | |
---|
[408] | 1071 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[23] | 1072 | |
---|
[408] | 1073 | // check attr argument MAPPED and SMALL |
---|
| 1074 | if( (attr & GPT_MAPPED) == 0 ) return; |
---|
| 1075 | if( (attr & GPT_SMALL ) == 0 ) return; |
---|
[23] | 1076 | |
---|
[408] | 1077 | // get cluster and local pointer on remote GPT |
---|
| 1078 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1079 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
[23] | 1080 | |
---|
[408] | 1081 | // compute indexes in PT1 and PT2 |
---|
| 1082 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1083 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[23] | 1084 | |
---|
[408] | 1085 | // get PT1 base |
---|
| 1086 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[23] | 1087 | |
---|
[408] | 1088 | // compute tsar_attr from generic attributes |
---|
| 1089 | tsar_attr = gpt2tsar( attr ); |
---|
[23] | 1090 | |
---|
[408] | 1091 | // get PTE1 value |
---|
[570] | 1092 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[23] | 1093 | |
---|
[629] | 1094 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) return; |
---|
| 1095 | if( (pte1 & TSAR_PTE_SMALL ) == 0 ) return; |
---|
[408] | 1096 | |
---|
| 1097 | // get PT2 base from PTE1 |
---|
| 1098 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1099 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 1100 | |
---|
| 1101 | // set PTE2 in this order |
---|
[570] | 1102 | hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2 + 1] ) , ppn ); |
---|
[408] | 1103 | hal_fence(); |
---|
[570] | 1104 | hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2] ) , tsar_attr ); |
---|
[408] | 1105 | hal_fence(); |
---|
| 1106 | |
---|
| 1107 | } // end hal_gpt_update_pte() |
---|
| 1108 | |
---|
[629] | 1109 | |
---|
| 1110 | |
---|
| 1111 | |
---|
| 1112 | /* unused until now (march 2019) [AG] |
---|
| 1113 | |
---|
| 1114 | ////////////////////////////////////// |
---|
| 1115 | void hal_gpt_reset_range( gpt * gpt, |
---|
| 1116 | vpn_t vpn_min, |
---|
| 1117 | vpn_t vpn_max ) |
---|
| 1118 | { |
---|
| 1119 | vpn_t vpn; // current vpn |
---|
| 1120 | |
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| 1121 | uint32_t * pt1; // PT1 base address |
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| 1122 | uint32_t pte1; // PT1 entry value |
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| 1123 | |
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| 1124 | ppn_t pt2_ppn; // PPN of PT2 |
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| 1125 | uint32_t * pt2; // PT2 base address |
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| 1126 | |
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| 1127 | uint32_t ix1; // index in PT1 |
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| 1128 | uint32_t ix2; // index in PT2 |
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| 1129 | |
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| 1130 | // get PT1 |
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| 1131 | pt1 = gpt->ptr; |
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| 1132 | |
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| 1133 | // initialize current index |
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| 1134 | vpn = vpn_min; |
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| 1135 | |
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| 1136 | // loop on pages |
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| 1137 | while( vpn <= vpn_max ) |
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| 1138 | { |
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| 1139 | // get ix1 index from vpn |
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| 1140 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 1141 | |
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| 1142 | // get PTE1 |
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| 1143 | pte1 = pt1[ix1] |
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| 1144 | |
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| 1145 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PT1[ix1] unmapped |
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| 1146 | { |
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| 1147 | // update vpn (next big page) |
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| 1148 | (vpn = ix1 + 1) << 9; |
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| 1149 | } |
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| 1150 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 (big page) |
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| 1151 | { |
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| 1152 | // unmap the big page |
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| 1153 | pt1[ix1] = 0; |
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| 1154 | hal_fence(); |
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| 1155 | |
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| 1156 | // update vpn (next big page) |
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| 1157 | (vpn = ix1 + 1) << 9; |
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| 1158 | } |
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| 1159 | else // it's a PTD1 (small page) |
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| 1160 | { |
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| 1161 | // compute PT2 base address |
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| 1162 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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| 1163 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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| 1164 | |
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| 1165 | // get ix2 index from vpn |
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| 1166 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 1167 | |
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| 1168 | // unmap the small page |
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| 1169 | pt2[2*ix2] = 0; |
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| 1170 | hal_fence(); |
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| 1171 | |
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| 1172 | // update vpn (next small page) |
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| 1173 | vpn++; |
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| 1174 | } |
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| 1175 | } |
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| 1176 | } // hal_gpt_reset_range() |
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| 1177 | */ |
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| 1178 | |
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| 1179 | |
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