[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.h |
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[648] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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| 9 | #ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 10 | #define SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 11 | |
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| 12 | #include <systemc> |
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| 13 | #include <sys/time.h> |
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| 14 | #include <iostream> |
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| 15 | #include <sstream> |
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| 16 | #include <cstdlib> |
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| 17 | #include <cstdarg> |
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| 18 | |
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| 19 | #include "gdbserver.h" |
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| 20 | #include "mapping_table.h" |
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| 21 | #include "mips32.h" |
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| 22 | #include "vci_simple_ram.h" |
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[658] | 23 | #include "vci_simple_rom.h" |
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[450] | 24 | #include "vci_xicu.h" |
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[696] | 25 | #include "vci_local_crossbar.h" |
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[450] | 26 | #include "dspin_local_crossbar.h" |
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| 27 | #include "vci_dspin_initiator_wrapper.h" |
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| 28 | #include "vci_dspin_target_wrapper.h" |
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[550] | 29 | #include "dspin_router_tsar.h" |
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[450] | 30 | #include "virtual_dspin_router.h" |
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| 31 | #include "vci_multi_dma.h" |
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| 32 | #include "vci_mem_cache.h" |
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| 33 | #include "vci_cc_vcache_wrapper.h" |
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| 34 | #include "vci_io_bridge.h" |
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[695] | 35 | #include "vci_multi_tty.h" |
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| 36 | #include "hard_config.h" |
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[450] | 37 | |
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[695] | 38 | /////////////////////////////////////////////////////////////////////// |
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| 39 | // Number of channels for debug TTY (may be 0) |
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| 40 | /////////////////////////////////////////////////////////////////////// |
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| 41 | #define NB_DEBUG_TTY_CHANNELS 1 |
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| 42 | |
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| 43 | /////////////////////////////////////////////////////////////////////// |
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| 44 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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| 45 | /////////////////////////////////////////////////////////////////////// |
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| 46 | |
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| 47 | #define INT_MEMC_TGT_ID 0 |
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| 48 | #define INT_XICU_TGT_ID 1 |
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| 49 | #define INT_BROM_TGT_ID 2 |
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| 50 | #define INT_MDMA_TGT_ID 3 |
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| 51 | #define INT_MTTY_TGT_ID 4 |
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| 52 | #define INT_IOBX_TGT_ID (4 + (NB_DEBUG_TTY_CHANNELS ? 1 : 0)) |
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| 53 | |
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| 54 | #define INT_PROC_INI_ID 0 // from 0 to 7 |
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| 55 | #define INT_MDMA_INI_ID NB_PROCS |
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| 56 | #define INT_IOBX_INI_ID (NB_PROCS + 1) |
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| 57 | |
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| 58 | /////////////////////////////////////////////////////////////////////// |
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| 59 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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| 60 | /////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #define RAM_XRAM_TGT_ID 0 |
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| 63 | |
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| 64 | #define RAM_MEMC_INI_ID 0 |
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| 65 | #define RAM_IOBX_INI_ID 1 |
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| 66 | |
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[648] | 67 | namespace soclib { namespace caba { |
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[450] | 68 | |
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| 69 | /////////////////////////////////////////////////////////////////////////// |
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[648] | 70 | template<typename vci_param_int, |
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[450] | 71 | typename vci_param_ext, |
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[648] | 72 | size_t dspin_int_cmd_width, |
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[450] | 73 | size_t dspin_int_rsp_width, |
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| 74 | size_t dspin_ram_cmd_width, |
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| 75 | size_t dspin_ram_rsp_width> |
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[648] | 76 | class TsarIobCluster |
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[450] | 77 | /////////////////////////////////////////////////////////////////////////// |
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| 78 | : public soclib::caba::BaseModule |
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| 79 | { |
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| 80 | |
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[648] | 81 | public: |
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[450] | 82 | |
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[648] | 83 | // Ports |
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| 84 | sc_in<bool> p_clk; |
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| 85 | sc_in<bool> p_resetn; |
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[450] | 86 | |
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[648] | 87 | // Thes two ports are used to connect IOB to IOX nework in top cell |
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| 88 | soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; |
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| 89 | soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; |
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[450] | 90 | |
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[648] | 91 | // These ports are used to connect IOB to RAM network in top cell |
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| 92 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out; |
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| 93 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; |
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[450] | 94 | |
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[648] | 95 | // These ports are used to connect hard IRQ from external peripherals to |
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| 96 | // IOB0 |
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| 97 | sc_in<bool>* p_irq[32]; |
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[550] | 98 | |
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[648] | 99 | // These arrays of ports are used to connect the INT & RAM networks in |
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| 100 | // top cell |
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| 101 | soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; |
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| 102 | soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; |
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| 103 | soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; |
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| 104 | soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; |
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[450] | 105 | |
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[648] | 106 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; |
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| 107 | soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; |
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| 108 | soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; |
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| 109 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; |
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[450] | 110 | |
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[648] | 111 | // interrupt signals |
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| 112 | sc_signal<bool> signal_false; |
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| 113 | sc_signal<bool> signal_proc_it[8]; |
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| 114 | sc_signal<bool> signal_irq_mdma[8]; |
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[695] | 115 | sc_signal<bool> signal_irq_mtty[8]; |
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[648] | 116 | sc_signal<bool> signal_irq_memc; |
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[450] | 117 | |
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[648] | 118 | // INT network DSPIN signals between DSPIN routers and DSPIN |
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| 119 | // local_crossbars |
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| 120 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; |
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| 121 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; |
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[696] | 122 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; |
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| 123 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; |
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[648] | 124 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; |
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| 125 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; |
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| 126 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; |
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| 127 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; |
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| 128 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; |
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| 129 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; |
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[450] | 130 | |
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[696] | 131 | // INT network VCI signals between VCI components and VCI local crossbar |
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[648] | 132 | VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; |
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| 133 | VciSignals<vci_param_int> signal_int_vci_ini_mdma; |
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| 134 | VciSignals<vci_param_int> signal_int_vci_ini_iobx; |
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[450] | 135 | |
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[648] | 136 | VciSignals<vci_param_int> signal_int_vci_tgt_memc; |
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| 137 | VciSignals<vci_param_int> signal_int_vci_tgt_xicu; |
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[658] | 138 | VciSignals<vci_param_int> signal_int_vci_tgt_brom; |
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[695] | 139 | VciSignals<vci_param_int> signal_int_vci_tgt_mtty; |
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[648] | 140 | VciSignals<vci_param_int> signal_int_vci_tgt_mdma; |
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| 141 | VciSignals<vci_param_int> signal_int_vci_tgt_iobx; |
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[450] | 142 | |
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[696] | 143 | VciSignals<vci_param_int> signal_int_vci_l2g; |
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| 144 | VciSignals<vci_param_int> signal_int_vci_g2l; |
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[450] | 145 | |
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[648] | 146 | // Coherence DSPIN signals between DSPIN local crossbars and CC |
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| 147 | // components |
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| 148 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; |
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| 149 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; |
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| 150 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; |
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| 151 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; |
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| 152 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; |
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| 153 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; |
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[450] | 154 | |
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[648] | 155 | // RAM network VCI signals between VCI components and VCI/DSPIN wrappers |
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| 156 | VciSignals<vci_param_ext> signal_ram_vci_ini_memc; |
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| 157 | VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; |
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| 158 | VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; |
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[450] | 159 | |
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[648] | 160 | // RAM network DSPIN signals between VCI/DSPIN wrappers and routers |
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| 161 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; |
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| 162 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; |
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| 163 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; |
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| 164 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; |
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[450] | 165 | |
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[648] | 166 | ////////////////////////////////////// |
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| 167 | // Hardwate Components (pointers) |
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| 168 | ////////////////////////////////////// |
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| 169 | typedef VciCcVCacheWrapper<vci_param_int, dspin_int_cmd_width, |
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| 170 | dspin_int_rsp_width, GdbServer<Mips32ElIss> > |
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| 171 | VciCcVCacheWrapperType; |
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[450] | 172 | |
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[648] | 173 | typedef VciMemCache<vci_param_int, vci_param_ext, dspin_int_rsp_width, |
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| 174 | dspin_int_cmd_width> VciMemCacheType; |
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[450] | 175 | |
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[648] | 176 | typedef VciDspinInitiatorWrapper<vci_param_int, dspin_int_cmd_width, |
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| 177 | dspin_int_rsp_width> VciIntDspinInitiatorWrapperType; |
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[450] | 178 | |
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[648] | 179 | typedef VciDspinTargetWrapper<vci_param_int, dspin_int_cmd_width, |
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| 180 | dspin_int_rsp_width> VciIntDspinTargetWrapperType; |
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[450] | 181 | |
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[648] | 182 | typedef VciDspinInitiatorWrapper<vci_param_ext, dspin_ram_cmd_width, |
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| 183 | dspin_ram_rsp_width> VciExtDspinInitiatorWrapperType; |
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[450] | 184 | |
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[648] | 185 | typedef VciDspinTargetWrapper<vci_param_ext, dspin_ram_cmd_width, |
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| 186 | dspin_ram_rsp_width> VciExtDspinTargetWrapperType; |
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[450] | 187 | |
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[648] | 188 | VciCcVCacheWrapperType* proc[8]; |
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[450] | 189 | |
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[648] | 190 | VciMemCacheType* memc; |
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| 191 | VciExtDspinInitiatorWrapperType* memc_ram_wi; |
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[450] | 192 | |
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[648] | 193 | VciXicu<vci_param_int>* xicu; |
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[450] | 194 | |
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[648] | 195 | VciMultiDma<vci_param_int>* mdma; |
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[450] | 196 | |
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[658] | 197 | VciSimpleRom<vci_param_int>* brom; |
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| 198 | |
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[695] | 199 | VciMultiTty<vci_param_int>* mtty; |
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| 200 | |
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[696] | 201 | VciLocalCrossbar<vci_param_int>* int_xbar_d; |
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| 202 | VciIntDspinInitiatorWrapperType* int_wi_gate_d; |
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| 203 | VciIntDspinTargetWrapperType* int_wt_gate_d; |
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| 204 | |
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[648] | 205 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; |
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| 206 | DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; |
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| 207 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; |
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[450] | 208 | |
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[648] | 209 | VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; |
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| 210 | VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; |
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[450] | 211 | |
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[648] | 212 | VciSimpleRam<vci_param_ext>* xram; |
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| 213 | VciExtDspinTargetWrapperType* xram_ram_wt; |
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[450] | 214 | |
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[648] | 215 | DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; |
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| 216 | DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; |
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[450] | 217 | |
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[648] | 218 | // IO Network Components (not instanciated in all clusters) |
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[450] | 219 | |
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[648] | 220 | VciIoBridge<vci_param_int, vci_param_ext>* iob; |
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| 221 | VciExtDspinInitiatorWrapperType* iob_ram_wi; |
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[450] | 222 | |
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[648] | 223 | size_t m_procs; |
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[450] | 224 | |
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[648] | 225 | struct ClusterParams { |
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| 226 | sc_module_name insname; |
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[450] | 227 | |
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[648] | 228 | size_t x_id; |
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| 229 | size_t y_id; |
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[450] | 230 | |
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[648] | 231 | const soclib::common::MappingTable &mt_int; |
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| 232 | const soclib::common::MappingTable &mt_ext; |
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| 233 | const soclib::common::MappingTable &mt_iox; |
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[450] | 234 | |
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[648] | 235 | size_t memc_ways; |
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| 236 | size_t memc_sets; |
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| 237 | size_t l1_i_ways; |
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| 238 | size_t l1_i_sets; |
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| 239 | size_t l1_d_ways; |
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| 240 | size_t l1_d_sets; |
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| 241 | size_t xram_latency; |
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[450] | 242 | |
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[648] | 243 | const Loader& loader; |
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[450] | 244 | |
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[648] | 245 | uint32_t frozen_cycles; |
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| 246 | uint32_t debug_start_cycle; |
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| 247 | bool memc_debug_ok; |
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| 248 | bool proc_debug_ok; |
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| 249 | bool iob_debug_ok; |
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| 250 | }; |
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[450] | 251 | |
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[695] | 252 | // utility functions |
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| 253 | static uint32_t clusterId(size_t x_id, size_t y_id) { |
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| 254 | return ((x_id << Y_WIDTH) | y_id); |
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| 255 | }; |
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| 256 | |
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[648] | 257 | // cluster constructor |
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| 258 | TsarIobCluster(struct ClusterParams& params); |
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| 259 | ~TsarIobCluster(); |
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[450] | 260 | }; |
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| 261 | |
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| 262 | }} |
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| 263 | |
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| 264 | #endif |
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[648] | 265 | |
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| 266 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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