[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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[648] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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| 9 | // Modified on: mars 2014 |
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[450] | 10 | ////////////////////////////////////////////////////////////////////////////// |
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| 11 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 12 | // These two clusters contain 6 extra components: |
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| 13 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 14 | // - 3 vci_dspin_wrapper for the IOB. |
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| 15 | // - 2 dspin_local_crossbar for commands and responses. |
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| 16 | ////////////////////////////////////////////////////////////////////////////// |
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| 17 | |
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| 18 | #include "../include/tsar_iob_cluster.h" |
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| 19 | |
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[648] | 20 | #define tmpl(x) \ |
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| 21 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 22 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 23 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 24 | x TsarIobCluster<\ |
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| 25 | vci_param_int , vci_param_ext,\ |
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| 26 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 27 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 28 | |
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[450] | 29 | namespace soclib { namespace caba { |
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| 30 | |
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| 31 | ////////////////////////////////////////////////////////////////////////// |
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| 32 | // Constructor |
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| 33 | ////////////////////////////////////////////////////////////////////////// |
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[648] | 34 | tmpl(/**/)::TsarIobCluster(struct ClusterParams& params) : |
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| 35 | soclib::caba::BaseModule(params.insname), p_clk("clk"), p_resetn("resetn") |
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| 36 | { |
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| 37 | assert((params.x_id < params.x_size) and (params.y_id < params.y_size)); |
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[450] | 38 | |
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[648] | 39 | this->m_procs = params.nb_procs; |
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| 40 | size_t cluster_id = (params.x_id << 4) + params.y_id; |
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[450] | 41 | |
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[648] | 42 | size_t cluster_iob0 = 0; |
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| 43 | size_t cluster_iob1 = ((params.x_size - 1) << 4) + params.y_size - 1; |
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[450] | 44 | |
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[648] | 45 | // Vectors of DSPIN ports for inter-cluster communications |
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| 46 | p_dspin_int_cmd_in = |
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| 47 | alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 48 | p_dspin_int_cmd_out = |
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| 49 | alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 50 | p_dspin_int_rsp_in = |
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| 51 | alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 52 | p_dspin_int_rsp_out = |
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| 53 | alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 54 | |
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[648] | 55 | p_dspin_ram_cmd_in = |
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| 56 | alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 57 | p_dspin_ram_cmd_out = |
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| 58 | alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 59 | p_dspin_ram_rsp_in = |
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| 60 | alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 61 | p_dspin_ram_rsp_out = |
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| 62 | alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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[450] | 63 | |
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[648] | 64 | // ports in cluster_iob0 and cluster_iob1 only |
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| 65 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 66 | { |
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| 67 | // VCI ports from IOB to IOX network |
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| 68 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 69 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[450] | 70 | |
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[648] | 71 | // DSPIN ports from IOB to RAM network |
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| 72 | p_dspin_iob_cmd_out = |
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| 73 | new soclib::caba::DspinOutput<dspin_ram_cmd_width>; |
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| 74 | p_dspin_iob_rsp_in = |
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| 75 | new soclib::caba::DspinInput<dspin_ram_rsp_width>; |
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| 76 | } |
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| 77 | else |
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| 78 | { |
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| 79 | p_vci_iob_iox_ini = NULL; |
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| 80 | p_vci_iob_iox_tgt = NULL; |
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| 81 | p_dspin_iob_cmd_out = NULL; |
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| 82 | p_dspin_iob_rsp_in = NULL; |
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| 83 | } |
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[450] | 84 | |
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[648] | 85 | // IRQ ports in cluster_iob0 only |
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| 86 | for ( size_t n = 0 ; n < 32 ; n++ ) |
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| 87 | { |
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| 88 | if ( cluster_id == cluster_iob0 ) |
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| 89 | { |
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| 90 | p_irq[n] = new sc_in<bool>; |
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| 91 | } |
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| 92 | else |
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| 93 | { |
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| 94 | p_irq[n] = NULL; |
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| 95 | } |
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| 96 | } |
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[450] | 97 | |
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[648] | 98 | /////////////////////////////////////////////////////////////////////////// |
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| 99 | // Hardware components |
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| 100 | /////////////////////////////////////////////////////////////////////////// |
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[450] | 101 | |
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[648] | 102 | //////////// PROCS |
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| 103 | for (size_t p = 0; p < params.nb_procs; p++) |
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| 104 | { |
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| 105 | std::ostringstream s_proc; |
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| 106 | s_proc << "proc_" << params.x_id << "_" << params.y_id << "_" << p; |
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| 107 | proc[p] = new VciCcVCacheWrapperType ( |
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| 108 | s_proc.str().c_str(), |
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| 109 | cluster_id * params.nb_procs + p, |
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| 110 | params.mt_int, |
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| 111 | IntTab(cluster_id,p), |
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| 112 | (cluster_id << params.l_width) + p, |
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| 113 | 8, 8, |
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| 114 | 8, 8, |
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| 115 | params.l1_i_ways, params.l1_i_sets, 16, |
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| 116 | params.l1_d_ways, params.l1_d_sets, 16, |
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| 117 | 4, 4, |
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| 118 | params.x_width, params.y_width, |
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| 119 | params.frozen_cycles, |
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| 120 | params.debug_start_cycle, params.proc_debug_ok); |
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[450] | 121 | |
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[648] | 122 | std::ostringstream s_wi_proc; |
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| 123 | s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" |
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| 124 | << p; |
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| 125 | proc_wi[p] = new VciIntDspinInitiatorWrapperType( |
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| 126 | s_wi_proc.str().c_str(), |
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| 127 | params.x_width + params.y_width + params.l_width); |
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| 128 | } |
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[450] | 129 | |
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[648] | 130 | /////////// MEMC |
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| 131 | std::ostringstream s_memc; |
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| 132 | s_memc << "memc_" << params.x_id << "_" << params.y_id; |
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| 133 | memc = new VciMemCacheType ( |
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| 134 | s_memc.str().c_str(), |
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| 135 | params.mt_int, |
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| 136 | params.mt_ext, |
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| 137 | IntTab(cluster_id, params.ext_memc_srcid), |
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| 138 | IntTab(cluster_id, params.int_memc_tgtid), |
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| 139 | params.x_width, |
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| 140 | params.y_width, |
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| 141 | params.memc_ways, params.memc_sets, 16, |
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| 142 | 3, |
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| 143 | 4096, |
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| 144 | 8, |
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| 145 | 8, |
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| 146 | 8, |
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| 147 | params.debug_start_cycle, |
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| 148 | params.memc_debug_ok); |
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[550] | 149 | |
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[648] | 150 | std::ostringstream s_wt_memc; |
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| 151 | s_wt_memc << "memc_wt_" << params.x_id << "_" << params.y_id; |
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| 152 | memc_int_wt = new VciIntDspinTargetWrapperType ( |
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| 153 | s_wt_memc.str().c_str(), |
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| 154 | params.x_width + params.y_width + params.l_width); |
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[450] | 155 | |
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[648] | 156 | std::ostringstream s_wi_memc; |
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| 157 | s_wi_memc << "memc_wi_" << params.x_id << "_" << params.y_id; |
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| 158 | memc_ram_wi = new VciExtDspinInitiatorWrapperType ( |
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| 159 | s_wi_memc.str().c_str(), |
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| 160 | params.x_width + params.y_width + params.l_width); |
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[450] | 161 | |
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[658] | 162 | /////////// LOCAL ROM |
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| 163 | brom = new VciSimpleRom<vci_param_int>( |
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| 164 | "brom", |
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| 165 | IntTab(cluster_id, params.int_brom_tgtid), |
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| 166 | params.mt_int, |
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| 167 | params.loader, |
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| 168 | params.x_width + params.y_width); |
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| 169 | |
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| 170 | std::ostringstream s_wt_brom; |
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| 171 | s_wt_brom << "brom_wt_" << params.x_id << "_" << params.y_id; |
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| 172 | brom_int_wt = new VciIntDspinTargetWrapperType ( |
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| 173 | s_wt_brom.str().c_str(), |
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| 174 | params.x_width + params.y_width + params.l_width); |
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| 175 | |
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[648] | 176 | /////////// XICU |
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| 177 | std::ostringstream s_xicu; |
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| 178 | s_xicu << "xicu_" << params.x_id << "_" << params.y_id; |
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| 179 | xicu = new VciXicu<vci_param_int>( |
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| 180 | s_xicu.str().c_str(), |
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| 181 | params.mt_int, |
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| 182 | IntTab(cluster_id,params.int_xicu_tgtid), |
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| 183 | 32, 32, 32, |
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| 184 | params.nb_procs); |
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[550] | 185 | |
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[648] | 186 | std::ostringstream s_wt_xicu; |
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| 187 | s_wt_xicu << "xicu_wt_" << params.x_id << "_" << params.y_id; |
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| 188 | xicu_int_wt = new VciIntDspinTargetWrapperType ( |
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| 189 | s_wt_xicu.str().c_str(), |
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| 190 | params.x_width + params.y_width + params.l_width); |
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[450] | 191 | |
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[648] | 192 | //////////// MDMA |
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| 193 | std::ostringstream s_mdma; |
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| 194 | s_mdma << "mdma_" << params.x_id << "_" << params.y_id; |
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| 195 | mdma = new VciMultiDma<vci_param_int>( |
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| 196 | s_mdma.str().c_str(), |
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| 197 | params.mt_int, |
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| 198 | IntTab(cluster_id, params.nb_procs), |
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| 199 | IntTab(cluster_id, params.int_mdma_tgtid), |
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| 200 | 64, |
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| 201 | params.nb_dmas); |
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[450] | 202 | |
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[648] | 203 | std::ostringstream s_wt_mdma; |
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| 204 | s_wt_mdma << "mdma_wt_" << params.x_id << "_" << params.y_id; |
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| 205 | mdma_int_wt = new VciIntDspinTargetWrapperType( |
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| 206 | s_wt_mdma.str().c_str(), |
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| 207 | params.x_width + params.y_width + params.l_width); |
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[450] | 208 | |
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[648] | 209 | std::ostringstream s_wi_mdma; |
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| 210 | s_wi_mdma << "mdma_wi_" << params.x_id << "_" << params.y_id; |
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| 211 | mdma_int_wi = new VciIntDspinInitiatorWrapperType( |
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| 212 | s_wi_mdma.str().c_str(), |
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| 213 | params.x_width + params.y_width + params.l_width); |
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[450] | 214 | |
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[648] | 215 | /////////// Direct LOCAL_XBAR(S) |
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| 216 | size_t nb_direct_initiators = params.nb_procs + 1; |
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[658] | 217 | size_t nb_direct_targets = 4; |
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[648] | 218 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
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| 219 | { |
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| 220 | nb_direct_initiators = params.nb_procs + 2; |
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[658] | 221 | nb_direct_targets = 5; |
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[648] | 222 | } |
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[450] | 223 | |
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[648] | 224 | std::ostringstream s_int_xbar_cmd_d; |
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| 225 | s_int_xbar_cmd_d << "int_xbar_cmd_d_" << params.x_id << "_" << params.y_id; |
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| 226 | int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 227 | s_int_xbar_cmd_d.str().c_str(), |
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| 228 | params.mt_int, |
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| 229 | params.x_id, params.y_id, |
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| 230 | params.x_width, params.y_width, params.l_width, |
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| 231 | nb_direct_initiators, |
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| 232 | nb_direct_targets, |
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| 233 | 2, 2, |
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| 234 | true, |
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| 235 | true, |
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| 236 | false); |
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[450] | 237 | |
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[648] | 238 | std::ostringstream s_int_xbar_rsp_d; |
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| 239 | s_int_xbar_rsp_d << "int_xbar_rsp_d_" << params.x_id << "_" << params.y_id; |
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| 240 | int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 241 | s_int_xbar_rsp_d.str().c_str(), |
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| 242 | params.mt_int, |
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| 243 | params.x_id, params.y_id, |
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| 244 | params.x_width, params.y_width, params.l_width, |
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| 245 | nb_direct_targets, |
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| 246 | nb_direct_initiators, |
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| 247 | 2, 2, |
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| 248 | false, |
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| 249 | false, |
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| 250 | false); |
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[450] | 251 | |
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[648] | 252 | //////////// Coherence LOCAL_XBAR(S) |
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| 253 | std::ostringstream s_int_xbar_m2p_c; |
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| 254 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << params.x_id << "_" << params.y_id; |
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| 255 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 256 | s_int_xbar_m2p_c.str().c_str(), |
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| 257 | params.mt_int, |
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| 258 | params.x_id, params.y_id, |
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| 259 | params.x_width, params.y_width, params.l_width, |
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| 260 | 1, |
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| 261 | params.nb_procs, |
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| 262 | 2, 2, |
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| 263 | true, |
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| 264 | false, |
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| 265 | true); |
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[450] | 266 | |
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[648] | 267 | std::ostringstream s_int_xbar_p2m_c; |
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| 268 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << params.x_id << "_" << params.y_id; |
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| 269 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 270 | s_int_xbar_p2m_c.str().c_str(), |
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| 271 | params.mt_int, |
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| 272 | params.x_id, params.y_id, |
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| 273 | params.x_width, params.y_width, 0, |
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| 274 | params.nb_procs, |
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| 275 | 1, |
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| 276 | 2, 2, |
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| 277 | false, |
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| 278 | false, |
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| 279 | false); |
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[450] | 280 | |
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[648] | 281 | std::ostringstream s_int_xbar_clack_c; |
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| 282 | s_int_xbar_clack_c << "int_xbar_clack_c_" << params.x_id << "_" |
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| 283 | << params.y_id; |
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| 284 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 285 | s_int_xbar_clack_c.str().c_str(), |
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| 286 | params.mt_int, |
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| 287 | params.x_id, params.y_id, |
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| 288 | params.x_width, params.y_width, params.l_width, |
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| 289 | 1, |
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| 290 | params.nb_procs, |
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| 291 | 1, 1, |
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| 292 | true, |
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| 293 | false, |
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| 294 | false); |
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[450] | 295 | |
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[648] | 296 | ////////////// INT ROUTER(S) |
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| 297 | std::ostringstream s_int_router_cmd; |
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| 298 | s_int_router_cmd << "router_cmd_" << params.x_id << "_" << params.y_id; |
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| 299 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 300 | s_int_router_cmd.str().c_str(), |
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| 301 | params.x_id,params.y_id, |
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| 302 | params.x_width, params.y_width, |
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| 303 | 3, |
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| 304 | 4,4); |
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[450] | 305 | |
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[648] | 306 | std::ostringstream s_int_router_rsp; |
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| 307 | s_int_router_rsp << "router_rsp_" << params.x_id << "_" << params.y_id; |
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| 308 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 309 | s_int_router_rsp.str().c_str(), |
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| 310 | params.x_id,params.y_id, |
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| 311 | params.x_width, params.y_width, |
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| 312 | 2, |
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| 313 | 4,4); |
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[450] | 314 | |
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[648] | 315 | ////////////// XRAM |
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| 316 | std::ostringstream s_xram; |
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| 317 | s_xram << "xram_" << params.x_id << "_" << params.y_id; |
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| 318 | xram = new VciSimpleRam<vci_param_ext>( |
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| 319 | s_xram.str().c_str(), |
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| 320 | IntTab(cluster_id, params.ext_xram_tgtid), |
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| 321 | params.mt_ext, |
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| 322 | params.loader, |
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| 323 | params.xram_latency); |
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[450] | 324 | |
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[648] | 325 | std::ostringstream s_wt_xram; |
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| 326 | s_wt_xram << "xram_wt_" << params.x_id << "_" << params.y_id; |
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| 327 | xram_ram_wt = new VciExtDspinTargetWrapperType( |
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| 328 | s_wt_xram.str().c_str(), |
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| 329 | params.x_width + params.y_width + params.l_width); |
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[450] | 330 | |
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[648] | 331 | ///////////// RAM ROUTER(S) |
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| 332 | std::ostringstream s_ram_router_cmd; |
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| 333 | s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id; |
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| 334 | size_t is_iob0 = (params.x_id == 0) and (params.y_id == 0); |
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| 335 | size_t is_iob1 = (params.x_id == (params.x_size-1)) and |
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| 336 | (params.y_id == (params.y_size-1)); |
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| 337 | ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( |
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| 338 | s_ram_router_cmd.str().c_str(), |
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| 339 | params.x_id, params.y_id, |
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| 340 | params.x_width, |
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| 341 | params.y_width, |
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| 342 | 4, 4, |
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| 343 | is_iob0, |
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| 344 | is_iob1, |
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| 345 | false, |
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| 346 | params.l_width); |
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[450] | 347 | |
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[648] | 348 | std::ostringstream s_ram_router_rsp; |
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| 349 | s_ram_router_rsp << "ram_router_rsp_" << params.x_id << "_" << params.y_id; |
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| 350 | ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( |
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| 351 | s_ram_router_rsp.str().c_str(), |
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| 352 | params.x_id, params.y_id, |
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| 353 | params.x_width, |
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| 354 | params.y_width, |
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| 355 | 4, 4, |
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| 356 | is_iob0, |
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| 357 | is_iob1, |
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| 358 | true, |
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| 359 | params.l_width); |
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[450] | 360 | |
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[648] | 361 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 362 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
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| 363 | { |
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| 364 | /////////// IO_BRIDGE |
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| 365 | size_t iox_local_id; |
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| 366 | size_t global_id; |
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| 367 | bool has_irqs; |
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| 368 | if (cluster_id == cluster_iob0 ) |
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| 369 | { |
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| 370 | iox_local_id = 0; |
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| 371 | global_id = cluster_iob0; |
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| 372 | has_irqs = true; |
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| 373 | } |
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| 374 | else |
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| 375 | { |
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| 376 | iox_local_id = 1; |
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| 377 | global_id = cluster_iob1; |
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| 378 | has_irqs = false; |
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| 379 | } |
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[450] | 380 | |
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[648] | 381 | std::ostringstream s_iob; |
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| 382 | s_iob << "iob_" << params.x_id << "_" << params.y_id; |
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| 383 | iob = new VciIoBridge<vci_param_int, vci_param_ext>( |
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| 384 | s_iob.str().c_str(), |
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| 385 | params.mt_ext, |
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| 386 | params.mt_int, |
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| 387 | params.mt_iox, |
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| 388 | IntTab( global_id, params.int_iobx_tgtid), |
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| 389 | IntTab( global_id, params.int_iobx_srcid), |
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| 390 | IntTab( global_id, iox_local_id ), |
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| 391 | has_irqs, |
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| 392 | 16, |
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| 393 | 8, |
---|
| 394 | 8, |
---|
| 395 | params.debug_start_cycle, |
---|
| 396 | params.iob_debug_ok ); |
---|
[450] | 397 | |
---|
[648] | 398 | std::ostringstream s_iob_int_wi; |
---|
| 399 | s_iob_int_wi << "iob_int_wi_" << params.x_id << "_" << params.y_id; |
---|
| 400 | iob_int_wi = new VciIntDspinInitiatorWrapperType( |
---|
| 401 | s_iob_int_wi.str().c_str(), |
---|
| 402 | params.x_width + params.y_width + params.l_width); |
---|
[468] | 403 | |
---|
[648] | 404 | std::ostringstream s_iob_int_wt; |
---|
| 405 | s_iob_int_wt << "iob_int_wt_" << params.x_id << "_" << params.y_id; |
---|
| 406 | iob_int_wt = new VciIntDspinTargetWrapperType( |
---|
| 407 | s_iob_int_wt.str().c_str(), |
---|
| 408 | params.x_width + params.y_width + params.l_width); |
---|
[450] | 409 | |
---|
[648] | 410 | std::ostringstream s_iob_ram_wi; |
---|
| 411 | s_iob_ram_wi << "iob_ram_wi_" << params.x_id << "_" << params.y_id; |
---|
| 412 | iob_ram_wi = new VciExtDspinInitiatorWrapperType( |
---|
| 413 | s_iob_ram_wi.str().c_str(), |
---|
| 414 | params.x_width + params.y_width + params.l_width); |
---|
| 415 | } |
---|
| 416 | else |
---|
| 417 | { |
---|
| 418 | iob = NULL; |
---|
| 419 | iob_int_wi = NULL; |
---|
| 420 | iob_int_wt = NULL; |
---|
| 421 | iob_ram_wi = NULL; |
---|
| 422 | } |
---|
[450] | 423 | |
---|
[648] | 424 | //////////////////////////////////// |
---|
| 425 | // Connections are defined here |
---|
| 426 | //////////////////////////////////// |
---|
[450] | 427 | |
---|
[648] | 428 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
---|
| 429 | // : local srcid[memc] = nb_procs |
---|
| 430 | // In cluster_iob0, 32 HWI interrupts from external peripherals |
---|
| 431 | // are connected to the XICU ports p_hwi[0:31] |
---|
| 432 | // In other clusters, no HWI interrupts are connected to XICU |
---|
[450] | 433 | |
---|
[648] | 434 | //////////////////////// internal CMD & RSP routers |
---|
| 435 | int_router_cmd->p_clk (this->p_clk); |
---|
| 436 | int_router_cmd->p_resetn (this->p_resetn); |
---|
| 437 | int_router_rsp->p_clk (this->p_clk); |
---|
| 438 | int_router_rsp->p_resetn (this->p_resetn); |
---|
[450] | 439 | |
---|
[648] | 440 | for (int i = 0; i < 4; i++) |
---|
| 441 | { |
---|
| 442 | for(int k = 0; k < 3; k++) |
---|
| 443 | { |
---|
| 444 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
---|
| 445 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
---|
| 446 | } |
---|
[450] | 447 | |
---|
[648] | 448 | for(int k = 0; k < 2; k++) |
---|
| 449 | { |
---|
| 450 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
---|
| 451 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
---|
| 452 | } |
---|
| 453 | } |
---|
[550] | 454 | |
---|
[648] | 455 | // local ports |
---|
| 456 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
---|
| 457 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
---|
| 458 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
---|
| 459 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
---|
| 460 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
---|
| 461 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
---|
[450] | 462 | |
---|
[648] | 463 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
---|
| 464 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
---|
| 465 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
---|
| 466 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
---|
[450] | 467 | |
---|
[648] | 468 | ///////////////////// CMD DSPIN local crossbar direct |
---|
| 469 | int_xbar_cmd_d->p_clk (this->p_clk); |
---|
| 470 | int_xbar_cmd_d->p_resetn (this->p_resetn); |
---|
| 471 | int_xbar_cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d); |
---|
| 472 | int_xbar_cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d); |
---|
[450] | 473 | |
---|
[648] | 474 | int_xbar_cmd_d->p_local_out[params.int_memc_tgtid]( |
---|
| 475 | signal_int_dspin_cmd_memc_t); |
---|
| 476 | int_xbar_cmd_d->p_local_out[params.int_xicu_tgtid]( |
---|
| 477 | signal_int_dspin_cmd_xicu_t); |
---|
[658] | 478 | int_xbar_cmd_d->p_local_out[params.int_brom_tgtid]( |
---|
| 479 | signal_int_dspin_cmd_brom_t); |
---|
[648] | 480 | int_xbar_cmd_d->p_local_out[params.int_mdma_tgtid]( |
---|
| 481 | signal_int_dspin_cmd_mdma_t); |
---|
| 482 | int_xbar_cmd_d->p_local_in[params.int_mdma_srcid]( |
---|
| 483 | signal_int_dspin_cmd_mdma_i); |
---|
[450] | 484 | |
---|
[648] | 485 | for (size_t p = 0; p < params.nb_procs; p++) { |
---|
| 486 | int_xbar_cmd_d->p_local_in[params.int_proc_srcid + p]( |
---|
| 487 | signal_int_dspin_cmd_proc_i[p]); |
---|
| 488 | } |
---|
[450] | 489 | |
---|
[648] | 490 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
---|
| 491 | { |
---|
| 492 | int_xbar_cmd_d->p_local_out[params.int_iobx_tgtid]( |
---|
| 493 | signal_int_dspin_cmd_iobx_t); |
---|
| 494 | int_xbar_cmd_d->p_local_in[params.int_iobx_srcid]( |
---|
| 495 | signal_int_dspin_cmd_iobx_i); |
---|
| 496 | } |
---|
[468] | 497 | |
---|
[648] | 498 | //////////////////////// RSP DSPIN local crossbar direct |
---|
| 499 | int_xbar_rsp_d->p_clk (this->p_clk); |
---|
| 500 | int_xbar_rsp_d->p_resetn (this->p_resetn); |
---|
| 501 | int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); |
---|
| 502 | int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); |
---|
[468] | 503 | |
---|
[648] | 504 | int_xbar_rsp_d->p_local_in[params.int_memc_tgtid]( |
---|
| 505 | signal_int_dspin_rsp_memc_t); |
---|
| 506 | int_xbar_rsp_d->p_local_in[params.int_xicu_tgtid]( |
---|
| 507 | signal_int_dspin_rsp_xicu_t); |
---|
[658] | 508 | int_xbar_rsp_d->p_local_in[params.int_brom_tgtid]( |
---|
| 509 | signal_int_dspin_rsp_brom_t); |
---|
[648] | 510 | int_xbar_rsp_d->p_local_in[params.int_mdma_tgtid]( |
---|
| 511 | signal_int_dspin_rsp_mdma_t); |
---|
[450] | 512 | |
---|
[648] | 513 | int_xbar_rsp_d->p_local_out[params.int_mdma_srcid]( |
---|
| 514 | signal_int_dspin_rsp_mdma_i); |
---|
| 515 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 516 | int_xbar_rsp_d->p_local_out[params.int_proc_srcid + p]( |
---|
| 517 | signal_int_dspin_rsp_proc_i[p]); |
---|
[450] | 518 | |
---|
[648] | 519 | if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1)) |
---|
| 520 | { |
---|
| 521 | int_xbar_rsp_d->p_local_in[params.int_iobx_tgtid]( |
---|
| 522 | signal_int_dspin_rsp_iobx_t); |
---|
| 523 | int_xbar_rsp_d->p_local_out[params.int_iobx_srcid]( |
---|
| 524 | signal_int_dspin_rsp_iobx_i); |
---|
| 525 | } |
---|
[450] | 526 | |
---|
[648] | 527 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
| 528 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
| 529 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
| 530 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
| 531 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
| 532 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
| 533 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 534 | { |
---|
| 535 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
| 536 | } |
---|
[450] | 537 | |
---|
[648] | 538 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
| 539 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
| 540 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
| 541 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
| 542 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
| 543 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
| 544 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 545 | { |
---|
| 546 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
| 547 | } |
---|
| 548 | |
---|
| 549 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
| 550 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 551 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
| 552 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
---|
| 553 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
---|
| 554 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
---|
| 555 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 556 | { |
---|
| 557 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
---|
| 558 | } |
---|
[450] | 559 | |
---|
[648] | 560 | //////////////////////////////////// Processors |
---|
| 561 | for (size_t p = 0; p < params.nb_procs; p++) |
---|
| 562 | { |
---|
| 563 | proc[p]->p_clk (this->p_clk); |
---|
| 564 | proc[p]->p_resetn (this->p_resetn); |
---|
| 565 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 566 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
| 567 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
| 568 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
---|
| 569 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
| 570 | for ( size_t j = 1 ; j < 6 ; j++) |
---|
| 571 | { |
---|
| 572 | proc[p]->p_irq[j] (signal_false); |
---|
| 573 | } |
---|
[450] | 574 | |
---|
[648] | 575 | proc_wi[p]->p_clk (this->p_clk); |
---|
| 576 | proc_wi[p]->p_resetn (this->p_resetn); |
---|
| 577 | proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]); |
---|
| 578 | proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]); |
---|
| 579 | proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 580 | } |
---|
[450] | 581 | |
---|
[648] | 582 | ///////////////////////////////////// XICU |
---|
| 583 | xicu->p_clk (this->p_clk); |
---|
| 584 | xicu->p_resetn (this->p_resetn); |
---|
| 585 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
| 586 | for ( size_t p = 0 ; p < params.nb_procs ; p++) |
---|
| 587 | { |
---|
| 588 | xicu->p_irq[p] (signal_proc_it[p]); |
---|
| 589 | } |
---|
| 590 | for ( size_t i=0 ; i<32 ; i++) |
---|
| 591 | { |
---|
| 592 | if (cluster_id == cluster_iob0) |
---|
| 593 | xicu->p_hwi[i] (*(this->p_irq[i])); |
---|
| 594 | else |
---|
| 595 | xicu->p_hwi[i] (signal_false); |
---|
| 596 | } |
---|
[450] | 597 | |
---|
[648] | 598 | // wrapper XICU |
---|
| 599 | xicu_int_wt->p_clk (this->p_clk); |
---|
| 600 | xicu_int_wt->p_resetn (this->p_resetn); |
---|
| 601 | xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t); |
---|
| 602 | xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t); |
---|
| 603 | xicu_int_wt->p_vci (signal_int_vci_tgt_xicu); |
---|
[450] | 604 | |
---|
[648] | 605 | ///////////////////////////////////// MEMC |
---|
| 606 | memc->p_clk (this->p_clk); |
---|
| 607 | memc->p_resetn (this->p_resetn); |
---|
| 608 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
| 609 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 610 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
| 611 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
| 612 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
---|
| 613 | memc->p_irq (signal_irq_memc); |
---|
[450] | 614 | |
---|
[648] | 615 | // wrapper to INT network |
---|
| 616 | memc_int_wt->p_clk (this->p_clk); |
---|
| 617 | memc_int_wt->p_resetn (this->p_resetn); |
---|
| 618 | memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t); |
---|
| 619 | memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t); |
---|
| 620 | memc_int_wt->p_vci (signal_int_vci_tgt_memc); |
---|
[450] | 621 | |
---|
[648] | 622 | // wrapper to RAM network |
---|
| 623 | memc_ram_wi->p_clk (this->p_clk); |
---|
| 624 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
| 625 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
| 626 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
| 627 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
[450] | 628 | |
---|
[658] | 629 | //////////////////////////////////// BROM |
---|
| 630 | brom->p_clk (this->p_clk); |
---|
| 631 | brom->p_resetn (this->p_resetn); |
---|
| 632 | brom->p_vci (signal_int_vci_tgt_brom); |
---|
| 633 | |
---|
| 634 | //wrapper to INT network |
---|
| 635 | brom_int_wt->p_clk (this->p_clk); |
---|
| 636 | brom_int_wt->p_resetn (this->p_resetn); |
---|
| 637 | brom_int_wt->p_dspin_cmd (signal_int_dspin_cmd_brom_t); |
---|
| 638 | brom_int_wt->p_dspin_rsp (signal_int_dspin_rsp_brom_t); |
---|
| 639 | brom_int_wt->p_vci (signal_int_vci_tgt_brom); |
---|
| 640 | |
---|
[648] | 641 | //////////////////////////////////// XRAM |
---|
| 642 | xram->p_clk (this->p_clk); |
---|
| 643 | xram->p_resetn (this->p_resetn); |
---|
| 644 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 645 | |
---|
[648] | 646 | // wrapper to RAM network |
---|
| 647 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 648 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 649 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
| 650 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 651 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 652 | |
---|
[648] | 653 | /////////////////////////////////// MDMA |
---|
| 654 | mdma->p_clk (this->p_clk); |
---|
| 655 | mdma->p_resetn (this->p_resetn); |
---|
| 656 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 657 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
| 658 | for (size_t i = 0 ; i < params.nb_dmas ; i++) |
---|
| 659 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
[468] | 660 | |
---|
[648] | 661 | // target wrapper |
---|
| 662 | mdma_int_wt->p_clk (this->p_clk); |
---|
| 663 | mdma_int_wt->p_resetn (this->p_resetn); |
---|
| 664 | mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t); |
---|
| 665 | mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t); |
---|
| 666 | mdma_int_wt->p_vci (signal_int_vci_tgt_mdma); |
---|
[450] | 667 | |
---|
[648] | 668 | // initiator wrapper |
---|
| 669 | mdma_int_wi->p_clk (this->p_clk); |
---|
| 670 | mdma_int_wi->p_resetn (this->p_resetn); |
---|
| 671 | mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i); |
---|
| 672 | mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i); |
---|
| 673 | mdma_int_wi->p_vci (signal_int_vci_ini_mdma); |
---|
[450] | 674 | |
---|
[648] | 675 | //////////////////////////// RAM network CMD & RSP routers |
---|
| 676 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 677 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 678 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 679 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
| 680 | for( size_t n=0 ; n<4 ; n++) |
---|
| 681 | { |
---|
| 682 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 683 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 684 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 685 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
| 686 | } |
---|
| 687 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 688 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 689 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 690 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
[450] | 691 | |
---|
[648] | 692 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
---|
| 693 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
---|
| 694 | { |
---|
| 695 | // IO bridge |
---|
| 696 | iob->p_clk (this->p_clk); |
---|
| 697 | iob->p_resetn (this->p_resetn); |
---|
| 698 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
---|
| 699 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
---|
| 700 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 701 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
| 702 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
---|
[450] | 703 | |
---|
[648] | 704 | if ( cluster_id == cluster_iob0 ) |
---|
| 705 | for ( size_t n = 0 ; n < 32 ; n++ ) |
---|
| 706 | (*iob->p_irq[n]) (*(this->p_irq[n])); |
---|
[450] | 707 | |
---|
[648] | 708 | // initiator wrapper to RAM network |
---|
| 709 | iob_ram_wi->p_clk (this->p_clk); |
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| 710 | iob_ram_wi->p_resetn (this->p_resetn); |
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| 711 | iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); |
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| 712 | iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); |
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| 713 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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[450] | 714 | |
---|
[648] | 715 | // initiator wrapper to INT network |
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| 716 | iob_int_wi->p_clk (this->p_clk); |
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| 717 | iob_int_wi->p_resetn (this->p_resetn); |
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| 718 | iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i); |
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| 719 | iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i); |
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| 720 | iob_int_wi->p_vci (signal_int_vci_ini_iobx); |
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[450] | 721 | |
---|
[648] | 722 | // target wrapper to INT network |
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| 723 | iob_int_wt->p_clk (this->p_clk); |
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| 724 | iob_int_wt->p_resetn (this->p_resetn); |
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| 725 | iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t); |
---|
| 726 | iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t); |
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| 727 | iob_int_wt->p_vci (signal_int_vci_tgt_iobx); |
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| 728 | } |
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| 729 | } // end constructor |
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[450] | 730 | |
---|
[648] | 731 | tmpl(/**/)::~TsarIobCluster() |
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| 732 | { |
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| 733 | if (p_vci_iob_iox_ini) delete p_vci_iob_iox_ini; |
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| 734 | if (p_vci_iob_iox_tgt) delete p_vci_iob_iox_tgt; |
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| 735 | if (p_dspin_iob_cmd_out) delete p_dspin_iob_cmd_out; |
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| 736 | if (p_dspin_iob_rsp_in) delete p_dspin_iob_rsp_in; |
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| 737 | if (iob) delete iob; |
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| 738 | if (iob_int_wi) delete iob_int_wi; |
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| 739 | if (iob_int_wt) delete iob_int_wt; |
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| 740 | if (iob_ram_wi) delete iob_ram_wi; |
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[450] | 741 | |
---|
[648] | 742 | for (size_t n = 0 ; n < 32 ; n++) |
---|
| 743 | { |
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| 744 | if (p_irq[n]) delete p_irq[n]; |
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| 745 | } |
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[450] | 746 | |
---|
[648] | 747 | for (size_t p = 0; p < m_procs; p++) |
---|
| 748 | { |
---|
| 749 | delete proc[p]; |
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| 750 | delete proc_wi[p]; |
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| 751 | } |
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[450] | 752 | |
---|
[648] | 753 | delete memc; |
---|
| 754 | delete memc_int_wt; |
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| 755 | delete memc_ram_wi; |
---|
| 756 | delete xicu; |
---|
| 757 | delete xicu_int_wt; |
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[658] | 758 | delete brom; |
---|
| 759 | delete brom_int_wt; |
---|
[648] | 760 | delete mdma; |
---|
| 761 | delete mdma_int_wt; |
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| 762 | delete mdma_int_wi; |
---|
| 763 | delete int_xbar_cmd_d; |
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| 764 | delete int_xbar_rsp_d; |
---|
| 765 | delete int_xbar_m2p_c; |
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| 766 | delete int_xbar_p2m_c; |
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| 767 | delete int_xbar_clack_c; |
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| 768 | delete int_router_cmd; |
---|
| 769 | delete int_router_rsp; |
---|
| 770 | delete xram; |
---|
| 771 | delete xram_ram_wt; |
---|
| 772 | delete ram_router_cmd; |
---|
| 773 | delete ram_router_rsp; |
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| 774 | } |
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[450] | 775 | |
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| 776 | }} |
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| 777 | |
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| 778 | |
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| 779 | // Local Variables: |
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| 780 | // tab-width: 3 |
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| 781 | // c-basic-offset: 3 |
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| 782 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 783 | // indent-tabs-mode: nil |
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| 784 | // End: |
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| 785 | |
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| 786 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 787 | |
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