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source: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 1041

Last change on this file since 1041 was 1041, checked in by meunier, 8 years ago
Fixing bug found by CD in the L1 cache: the flushing of the cache didn't flush the last line of the last way
File size: 243.0 KB

Rev	Line
[331]	1	/* -- c++ --
	2	* File : vci_cc_vcache_wrapper.cpp
	3	* Copyright (c) UPMC, Lip6, SoC
	4	* Authors : Alain GREINER, Yang GAO
	5	*
	6	* SOCLIB_LGPL_HEADER_BEGIN
	7	*
	8	* This file is part of SoCLib, GNU LGPLv2.1.
	9	*
	10	* SoCLib is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU Lesser General Public License as published
	12	* by the Free Software Foundation; version 2.1 of the License.
	13	*
	14	* SoCLib is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	17	* Lesser General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU Lesser General Public
	20	* License along with SoCLib; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	22	* 02110-1301 USA
	23	*
	24	* SOCLIB_LGPL_HEADER_END
	25	*
	26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
	27	* alexandre.joannou@lip6.fr
	28	*/
	29
	30	#include <cassert>
[752]	31	#include <signal.h>
	32
[331]	33	#include "arithmetics.h"
[351]	34	#include "../include/vci_cc_vcache_wrapper.h"
[331]	35
[789]	36	#define DEBUG_DCACHE 1
	37	#define DEBUG_ICACHE 1
	38	#define DEBUG_CMD 0
[331]	39
	40	namespace soclib {
	41	namespace caba {
	42
	43	namespace {
[789]	44	const char * icache_fsm_state_str[] = {
[331]	45	"ICACHE_IDLE",
	46
	47	"ICACHE_XTN_TLB_FLUSH",
	48	"ICACHE_XTN_CACHE_FLUSH",
	49	"ICACHE_XTN_CACHE_FLUSH_GO",
	50	"ICACHE_XTN_TLB_INVAL",
	51	"ICACHE_XTN_CACHE_INVAL_VA",
	52	"ICACHE_XTN_CACHE_INVAL_PA",
	53	"ICACHE_XTN_CACHE_INVAL_GO",
	54
	55	"ICACHE_TLB_WAIT",
	56
	57	"ICACHE_MISS_SELECT",
	58	"ICACHE_MISS_CLEAN",
	59	"ICACHE_MISS_WAIT",
	60	"ICACHE_MISS_DATA_UPDT",
	61	"ICACHE_MISS_DIR_UPDT",
	62
	63	"ICACHE_UNC_WAIT",
	64
	65	"ICACHE_CC_CHECK",
[468]	66	"ICACHE_CC_UPDT",
[331]	67	"ICACHE_CC_INVAL",
	68	};
	69
[789]	70	const char * dcache_fsm_state_str[] = {
[331]	71	"DCACHE_IDLE",
	72
	73	"DCACHE_TLB_MISS",
	74	"DCACHE_TLB_PTE1_GET",
	75	"DCACHE_TLB_PTE1_SELECT",
	76	"DCACHE_TLB_PTE1_UPDT",
	77	"DCACHE_TLB_PTE2_GET",
	78	"DCACHE_TLB_PTE2_SELECT",
	79	"DCACHE_TLB_PTE2_UPDT",
	80	"DCACHE_TLB_LR_UPDT",
	81	"DCACHE_TLB_LR_WAIT",
	82	"DCACHE_TLB_RETURN",
	83
	84	"DCACHE_XTN_SWITCH",
	85	"DCACHE_XTN_SYNC",
	86	"DCACHE_XTN_IC_INVAL_VA",
	87	"DCACHE_XTN_IC_FLUSH",
	88	"DCACHE_XTN_IC_INVAL_PA",
[721]	89	"DCACHE_XTN_IC_PADDR_EXT",
[331]	90	"DCACHE_XTN_IT_INVAL",
	91	"DCACHE_XTN_DC_FLUSH",
	92	"DCACHE_XTN_DC_FLUSH_GO",
	93	"DCACHE_XTN_DC_INVAL_VA",
	94	"DCACHE_XTN_DC_INVAL_PA",
	95	"DCACHE_XTN_DC_INVAL_END",
	96	"DCACHE_XTN_DC_INVAL_GO",
	97	"DCACHE_XTN_DT_INVAL",
	98
[384]	99	"DCACHE_DIRTY_GET_PTE",
[331]	100	"DCACHE_DIRTY_WAIT",
	101
	102	"DCACHE_MISS_SELECT",
	103	"DCACHE_MISS_CLEAN",
	104	"DCACHE_MISS_WAIT",
	105	"DCACHE_MISS_DATA_UPDT",
	106	"DCACHE_MISS_DIR_UPDT",
	107
	108	"DCACHE_UNC_WAIT",
	109	"DCACHE_LL_WAIT",
	110	"DCACHE_SC_WAIT",
	111
	112	"DCACHE_CC_CHECK",
[468]	113	"DCACHE_CC_UPDT",
[331]	114	"DCACHE_CC_INVAL",
	115
	116	"DCACHE_INVAL_TLB_SCAN",
	117	};
	118
[789]	119	const char * cmd_fsm_state_str[] = {
[331]	120	"CMD_IDLE",
	121	"CMD_INS_MISS",
	122	"CMD_INS_UNC",
	123	"CMD_DATA_MISS",
[616]	124	"CMD_DATA_UNC_READ",
	125	"CMD_DATA_UNC_WRITE",
[331]	126	"CMD_DATA_WRITE",
	127	"CMD_DATA_LL",
	128	"CMD_DATA_SC",
	129	"CMD_DATA_CAS",
	130	};
	131
[789]	132	const char * vci_pktid_type_str[] = {
[616]	133	"TYPE_DATA_UNC",
[816]	134	"TYPE_READ_DATA_MISS",
	135	"TYPE_READ_INS_UNC",
[423]	136	"TYPE_READ_INS_MISS",
	137	"TYPE_WRITE",
	138	"TYPE_CAS",
	139	"TYPE_LL",
	140	"TYPE_SC",
	141	};
	142
[789]	143	const char * vci_cmd_type_str[] = {
[423]	144	"NOP or STORE_COND",
	145	"READ",
	146	"WRITE",
	147	"LOCKED_READ"
	148	};
	149
[789]	150	const char * rsp_fsm_state_str[] = {
[331]	151	"RSP_IDLE",
	152	"RSP_INS_MISS",
	153	"RSP_INS_UNC",
	154	"RSP_DATA_MISS",
	155	"RSP_DATA_UNC",
	156	"RSP_DATA_LL",
	157	"RSP_DATA_WRITE",
	158	};
	159
[789]	160	const char * cc_receive_fsm_state_str[] = {
[331]	161	"CC_RECEIVE_IDLE",
	162	"CC_RECEIVE_BRDCAST_HEADER",
	163	"CC_RECEIVE_BRDCAST_NLINE",
[468]	164	"CC_RECEIVE_INS_INVAL_HEADER",
	165	"CC_RECEIVE_INS_INVAL_NLINE",
	166	"CC_RECEIVE_INS_UPDT_HEADER",
	167	"CC_RECEIVE_INS_UPDT_NLINE",
	168	"CC_RECEIVE_INS_UPDT_DATA",
	169	"CC_RECEIVE_DATA_INVAL_HEADER",
	170	"CC_RECEIVE_DATA_INVAL_NLINE",
	171	"CC_RECEIVE_DATA_UPDT_HEADER",
	172	"CC_RECEIVE_DATA_UPDT_NLINE",
	173	"CC_RECEIVE_DATA_UPDT_DATA",
[331]	174	};
	175
[789]	176	const char * cc_send_fsm_state_str[] = {
[331]	177	"CC_SEND_IDLE",
	178	"CC_SEND_CLEANUP_1",
	179	"CC_SEND_CLEANUP_2",
	180	"CC_SEND_MULTI_ACK",
	181	};
	182	}
	183
[386]	184	#define tmpl(...) \
	185	template<typename vci_param, \
	186	size_t dspin_in_width, \
	187	size_t dspin_out_width, \
	188	typename iss_t> __VA_ARGS__ \
	189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
[331]	190
[346]	191	using namespace soclib::common;
[331]	192
	193	/////////////////////////////////
	194	tmpl(/**/)::VciCcVCacheWrapper(
[789]	195	sc_module_name name,
	196	const int proc_id,
	197	const MappingTable &mtd,
	198	const IntTab &srcid,
	199	const size_t cc_global_id,
	200	const size_t itlb_ways,
	201	const size_t itlb_sets,
	202	const size_t dtlb_ways,
	203	const size_t dtlb_sets,
	204	const size_t icache_ways,
	205	const size_t icache_sets,
	206	const size_t icache_words,
	207	const size_t dcache_ways,
	208	const size_t dcache_sets,
	209	const size_t dcache_words,
	210	const size_t wbuf_nlines,
	211	const size_t wbuf_nwords,
	212	const size_t x_width,
	213	const size_t y_width,
	214	const uint32_t max_frozen_cycles,
	215	const uint32_t debug_start_cycle,
	216	const bool debug_ok)
[331]	217	: soclib::caba::BaseModule(name),
	218
[346]	219	p_clk("p_clk"),
	220	p_resetn("p_resetn"),
	221	p_vci("p_vci"),
[468]	222	p_dspin_m2p("p_dspin_m2p"),
	223	p_dspin_p2m("p_dspin_p2m"),
	224	p_dspin_clack("p_dspin_clack"),
[331]	225
[789]	226	m_cacheability_table( mtd.getCacheabilityTable()),
	227	m_srcid(mtd.indexForId(srcid)),
	228	m_cc_global_id(cc_global_id),
	229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
	230	m_itlb_ways(itlb_ways),
	231	m_itlb_sets(itlb_sets),
	232	m_dtlb_ways(dtlb_ways),
	233	m_dtlb_sets(dtlb_sets),
	234	m_icache_ways(icache_ways),
	235	m_icache_sets(icache_sets),
	236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
	237	m_icache_words(icache_words),
	238	m_dcache_ways(dcache_ways),
	239	m_dcache_sets(dcache_sets),
	240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
	241	m_dcache_words(dcache_words),
	242	m_x_width(x_width),
	243	m_y_width(y_width),
	244	m_proc_id(proc_id),
	245	m_max_frozen_cycles(max_frozen_cycles),
	246	m_paddr_nbits(vci_param::N),
	247	m_debug_start_cycle(debug_start_cycle),
	248	m_debug_ok(debug_ok),
[721]	249	m_dcache_paddr_ext_reset(0),
	250	m_icache_paddr_ext_reset(0),
[331]	251
	252	r_mmu_ptpr("r_mmu_ptpr"),
	253	r_mmu_mode("r_mmu_mode"),
	254	r_mmu_word_lo("r_mmu_word_lo"),
	255	r_mmu_word_hi("r_mmu_word_hi"),
	256	r_mmu_ibvar("r_mmu_ibvar"),
	257	r_mmu_dbvar("r_mmu_dbvar"),
	258	r_mmu_ietr("r_mmu_ietr"),
	259	r_mmu_detr("r_mmu_detr"),
	260
	261	r_icache_fsm("r_icache_fsm"),
	262	r_icache_fsm_save("r_icache_fsm_save"),
	263	r_icache_vci_paddr("r_icache_vci_paddr"),
	264	r_icache_vaddr_save("r_icache_vaddr_save"),
	265
	266	r_icache_miss_way("r_icache_miss_way"),
	267	r_icache_miss_set("r_icache_miss_set"),
	268	r_icache_miss_word("r_icache_miss_word"),
	269	r_icache_miss_inval("r_icache_miss_inval"),
	270	r_icache_miss_clack("r_icache_miss_clack"),
	271
	272	r_icache_cc_way("r_icache_cc_way"),
	273	r_icache_cc_set("r_icache_cc_set"),
	274	r_icache_cc_word("r_icache_cc_word"),
	275	r_icache_cc_need_write("r_icache_cc_need_write"),
	276
	277	r_icache_flush_count("r_icache_flush_count"),
	278
	279	r_icache_miss_req("r_icache_miss_req"),
	280	r_icache_unc_req("r_icache_unc_req"),
	281
	282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
	283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
	284
[487]	285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
	286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
	287
[331]	288	r_icache_cc_send_req("r_icache_cc_send_req"),
	289	r_icache_cc_send_type("r_icache_cc_send_type"),
	290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
	291	r_icache_cc_send_way("r_icache_cc_send_way"),
	292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
	293
	294	r_dcache_fsm("r_dcache_fsm"),
	295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
	296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
	297
	298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
	299	r_dcache_updt_req("r_dcache_updt_req"),
	300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
	301	r_dcache_save_wdata("r_dcache_save_wdata"),
	302	r_dcache_save_be("r_dcache_save_be"),
	303	r_dcache_save_paddr("r_dcache_save_paddr"),
	304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
	305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
	306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
	307
	308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
	309	r_dcache_dirty_way("r_dcache_dirty_way"),
	310	r_dcache_dirty_set("r_dcache_dirty_set"),
	311
	312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
[616]	313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
[331]	314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
	315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
[627]	316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
[616]	317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
[331]	318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
	319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
	320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
	321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
	322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
	323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
	324
	325	r_dcache_xtn_way("r_dcache_xtn_way"),
	326	r_dcache_xtn_set("r_dcache_xtn_set"),
	327
	328	r_dcache_miss_type("r_dcache_miss_type"),
	329	r_dcache_miss_word("r_dcache_miss_word"),
	330	r_dcache_miss_way("r_dcache_miss_way"),
	331	r_dcache_miss_set("r_dcache_miss_set"),
	332	r_dcache_miss_inval("r_dcache_miss_inval"),
	333
	334	r_dcache_cc_way("r_dcache_cc_way"),
	335	r_dcache_cc_set("r_dcache_cc_set"),
	336	r_dcache_cc_word("r_dcache_cc_word"),
	337	r_dcache_cc_need_write("r_dcache_cc_need_write"),
	338
	339	r_dcache_flush_count("r_dcache_flush_count"),
	340
	341	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
	342
	343	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
	344	r_dcache_tlb_ins("r_dcache_tlb_ins"),
	345	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
	346	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
	347	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
	348	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
	349	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
	350	r_dcache_tlb_way("r_dcache_tlb_way"),
	351	r_dcache_tlb_set("r_dcache_tlb_set"),
	352
	353	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
	354	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
	355
	356	r_dcache_xtn_req("r_dcache_xtn_req"),
	357	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
	358
[487]	359	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
	360	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
[816]	361
[331]	362	r_dcache_cc_send_req("r_dcache_cc_send_req"),
	363	r_dcache_cc_send_type("r_dcache_cc_send_type"),
	364	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
	365	r_dcache_cc_send_way("r_dcache_cc_send_way"),
	366	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
	367
	368	r_vci_cmd_fsm("r_vci_cmd_fsm"),
	369	r_vci_cmd_min("r_vci_cmd_min"),
	370	r_vci_cmd_max("r_vci_cmd_max"),
	371	r_vci_cmd_cpt("r_vci_cmd_cpt"),
	372	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
	373
	374	r_vci_rsp_fsm("r_vci_rsp_fsm"),
	375	r_vci_rsp_cpt("r_vci_rsp_cpt"),
	376	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
	377	r_vci_rsp_data_error("r_vci_rsp_data_error"),
[789]	378	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
	379	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
[331]	380
	381	r_cc_send_fsm("r_cc_send_fsm"),
	382	r_cc_send_last_client("r_cc_send_last_client"),
	383
	384	r_cc_receive_fsm("r_cc_receive_fsm"),
	385	r_cc_receive_data_ins("r_cc_receive_data_ins"),
	386	r_cc_receive_word_idx("r_cc_receive_word_idx"),
[789]	387	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
	388	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
	389	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
[331]	390
	391	r_cc_receive_icache_req("r_cc_receive_icache_req"),
	392	r_cc_receive_icache_type("r_cc_receive_icache_type"),
	393	r_cc_receive_icache_way("r_cc_receive_icache_way"),
	394	r_cc_receive_icache_set("r_cc_receive_icache_set"),
	395	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
	396	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
	397
	398	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
	399	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
	400	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
	401	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
	402	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
	403	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
	404
	405	r_iss(this->name(), proc_id),
	406	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
	407	r_icache("icache", icache_ways, icache_sets, icache_words),
	408	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
	409	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
	410	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
	411	{
[421]	412	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
	413
[789]	414	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
[331]	415	"Need more PLEN bits.");
	416
[789]	417	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
[331]	418	"Need more TRDID bits.");
	419
[789]	420	assert((icache_words == dcache_words) and
[331]	421	"icache_words and dcache_words parameters must be equal");
	422
[789]	423	assert((itlb_sets == dtlb_sets) and
[331]	424	"itlb_sets and dtlb_sets parameters must be etqual");
	425
[789]	426	assert((itlb_ways == dtlb_ways) and
[331]	427	"itlb_ways and dtlb_ways parameters must be etqual");
	428
[789]	429	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
	430	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
	431	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
	432	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
	433	(uint32_log2(m_icache_words << 2));
[331]	434
[789]	435	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
[331]	436
[789]	437	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
	438	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
[331]	439
	440	SC_METHOD(transition);
	441	dont_initialize();
	442	sensitive << p_clk.pos();
	443
	444	SC_METHOD(genMoore);
	445	dont_initialize();
	446	sensitive << p_clk.neg();
	447
	448	typename iss_t::CacheInfo cache_info;
	449	cache_info.has_mmu = true;
[789]	450	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
[331]	451	cache_info.icache_assoc = icache_ways;
	452	cache_info.icache_n_lines = icache_sets;
[789]	453	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
[331]	454	cache_info.dcache_assoc = dcache_ways;
	455	cache_info.dcache_n_lines = dcache_sets;
	456	r_iss.setCacheInfo(cache_info);
	457	}
	458
	459	/////////////////////////////////////
	460	tmpl(/**/)::~VciCcVCacheWrapper()
	461	/////////////////////////////////////
	462	{
	463	delete [] r_dcache_in_tlb;
	464	delete [] r_dcache_contains_ptd;
	465	}
	466
	467	////////////////////////
	468	tmpl(void)::print_cpi()
	469	////////////////////////
	470	{
	471	std::cout << name() << " CPI = "
	472	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
	473	}
	474
	475	////////////////////////////////////
	476	tmpl(void)::print_trace(size_t mode)
	477	////////////////////////////////////
	478	{
	479	// b0 : write buffer trace
[740]	480	// b1 : dump processor registers
[331]	481	// b2 : dcache trace
	482	// b3 : icache trace
	483	// b4 : dtlb trace
	484	// b5 : itlb trace
[740]	485	// b6 : SR (ISS register 32)
[331]	486
	487	std::cout << std::dec << "PROC " << name() << std::endl;
	488
	489	std::cout << " " << m_ireq << std::endl;
	490	std::cout << " " << m_irsp << std::endl;
	491	std::cout << " " << m_dreq << std::endl;
	492	std::cout << " " << m_drsp << std::endl;
	493
	494	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
	495	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
	496	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
	497	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
	498	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
[394]	499	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
	500	<< " \| MMU = " << r_mmu_mode.read();
[711]	501
[789]	502	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
	503	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
[331]	504	std::cout << std::endl;
	505
[789]	506	if (mode & 0x01)
[331]	507	{
[789]	508	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
	509	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
	510	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
	511	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
[711]	512
[789]	513	r_wbuf.printTrace((mode >> 1) & 1);
[331]	514	}
[789]	515	if (mode & 0x02)
[740]	516	{
	517	r_iss.dump();
	518	}
[789]	519	if (mode & 0x04)
[331]	520	{
	521	std::cout << " Data Cache" << std::endl;
	522	r_dcache.printTrace();
	523	}
[789]	524	if (mode & 0x08)
[331]	525	{
	526	std::cout << " Instruction Cache" << std::endl;
	527	r_icache.printTrace();
	528	}
[789]	529	if (mode & 0x10)
[331]	530	{
	531	std::cout << " Data TLB" << std::endl;
	532	r_dtlb.printTrace();
	533	}
[789]	534	if (mode & 0x20)
[331]	535	{
	536	std::cout << " Instruction TLB" << std::endl;
	537	r_itlb.printTrace();
	538	}
[789]	539	if (mode & 0x40)
[740]	540	{
[789]	541	uint32_t status = r_iss.debugGetRegisterValue(32);
[740]	542	std::cout << name();
[789]	543	if (status != m_previous_status ) std::cout << " NEW ";
[740]	544	std::cout << " status = " << std::hex << status << " " << std::endl;
	545	m_previous_status = status;
	546	}
[331]	547	}
	548
	549	//////////////////////////////////////////
[789]	550	tmpl(void)::cache_monitor(paddr_t addr)
[331]	551	//////////////////////////////////////////
	552	{
[789]	553	bool cache_hit;
	554	size_t cache_way = 0;
	555	size_t cache_set = 0;
	556	size_t cache_word = 0;
	557	uint32_t cache_rdata = 0;
[394]	558
[789]	559	cache_hit = r_dcache.read_neutral(addr,
	560	&cache_rdata,
	561	&cache_way,
	562	&cache_set,
	563	&cache_word);
[394]	564
[789]	565	if (cache_hit != m_debug_previous_d_hit)
[331]	566	{
[394]	567	std::cout << "Monitor PROC " << name()
	568	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
[816]	569	<< " / HIT = " << cache_hit
[394]	570	<< " / PADDR = " << std::hex << addr
[816]	571	<< " / DATA = " << cache_rdata
[394]	572	<< " / WAY = " << cache_way << std::endl;
[789]	573	m_debug_previous_d_hit = cache_hit;
[331]	574	}
[394]	575
[789]	576	cache_hit = r_icache.read_neutral(addr,
	577	&cache_rdata,
	578	&cache_way,
	579	&cache_set,
	580	&cache_word);
[394]	581
[789]	582	if (cache_hit != m_debug_previous_i_hit)
[331]	583	{
[394]	584	std::cout << "Monitor PROC " << name()
	585	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
[816]	586	<< " / HIT = " << cache_hit
[394]	587	<< " / PADDR = " << std::hex << addr
[816]	588	<< " / DATA = " << cache_rdata
[394]	589	<< " / WAY = " << cache_way << std::endl;
[789]	590	m_debug_previous_i_hit = cache_hit;
[331]	591	}
	592	}
	593
	594	/*
	595	////////////////////////
	596	tmpl(void)::print_stats()
	597	////////////////////////
	598	{
	599	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
	600	std::cout << name() << std::endl
	601	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
	602	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
	603	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
	604	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
	605	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
	606	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
	607	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
	608	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
	609	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
	610	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
	611	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
	612	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
	613	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
	614	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
	615	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
	616	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
	617	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
	618	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
	619	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
	620	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
	621	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
	622	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
	623	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
	624	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
	625	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
	626	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
	627	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
	628	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
	629	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
	630	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
	631	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
	632	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
	633	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
	634	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
	635	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
	636	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
	637	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
	638	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
	639	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
	640	}
	641
	642	////////////////////////
	643	tmpl(void)::clear_stats()
	644	////////////////////////
	645	{
	646	m_cpt_dcache_data_read = 0;
	647	m_cpt_dcache_data_write = 0;
	648	m_cpt_dcache_dir_read = 0;
	649	m_cpt_dcache_dir_write = 0;
	650	m_cpt_icache_data_read = 0;
	651	m_cpt_icache_data_write = 0;
	652	m_cpt_icache_dir_read = 0;
	653	m_cpt_icache_dir_write = 0;
	654
	655	m_cpt_frz_cycles = 0;
	656	m_cpt_dcache_frz_cycles = 0;
	657	m_cpt_total_cycles = 0;
	658
	659	m_cpt_read = 0;
	660	m_cpt_write = 0;
	661	m_cpt_data_miss = 0;
	662	m_cpt_ins_miss = 0;
	663	m_cpt_unc_read = 0;
	664	m_cpt_write_cached = 0;
	665	m_cpt_ins_read = 0;
	666
	667	m_cost_write_frz = 0;
	668	m_cost_data_miss_frz = 0;
	669	m_cost_unc_read_frz = 0;
	670	m_cost_ins_miss_frz = 0;
	671
	672	m_cpt_imiss_transaction = 0;
	673	m_cpt_dmiss_transaction = 0;
	674	m_cpt_unc_transaction = 0;
	675	m_cpt_write_transaction = 0;
	676	m_cpt_icache_unc_transaction = 0;
	677
	678	m_cost_imiss_transaction = 0;
	679	m_cost_dmiss_transaction = 0;
	680	m_cost_unc_transaction = 0;
	681	m_cost_write_transaction = 0;
	682	m_cost_icache_unc_transaction = 0;
	683	m_length_write_transaction = 0;
	684
	685	m_cpt_ins_tlb_read = 0;
	686	m_cpt_ins_tlb_miss = 0;
	687	m_cpt_ins_tlb_update_acc = 0;
	688
	689	m_cpt_data_tlb_read = 0;
	690	m_cpt_data_tlb_miss = 0;
	691	m_cpt_data_tlb_update_acc = 0;
	692	m_cpt_data_tlb_update_dirty = 0;
	693	m_cpt_ins_tlb_hit_dcache = 0;
	694	m_cpt_data_tlb_hit_dcache = 0;
	695	m_cpt_ins_tlb_occup_cache = 0;
	696	m_cpt_data_tlb_occup_cache = 0;
	697
	698	m_cost_ins_tlb_miss_frz = 0;
	699	m_cost_data_tlb_miss_frz = 0;
	700	m_cost_ins_tlb_update_acc_frz = 0;
	701	m_cost_data_tlb_update_acc_frz = 0;
	702	m_cost_data_tlb_update_dirty_frz = 0;
	703	m_cost_ins_tlb_occup_cache_frz = 0;
	704	m_cost_data_tlb_occup_cache_frz = 0;
	705
	706	m_cpt_itlbmiss_transaction = 0;
	707	m_cpt_itlb_ll_transaction = 0;
	708	m_cpt_itlb_sc_transaction = 0;
	709	m_cpt_dtlbmiss_transaction = 0;
	710	m_cpt_dtlb_ll_transaction = 0;
	711	m_cpt_dtlb_sc_transaction = 0;
	712	m_cpt_dtlb_ll_dirty_transaction = 0;
	713	m_cpt_dtlb_sc_dirty_transaction = 0;
	714
	715	m_cost_itlbmiss_transaction = 0;
	716	m_cost_itlb_ll_transaction = 0;
	717	m_cost_itlb_sc_transaction = 0;
	718	m_cost_dtlbmiss_transaction = 0;
	719	m_cost_dtlb_ll_transaction = 0;
	720	m_cost_dtlb_sc_transaction = 0;
	721	m_cost_dtlb_ll_dirty_transaction = 0;
	722	m_cost_dtlb_sc_dirty_transaction = 0;
	723
	724	m_cpt_cc_update_data = 0;
	725	m_cpt_cc_inval_ins = 0;
	726	m_cpt_cc_inval_data = 0;
	727	m_cpt_cc_broadcast = 0;
	728
	729	m_cost_updt_data_frz = 0;
	730	m_cost_inval_ins_frz = 0;
	731	m_cost_inval_data_frz = 0;
	732	m_cost_broadcast_frz = 0;
	733
	734	m_cpt_cc_cleanup_data = 0;
	735	m_cpt_cc_cleanup_ins = 0;
	736	}
	737
	738	*/
	739
	740	/////////////////////////
	741	tmpl(void)::transition()
	742	/////////////////////////
	743	{
[789]	744	if (not p_resetn.read())
[331]	745	{
	746	r_iss.reset();
	747	r_wbuf.reset();
	748	r_icache.reset();
	749	r_dcache.reset();
	750	r_itlb.reset();
	751	r_dtlb.reset();
	752
[789]	753	r_dcache_fsm = DCACHE_IDLE;
	754	r_icache_fsm = ICACHE_IDLE;
	755	r_vci_cmd_fsm = CMD_IDLE;
	756	r_vci_rsp_fsm = RSP_IDLE;
	757	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	758	r_cc_send_fsm = CC_SEND_IDLE;
[331]	759
[394]	760	// reset data physical address extension
[721]	761	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
[394]	762
[721]	763	// reset inst physical address extension
	764	r_icache_paddr_ext = m_icache_paddr_ext_reset;
	765
[331]	766	// reset dcache directory extension
[789]	767	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
[331]	768	{
[789]	769	r_dcache_in_tlb[i] = false;
[331]	770	r_dcache_contains_ptd[i] = false;
	771	}
	772
	773	// Response FIFOs and cleanup buffer
	774	r_vci_rsp_fifo_icache.init();
	775	r_vci_rsp_fifo_dcache.init();
	776
	777	// ICACHE & DCACHE activated
[394]	778	// ITLB & DTLB desactivated
[331]	779	r_mmu_mode = 0x3;
	780
[789]	781	// No request from ICACHE FSM to CMD FSM
[331]	782	r_icache_miss_req = false;
	783	r_icache_unc_req = false;
	784
	785	// No request from ICACHE_FSM to DCACHE FSM
	786	r_icache_tlb_miss_req = false;
	787
	788	// No request from ICACHE_FSM to CC_SEND FSM
	789	r_icache_cc_send_req = false;
[487]	790	r_icache_cleanup_victim_req = false;
[331]	791
[468]	792	r_icache_clack_req = false;
	793
[331]	794	// No pending write in pipeline
	795	r_dcache_wbuf_req = false;
	796	r_dcache_updt_req = false;
	797
	798	// No request from DCACHE_FSM to CMD_FSM
	799	r_dcache_vci_miss_req = false;
	800	r_dcache_vci_unc_req = false;
	801	r_dcache_vci_cas_req = false;
	802	r_dcache_vci_ll_req = false;
	803	r_dcache_vci_sc_req = false;
	804
	805	// No processor XTN request pending
	806	r_dcache_xtn_req = false;
	807
	808	// No request from DCACHE FSM to CC_SEND FSM
[789]	809	r_dcache_cc_send_req = false;
[487]	810	r_dcache_cleanup_victim_req = false;
[331]	811
[468]	812	r_dcache_clack_req = false;
	813
[331]	814	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
	815	r_cc_receive_icache_req = false;
	816	r_cc_receive_dcache_req = false;
	817
	818	// last cc_send client was dcache
	819	r_cc_send_last_client = false;
	820
	821	// No pending cleanup after a replacement
	822	r_icache_miss_clack = false;
	823	r_dcache_miss_clack = false;
	824
	825	// No signalisation of a coherence request matching a pending miss
	826	r_icache_miss_inval = false;
	827	r_dcache_miss_inval = false;
	828
[468]	829	r_dspin_clack_req = false;
	830
[331]	831	// No signalisation of errors
	832	r_vci_rsp_ins_error = false;
	833	r_vci_rsp_data_error = false;
	834
	835	// Debug variables
[394]	836	m_debug_previous_i_hit = false;
	837	m_debug_previous_d_hit = false;
[789]	838	m_debug_icache_fsm = false;
	839	m_debug_dcache_fsm = false;
	840	m_debug_cmd_fsm = false;
[331]	841
	842	// activity counters
	843	m_cpt_dcache_data_read = 0;
	844	m_cpt_dcache_data_write = 0;
	845	m_cpt_dcache_dir_read = 0;
	846	m_cpt_dcache_dir_write = 0;
	847	m_cpt_icache_data_read = 0;
	848	m_cpt_icache_data_write = 0;
	849	m_cpt_icache_dir_read = 0;
	850	m_cpt_icache_dir_write = 0;
	851
	852	m_cpt_frz_cycles = 0;
	853	m_cpt_total_cycles = 0;
	854	m_cpt_stop_simulation = 0;
	855
	856	m_cpt_data_miss = 0;
	857	m_cpt_ins_miss = 0;
	858	m_cpt_unc_read = 0;
	859	m_cpt_write_cached = 0;
	860	m_cpt_ins_read = 0;
	861
	862	m_cost_write_frz = 0;
	863	m_cost_data_miss_frz = 0;
	864	m_cost_unc_read_frz = 0;
	865	m_cost_ins_miss_frz = 0;
	866
	867	m_cpt_imiss_transaction = 0;
	868	m_cpt_dmiss_transaction = 0;
	869	m_cpt_unc_transaction = 0;
	870	m_cpt_write_transaction = 0;
	871	m_cpt_icache_unc_transaction = 0;
	872
	873	m_cost_imiss_transaction = 0;
	874	m_cost_dmiss_transaction = 0;
	875	m_cost_unc_transaction = 0;
	876	m_cost_write_transaction = 0;
	877	m_cost_icache_unc_transaction = 0;
	878	m_length_write_transaction = 0;
	879
	880	m_cpt_ins_tlb_read = 0;
	881	m_cpt_ins_tlb_miss = 0;
	882	m_cpt_ins_tlb_update_acc = 0;
	883
	884	m_cpt_data_tlb_read = 0;
	885	m_cpt_data_tlb_miss = 0;
	886	m_cpt_data_tlb_update_acc = 0;
	887	m_cpt_data_tlb_update_dirty = 0;
	888	m_cpt_ins_tlb_hit_dcache = 0;
	889	m_cpt_data_tlb_hit_dcache = 0;
	890	m_cpt_ins_tlb_occup_cache = 0;
	891	m_cpt_data_tlb_occup_cache = 0;
	892
	893	m_cost_ins_tlb_miss_frz = 0;
	894	m_cost_data_tlb_miss_frz = 0;
	895	m_cost_ins_tlb_update_acc_frz = 0;
	896	m_cost_data_tlb_update_acc_frz = 0;
	897	m_cost_data_tlb_update_dirty_frz = 0;
	898	m_cost_ins_tlb_occup_cache_frz = 0;
	899	m_cost_data_tlb_occup_cache_frz = 0;
	900
[789]	901	m_cpt_ins_tlb_inval = 0;
	902	m_cpt_data_tlb_inval = 0;
	903	m_cost_ins_tlb_inval_frz = 0;
	904	m_cost_data_tlb_inval_frz = 0;
[331]	905
	906	m_cpt_cc_broadcast = 0;
	907
[789]	908	m_cost_updt_data_frz = 0;
	909	m_cost_inval_ins_frz = 0;
	910	m_cost_inval_data_frz = 0;
	911	m_cost_broadcast_frz = 0;
[331]	912
[789]	913	m_cpt_cc_cleanup_data = 0;
	914	m_cpt_cc_cleanup_ins = 0;
[331]	915
	916	m_cpt_itlbmiss_transaction = 0;
	917	m_cpt_itlb_ll_transaction = 0;
	918	m_cpt_itlb_sc_transaction = 0;
	919	m_cpt_dtlbmiss_transaction = 0;
	920	m_cpt_dtlb_ll_transaction = 0;
	921	m_cpt_dtlb_sc_transaction = 0;
	922	m_cpt_dtlb_ll_dirty_transaction = 0;
	923	m_cpt_dtlb_sc_dirty_transaction = 0;
	924
	925	m_cost_itlbmiss_transaction = 0;
	926	m_cost_itlb_ll_transaction = 0;
	927	m_cost_itlb_sc_transaction = 0;
	928	m_cost_dtlbmiss_transaction = 0;
	929	m_cost_dtlb_ll_transaction = 0;
	930	m_cost_dtlb_sc_transaction = 0;
	931	m_cost_dtlb_ll_dirty_transaction = 0;
	932	m_cost_dtlb_sc_dirty_transaction = 0;
	933	/*
	934	m_cpt_dcache_frz_cycles = 0;
[789]	935	m_cpt_read = 0;
	936	m_cpt_write = 0;
	937	m_cpt_cc_update_data = 0;
	938	m_cpt_cc_inval_ins = 0;
	939	m_cpt_cc_inval_data = 0;
[331]	940	*/
	941
[789]	942	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
	943	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
	944	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
	945	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
[331]	946
	947	// init the llsc reservation buffer
	948	r_dcache_llsc_valid = false;
[423]	949	m_monitor_ok = false;
[331]	950
	951	return;
	952	}
	953
	954	// Response FIFOs default values
[789]	955	bool vci_rsp_fifo_icache_get = false;
	956	bool vci_rsp_fifo_icache_put = false;
	957	uint32_t vci_rsp_fifo_icache_data = 0;
[331]	958
[789]	959	bool vci_rsp_fifo_dcache_get = false;
	960	bool vci_rsp_fifo_dcache_put = false;
	961	uint32_t vci_rsp_fifo_dcache_data = 0;
[331]	962
	963	// updt fifo
[789]	964	bool cc_receive_updt_fifo_get = false;
	965	bool cc_receive_updt_fifo_put = false;
	966	uint32_t cc_receive_updt_fifo_be = 0;
	967	uint32_t cc_receive_updt_fifo_data = 0;
	968	bool cc_receive_updt_fifo_eop = false;
[331]	969
	970	#ifdef INSTRUMENTATION
[789]	971	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
	972	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
	973	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
	974	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
	975	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
	976	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
[331]	977	#endif
	978
	979	m_cpt_total_cycles++;
	980
[668]	981	m_debug_icache_fsm = m_debug_icache_fsm \|\|
	982	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
	983	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
	984	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
	985	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
	986	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
[331]	987
	988	/////////////////////////////////////////////////////////////////////
	989	// Get data and instruction requests from processor
	990	///////////////////////////////////////////////////////////////////////
	991
	992	r_iss.getRequests(m_ireq, m_dreq);
	993
	994	////////////////////////////////////////////////////////////////////////////////////
	995	// ICACHE_FSM
	996	//
	997	// 1/ Coherence operations
	998	// They are handled as interrupts generated by the CC_RECEIVE FSM.
	999	// - There is a coherence request when r_tgt_icache_req is set.
	1000	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
	1001	// - There is a cleanup ack request when r_cleanup_icache_req is set.
	1002	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
	1003	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
	1004	// - For both types of requests, actions associated to the pre-empted state
	1005	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
	1006	// or CC_CLACK) to execute the requested coherence operation, and returns
	1007	// to the pre-empted state.
	1008	//
	1009	// 2/ Processor requests
	1010	// They are taken in IDLE state only. In case of cache miss, or uncacheable
	1011	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
	1012	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
	1013	// flip-flops are reset when the transaction starts.
	1014	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
	1015	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
	1016	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
	1017	// The availability of the missing cache line is signaled by the response fifo,
	1018	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
	1019	// and ICACHE_MISS_DIR_UPDT states.
	1020	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
	1021	// to wait the response from the RSP FSM, through the response fifo.
	1022	// The missing instruction is directly returned to processor in this state.
	1023	//
	1024	// 3/ TLB miss
	1025	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
	1026	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
	1027	// register, and goes to the ICACHE_TLB_WAIT state.
	1028	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
	1029	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
	1030	// to signal the completion.
	1031	//
	1032	// 4/ XTN requests
	1033	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
	1034	// using the r_dcache_xtn_req flip-flop.
	1035	// The request opcode and the address to be invalidated are transmitted
	1036	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
	1037	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
	1038	// is completed.
	1039	//
	1040	// 5/ Error Handling
	1041	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
	1042	// in a cache miss or uncacheable read VCI transaction. Nothing is written
	1043	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
	1044	////////////////////////////////////////////////////////////////////////////////////////
	1045
	1046	// default value for m_irsp
[789]	1047	m_irsp.valid = false;
	1048	m_irsp.error = false;
[331]	1049	m_irsp.instruction = 0;
	1050
[789]	1051	switch (r_icache_fsm.read())
[331]	1052	{
	1053	/////////////////
[789]	1054	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
[331]	1055	// and coherence requests with a fixed priority:
	1056	// 1/ Coherence requests => ICACHE_CC_CHECK
	1057	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
	1058	// 3/ tlb miss => ICACHE_TLB_WAIT
	1059	// 4/ cacheable read miss => ICACHE_MISS_SELECT
	1060	// 5/ uncacheable read miss => ICACHE_UNC_REQ
	1061	{
[468]	1062	// coherence clack interrupt
[789]	1063	if (r_icache_clack_req.read())
[468]	1064	{
	1065	r_icache_fsm = ICACHE_CC_CHECK;
	1066	r_icache_fsm_save = r_icache_fsm.read();
	1067	break;
	1068	}
	1069
[331]	1070	// coherence interrupt
[789]	1071	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1072	{
	1073	r_icache_fsm = ICACHE_CC_CHECK;
	1074	r_icache_fsm_save = r_icache_fsm.read();
	1075	break;
	1076	}
	1077
	1078	// XTN requests sent by DCACHE FSM
[721]	1079	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
	1080	// because they require access to icache or itlb, that are already accessed
[789]	1081	if (r_dcache_xtn_req.read())
[331]	1082	{
[789]	1083	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
[331]	1084	{
[789]	1085	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
[331]	1086	}
[789]	1087	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
[331]	1088	{
	1089	r_icache_flush_count = 0;
[789]	1090	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
[331]	1091	}
[789]	1092	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
[331]	1093	{
[789]	1094	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
[331]	1095	}
[789]	1096	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
[331]	1097	{
[789]	1098	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
[331]	1099	}
[789]	1100	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
[331]	1101	{
[970]	1102	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
	1103	((uint64_t)r_mmu_word_lo.read());
	1104
	1105	r_icache_vci_paddr = (paddr_t)pa;
[721]	1106	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
[331]	1107	}
[789]	1108	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
[721]	1109	{
[816]	1110	r_icache_paddr_ext = r_dcache_save_wdata.read();
[721]	1111	r_dcache_xtn_req = false;
	1112	}
[331]	1113	else
	1114	{
[789]	1115	assert(false and
[331]	1116	"undefined XTN request received by ICACHE FSM");
	1117	}
	1118	break;
	1119	} // end if xtn_req
	1120
	1121	// processor request
[789]	1122	if (m_ireq.valid )
[331]	1123	{
[789]	1124	bool cacheable;
	1125	paddr_t paddr;
	1126	bool tlb_hit = false;
	1127	pte_info_t tlb_flags;
	1128	size_t tlb_way;
	1129	size_t tlb_set;
	1130	paddr_t tlb_nline;
	1131	uint32_t cache_inst = 0;
	1132	size_t cache_way;
	1133	size_t cache_set;
	1134	size_t cache_word;
	1135	int cache_state = CACHE_SLOT_STATE_EMPTY;
[331]	1136
	1137	// We register processor request
	1138	r_icache_vaddr_save = m_ireq.addr;
[752]	1139	paddr = (paddr_t) m_ireq.addr;
[331]	1140
	1141	// sytematic itlb access (if activated)
[789]	1142	if (r_mmu_mode.read() & INS_TLB_MASK)
[331]	1143	{
	1144
	1145	#ifdef INSTRUMENTATION
[789]	1146	m_cpt_itlb_read++;
[331]	1147	#endif
[789]	1148	tlb_hit = r_itlb.translate(m_ireq.addr,
	1149	&paddr,
	1150	&tlb_flags,
	1151	&tlb_nline, // unused
	1152	&tlb_way, // unused
	1153	&tlb_set); // unused
[331]	1154	}
[752]	1155	else if (vci_param::N > 32)
[331]	1156	{
[752]	1157	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
[331]	1158	}
	1159
	1160	// systematic icache access (if activated)
[789]	1161	if (r_mmu_mode.read() & INS_CACHE_MASK)
[331]	1162	{
	1163
	1164
	1165	#ifdef INSTRUMENTATION
[789]	1166	m_cpt_icache_data_read++;
	1167	m_cpt_icache_dir_read++;
[331]	1168	#endif
[789]	1169	r_icache.read(paddr,
	1170	&cache_inst,
	1171	&cache_way,
	1172	&cache_set,
	1173	&cache_word,
	1174	&cache_state);
[331]	1175	}
	1176
	1177	// We compute cacheability and check access rights:
	1178	// - If MMU activated : cacheability is defined by the C bit in the PTE,
	1179	// and the access rights are defined by the U and X bits in the PTE.
	1180	// - If MMU not activated : cacheability is defined by the segment table,
	1181	// and there is no access rights checking
	1182
[789]	1183	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
[331]	1184	{
	1185	// cacheability
[789]	1186	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
	1187	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
[331]	1188	}
[789]	1189	else // itlb activated
[331]	1190	{
[789]	1191	if (tlb_hit) // ITLB hit
[331]	1192	{
	1193	// cacheability
[789]	1194	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
[331]	1195	else cacheable = tlb_flags.c;
	1196
	1197	// access rights checking
[789]	1198	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
[331]	1199	{
[809]	1200
	1201	#if DEBUG_ICACHE
	1202	if ( m_debug_icache_fsm )
[816]	1203	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
[809]	1204	<< " : PADDR = " << std::hex << paddr << std::endl;
	1205	#endif
	1206	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
	1207	r_mmu_ibvar = m_ireq.addr;
	1208	m_irsp.valid = true;
	1209	m_irsp.error = true;
	1210	m_irsp.instruction = 0;
[331]	1211	break;
	1212	}
[789]	1213	else if (not tlb_flags.x)
[331]	1214	{
[809]	1215
	1216	#if DEBUG_ICACHE
	1217	if ( m_debug_icache_fsm )
[816]	1218	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
[809]	1219	<< " : PADDR = " << std::hex << paddr << std::endl;
	1220	#endif
	1221	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
	1222	r_mmu_ibvar = m_ireq.addr;
	1223	m_irsp.valid = true;
	1224	m_irsp.error = true;
	1225	m_irsp.instruction = 0;
[331]	1226	break;
	1227	}
	1228	}
[789]	1229	else // ITLB miss
[331]	1230	{
	1231
	1232	#ifdef INSTRUMENTATION
[789]	1233	m_cpt_itlb_miss++;
[331]	1234	#endif
	1235	r_icache_fsm = ICACHE_TLB_WAIT;
	1236	r_icache_tlb_miss_req = true;
	1237	break;
	1238	}
	1239	} // end if itlb activated
	1240
	1241	// physical address registration
[789]	1242	r_icache_vci_paddr = paddr;
[331]	1243
	1244	// Finally, we send the response to processor, and compute next state
[789]	1245	if (cacheable)
[331]	1246	{
[789]	1247	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
[331]	1248	{
	1249
	1250	#ifdef INSTRUMENTATION
[789]	1251	m_cpt_icache_miss++;
[331]	1252	#endif
	1253	// we request a VCI transaction
[789]	1254	r_icache_fsm = ICACHE_MISS_SELECT;
[386]	1255	#if DEBUG_ICACHE
[789]	1256	if (m_debug_icache_fsm)
[816]	1257	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
[789]	1258	<< " : PADDR = " << std::hex << paddr << std::endl;
[386]	1259	#endif
	1260	r_icache_miss_req = true;
[331]	1261	}
[789]	1262	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
[331]	1263	{
	1264	// stalled until cleanup is acknowledged
[789]	1265	r_icache_fsm = ICACHE_IDLE;
[331]	1266	}
[789]	1267	else // cache hit
[331]	1268	{
	1269
	1270	#ifdef INSTRUMENTATION
[789]	1271	m_cpt_ins_read++;
[331]	1272	#endif
	1273	// return instruction to processor
	1274	m_irsp.valid = true;
	1275	m_irsp.instruction = cache_inst;
	1276	r_icache_fsm = ICACHE_IDLE;
[386]	1277	#if DEBUG_ICACHE
[789]	1278	if (m_debug_icache_fsm)
[816]	1279	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
[789]	1280	<< " : PADDR = " << std::hex << paddr
	1281	<< " / INST = " << cache_inst << std::endl;
[386]	1282	#endif
[331]	1283	}
	1284	}
[789]	1285	else // non cacheable read
[331]	1286	{
[789]	1287	r_icache_unc_req = true;
	1288	r_icache_fsm = ICACHE_UNC_WAIT;
[386]	1289
	1290	#if DEBUG_ICACHE
[789]	1291	if (m_debug_icache_fsm)
	1292	{
	1293	std::cout << " <PROC " << name()
[816]	1294	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
[789]	1295	<< " : PADDR = " << std::hex << paddr << std::endl;
	1296	}
[386]	1297	#endif
[331]	1298	}
	1299	} // end if m_ireq.valid
	1300	break;
	1301	}
	1302	/////////////////////
[789]	1303	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
[331]	1304	// the itlb is udated by the DCACHE FSM, as well as the
	1305	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
	1306	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
	1307	// reset the r_icache_tlb_miss_req flip-flop
	1308	// external coherence request are accepted in this state.
	1309	{
[468]	1310	// coherence clack interrupt
[789]	1311	if (r_icache_clack_req.read())
[468]	1312	{
	1313	r_icache_fsm = ICACHE_CC_CHECK;
	1314	r_icache_fsm_save = r_icache_fsm.read();
	1315	break;
	1316	}
	1317
[331]	1318	// coherence interrupt
[789]	1319	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1320	{
	1321	r_icache_fsm = ICACHE_CC_CHECK;
	1322	r_icache_fsm_save = r_icache_fsm.read();
	1323	break;
	1324	}
	1325
[789]	1326	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
[331]	1327
	1328	// DCACHE FSM signals response by reseting the request flip-flop
[789]	1329	if (not r_icache_tlb_miss_req.read())
[331]	1330	{
[789]	1331	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
[331]	1332	{
	1333	r_icache_tlb_rsp_error = false;
[789]	1334	m_irsp.error = true;
	1335	m_irsp.valid = true;
	1336	r_icache_fsm = ICACHE_IDLE;
[331]	1337	}
[789]	1338	else // tlb updated : return to IDLE state
[331]	1339	{
	1340	r_icache_fsm = ICACHE_IDLE;
	1341	}
	1342	}
	1343	break;
	1344	}
	1345	//////////////////////////
[789]	1346	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
[331]	1347	{
	1348	r_itlb.flush();
[789]	1349	r_dcache_xtn_req = false;
	1350	r_icache_fsm = ICACHE_IDLE;
[331]	1351	break;
	1352	}
	1353	////////////////////////////
[789]	1354	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
[331]	1355	// r_icache_flush_count as a slot counter,
[789]	1356	// looping in this state until all slots are visited.
[331]	1357	// It can require two cycles per slot:
	1358	// We test here the slot state, and make the actual inval
	1359	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
[789]	1360	// A cleanup request is generated for each valid line
[331]	1361	{
[468]	1362	// coherence clack interrupt
[789]	1363	if (r_icache_clack_req.read())
[468]	1364	{
	1365	r_icache_fsm = ICACHE_CC_CHECK;
	1366	r_icache_fsm_save = r_icache_fsm.read();
	1367	break;
	1368	}
	1369
[384]	1370	// coherence request (from CC_RECEIVE FSM)
[789]	1371	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[384]	1372	{
	1373	r_icache_fsm = ICACHE_CC_CHECK;
	1374	r_icache_fsm_save = r_icache_fsm.read();
	1375	break;
	1376	}
	1377
[789]	1378	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
[331]	1379	{
[789]	1380	int state;
	1381	paddr_t tag;
[836]	1382	size_t way = r_icache_flush_count.read() / m_icache_sets;
	1383	size_t set = r_icache_flush_count.read() % m_icache_sets;
[331]	1384
[1041]	1385	if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways)) // last slot
	1386	{
	1387	r_dcache_xtn_req = false;
	1388	m_drsp.valid = true;
	1389	r_icache_fsm = ICACHE_IDLE;
	1390	break;
	1391	}
	1392
	1393
[331]	1394	#ifdef INSTRUMENTATION
[789]	1395	m_cpt_icache_dir_read++;
[331]	1396	#endif
[789]	1397	r_icache.read_dir(way,
	1398	set,
	1399	&tag,
	1400	&state);
[331]	1401
[789]	1402	if (state == CACHE_SLOT_STATE_VALID) // inval required
[331]	1403	{
	1404	// request cleanup
	1405	r_icache_cc_send_req = true;
[384]	1406	r_icache_cc_send_nline = tag * m_icache_sets + set;
[331]	1407	r_icache_cc_send_way = way;
	1408	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	1409
	1410	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
[789]	1411	r_icache_miss_way = way;
	1412	r_icache_miss_set = set;
	1413	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
[331]	1414	}
[1041]	1415	else {
	1416	// saturation counter, to have the same last slot condition
	1417	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
[331]	1418	r_icache_flush_count = r_icache_flush_count.read() + 1;
	1419	}
	1420	}
	1421	break;
	1422	}
	1423	///////////////////////////////
[789]	1424	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
[331]	1425	{
[789]	1426	size_t way = r_icache_miss_way.read();
	1427	size_t set = r_icache_miss_set.read();
[331]	1428
	1429	#ifdef INSTRUMENTATION
[789]	1430	m_cpt_icache_dir_write++;
[331]	1431	#endif
	1432
[789]	1433	r_icache.write_dir(way,
	1434	set,
	1435	CACHE_SLOT_STATE_ZOMBI);
[331]	1436
[1041]	1437	if (r_icache_flush_count.read() == (m_icache_sets * m_icache_ways - 1)) // last slot
[331]	1438	{
[789]	1439	r_icache_fsm = ICACHE_IDLE;
[1041]	1440	break;
[331]	1441	}
[1041]	1442	r_icache_flush_count = r_icache_flush_count.read() + 1;
	1443	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
[331]	1444	break;
	1445	}
	1446
	1447	//////////////////////////
[789]	1448	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
	1449	// stored in the r_dcache_save_wdata register
[331]	1450	{
	1451	r_itlb.inval(r_dcache_save_wdata.read());
[789]	1452	r_dcache_xtn_req = false;
	1453	r_icache_fsm = ICACHE_IDLE;
[331]	1454	break;
	1455	}
	1456	///////////////////////////////
[789]	1457	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
[331]	1458	// requires 3 cycles (in case of hit on itlb and icache).
[789]	1459	// In this state, access TLB to translate virtual address
	1460	// stored in the r_dcache_save_wdata register.
[331]	1461	{
[789]	1462	paddr_t paddr;
	1463	bool hit;
[331]	1464
	1465	// read physical address in TLB when MMU activated
[789]	1466	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
[331]	1467	{
	1468
	1469	#ifdef INSTRUMENTATION
[789]	1470	m_cpt_itlb_read++;
[331]	1471	#endif
[789]	1472	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
[331]	1473	}
[789]	1474	else // itlb not activated
[331]	1475	{
[789]	1476	paddr = (paddr_t) r_dcache_save_wdata.read();
	1477	hit = true;
[331]	1478	}
	1479
[789]	1480	if (hit) // continue the selective inval process
[331]	1481	{
[789]	1482	r_icache_vci_paddr = paddr;
	1483	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
[331]	1484	}
[789]	1485	else // miss : send a request to DCACHE FSM
[331]	1486	{
	1487
	1488	#ifdef INSTRUMENTATION
[789]	1489	m_cpt_itlb_miss++;
[331]	1490	#endif
	1491	r_icache_tlb_miss_req = true;
[789]	1492	r_icache_vaddr_save = r_dcache_save_wdata.read();
[331]	1493	r_icache_fsm = ICACHE_TLB_WAIT;
	1494	}
	1495	break;
	1496	}
	1497	///////////////////////////////
[789]	1498	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
[331]	1499	// require 2 cycles. In this state, we read directory
	1500	// with address stored in r_icache_vci_paddr register.
	1501	{
[789]	1502	int state;
	1503	size_t way;
	1504	size_t set;
	1505	size_t word;
[331]	1506
	1507	#ifdef INSTRUMENTATION
[789]	1508	m_cpt_icache_dir_read++;
[331]	1509	#endif
	1510	r_icache.read_dir(r_icache_vci_paddr.read(),
	1511	&state,
	1512	&way,
	1513	&set,
	1514	&word);
	1515
[789]	1516	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
[331]	1517	{
	1518	r_icache_miss_way = way;
	1519	r_icache_miss_set = set;
	1520	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
	1521	}
[789]	1522	else // miss : acknowlege the XTN request and return
[331]	1523	{
	1524	r_dcache_xtn_req = false;
	1525	r_icache_fsm = ICACHE_IDLE;
	1526	}
	1527	break;
	1528	}
	1529	///////////////////////////////
	1530	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
	1531	{
[789]	1532	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
[331]	1533	{
	1534
	1535	#ifdef INSTRUMENTATION
[789]	1536	m_cpt_icache_dir_write++;
[331]	1537	#endif
[789]	1538	r_icache.write_dir(r_icache_miss_way.read(),
	1539	r_icache_miss_set.read(),
	1540	CACHE_SLOT_STATE_ZOMBI);
[331]	1541
	1542	// request cleanup
	1543	r_icache_cc_send_req = true;
[789]	1544	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
[331]	1545	r_icache_cc_send_way = r_icache_miss_way.read();
	1546	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	1547
	1548	// acknowledge the XTN request and return
[789]	1549	r_dcache_xtn_req = false;
	1550	r_icache_fsm = ICACHE_IDLE;
[331]	1551	}
	1552	break;
	1553	}
	1554	////////////////////////
	1555	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
	1556	// Waiting in this state if no slot available.
[816]	1557	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
	1558	// we send the cleanup request in this state.
[487]	1559	// If not, a r_icache_cleanup_victim_req flip-flop is
	1560	// utilized for saving this cleanup request, and it will be sent later
[816]	1561	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
[487]	1562	// The r_icache_miss_clack flip-flop is set
[331]	1563	// when a cleanup is required
	1564	{
	1565	if (m_ireq.valid) m_cost_ins_miss_frz++;
	1566
[468]	1567	// coherence clack interrupt
[789]	1568	if (r_icache_clack_req.read())
[468]	1569	{
	1570	r_icache_fsm = ICACHE_CC_CHECK;
	1571	r_icache_fsm_save = r_icache_fsm.read();
	1572	break;
	1573	}
	1574
[331]	1575	// coherence interrupt
[789]	1576	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1577	{
	1578	r_icache_fsm = ICACHE_CC_CHECK;
	1579	r_icache_fsm_save = r_icache_fsm.read();
	1580	break;
	1581	}
	1582
	1583
[789]	1584	bool found;
	1585	bool cleanup;
	1586	size_t way;
	1587	size_t set;
	1588	paddr_t victim;
[487]	1589
[331]	1590	#ifdef INSTRUMENTATION
[789]	1591	m_cpt_icache_dir_read++;
[331]	1592	#endif
[487]	1593	r_icache.read_select(r_icache_vci_paddr.read(),
	1594	&victim,
	1595	&way,
	1596	&set,
	1597	&found,
[789]	1598	&cleanup);
	1599	if (not found)
[487]	1600	{
	1601	break;
	1602	}
	1603	else
	1604	{
[789]	1605	r_icache_miss_way = way;
	1606	r_icache_miss_set = set;
[487]	1607
[789]	1608	if (cleanup)
[331]	1609	{
[789]	1610	if (not r_icache_cc_send_req.read())
[331]	1611	{
[789]	1612	r_icache_cc_send_req = true;
	1613	r_icache_cc_send_nline = victim;
	1614	r_icache_cc_send_way = way;
[816]	1615	r_icache_cc_send_type = CC_TYPE_CLEANUP;
[331]	1616	}
	1617	else
	1618	{
[487]	1619	r_icache_cleanup_victim_req = true;
	1620	r_icache_cleanup_victim_nline = victim;
[331]	1621	}
	1622
[789]	1623	r_icache_miss_clack = true;
	1624	r_icache_fsm = ICACHE_MISS_CLEAN;
[487]	1625	}
	1626	else
	1627	{
[789]	1628	r_icache_fsm = ICACHE_MISS_WAIT;
[487]	1629	}
	1630
[331]	1631	#if DEBUG_ICACHE
[789]	1632	if (m_debug_icache_fsm)
	1633	{
	1634	std::cout << " <PROC " << name()
	1635	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
	1636	<< " / WAY = " << way
	1637	<< " / SET = " << set;
	1638	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
	1639	else std::cout << std::endl;
	1640	}
[331]	1641	#endif
	1642	}
	1643	break;
	1644	}
	1645	///////////////////////
[789]	1646	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
[331]	1647	{
	1648	if (m_ireq.valid) m_cost_ins_miss_frz++;
	1649
	1650	#ifdef INSTRUMENTATION
[789]	1651	m_cpt_icache_dir_write++;
[331]	1652	#endif
[789]	1653	r_icache.write_dir(r_icache_miss_way.read(),
	1654	r_icache_miss_set.read(),
	1655	CACHE_SLOT_STATE_ZOMBI);
[331]	1656	#if DEBUG_ICACHE
[789]	1657	if (m_debug_icache_fsm)
	1658	{
	1659	std::cout << " <PROC " << name()
	1660	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
	1661	<< " / WAY = " << r_icache_miss_way.read()
	1662	<< " / SET = " << r_icache_miss_set.read() << std::endl;
	1663	}
[331]	1664	#endif
	1665
	1666	r_icache_fsm = ICACHE_MISS_WAIT;
	1667	break;
	1668	}
	1669	//////////////////////
[789]	1670	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
[331]	1671	{
	1672	if (m_ireq.valid) m_cost_ins_miss_frz++;
	1673
[487]	1674	// send cleanup victim request
[789]	1675	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
[487]	1676	{
	1677	r_icache_cc_send_req = true;
	1678	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
	1679	r_icache_cc_send_way = r_icache_miss_way;
[816]	1680	r_icache_cc_send_type = CC_TYPE_CLEANUP;
[487]	1681	r_icache_cleanup_victim_req = false;
[816]	1682	}
[468]	1683
[488]	1684	// coherence clack interrupt
[789]	1685	if (r_icache_clack_req.read())
[488]	1686	{
	1687	r_icache_fsm = ICACHE_CC_CHECK;
	1688	r_icache_fsm_save = r_icache_fsm.read();
	1689	break;
	1690	}
[816]	1691
[331]	1692	// coherence interrupt
[789]	1693	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
[331]	1694	{
	1695	r_icache_fsm = ICACHE_CC_CHECK;
	1696	r_icache_fsm_save = r_icache_fsm.read();
	1697	break;
	1698	}
	1699
[789]	1700	if (r_vci_rsp_ins_error.read()) // bus error
[331]	1701	{
	1702	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
	1703	r_mmu_ibvar = r_icache_vaddr_save.read();
	1704	m_irsp.valid = true;
	1705	m_irsp.error = true;
	1706	r_vci_rsp_ins_error = false;
	1707	r_icache_fsm = ICACHE_IDLE;
	1708	}
[789]	1709	else if (r_vci_rsp_fifo_icache.rok()) // response available
[331]	1710	{
	1711	r_icache_miss_word = 0;
	1712	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
	1713	}
	1714	break;
	1715	}
	1716	///////////////////////////
[789]	1717	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
[331]	1718	{
[789]	1719	if (m_ireq.valid) m_cost_ins_miss_frz++;
[331]	1720
[789]	1721	if (r_vci_rsp_fifo_icache.rok()) // response available
[331]	1722	{
	1723
	1724	#ifdef INSTRUMENTATION
[789]	1725	m_cpt_icache_data_write++;
[331]	1726	#endif
[789]	1727	r_icache.write(r_icache_miss_way.read(),
	1728	r_icache_miss_set.read(),
	1729	r_icache_miss_word.read(),
	1730	r_vci_rsp_fifo_icache.read());
[331]	1731	#if DEBUG_ICACHE
[789]	1732	if (m_debug_icache_fsm)
	1733	{
	1734	std::cout << " <PROC " << name()
	1735	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
	1736	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
	1737	<< " WAY = " << r_icache_miss_way.read()
	1738	<< " SET = " << r_icache_miss_set.read()
	1739	<< " WORD = " << r_icache_miss_word.read() << std::endl;
	1740	}
[331]	1741	#endif
	1742	vci_rsp_fifo_icache_get = true;
	1743	r_icache_miss_word = r_icache_miss_word.read() + 1;
	1744
[789]	1745	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
[331]	1746	{
	1747	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
	1748	}
	1749	}
	1750	break;
	1751	}
	1752	//////////////////////////
[789]	1753	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
[331]	1754	// and the cleanup ack has not been received,
	1755	// as indicated by r_icache_miss_clack.
	1756	// - If no matching coherence request (r_icache_miss_inval)
	1757	// switch directory slot to VALID state.
	1758	// - If matching coherence request, switch directory slot
	1759	// to ZOMBI state, and send a cleanup request.
	1760	{
[789]	1761	if (m_ireq.valid ) m_cost_ins_miss_frz++;
[331]	1762
[487]	1763	// send cleanup victim request
[789]	1764	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
[487]	1765	{
	1766	r_icache_cc_send_req = true;
	1767	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
	1768	r_icache_cc_send_way = r_icache_miss_way;
[816]	1769	r_icache_cc_send_type = CC_TYPE_CLEANUP;
[487]	1770	r_icache_cleanup_victim_req = false;
[816]	1771	}
[487]	1772
[488]	1773	// coherence clack interrupt
[789]	1774	if (r_icache_clack_req.read())
[488]	1775	{
	1776	r_icache_fsm = ICACHE_CC_CHECK;
	1777	r_icache_fsm_save = r_icache_fsm.read();
	1778	break;
	1779	}
	1780
[331]	1781	// coherence interrupt
[789]	1782	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
[331]	1783	{
	1784	r_icache_fsm = ICACHE_CC_CHECK;
	1785	r_icache_fsm_save = r_icache_fsm.read();
	1786	break;
	1787	}
	1788
[789]	1789	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
[331]	1790	{
[789]	1791	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
[331]	1792	{
[789]	1793	if (not r_icache_cc_send_req.read())
[331]	1794	{
	1795	r_icache_miss_inval = false;
	1796	// request cleanup
	1797	r_icache_cc_send_req = true;
[789]	1798	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
[331]	1799	r_icache_cc_send_way = r_icache_miss_way.read();
	1800	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	1801
	1802	#ifdef INSTRUMENTATION
[789]	1803	m_cpt_icache_dir_write++;
[331]	1804	#endif
[789]	1805	r_icache.write_dir(r_icache_vci_paddr.read(),
	1806	r_icache_miss_way.read(),
	1807	r_icache_miss_set.read(),
	1808	CACHE_SLOT_STATE_ZOMBI);
[331]	1809	#if DEBUG_ICACHE
[789]	1810	if (m_debug_icache_fsm)
	1811	{
	1812	std::cout << " <PROC " << name()
	1813	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
	1814	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
	1815	<< " WAY = " << std::dec << r_icache_miss_way.read()
	1816	<< " SET = " << r_icache_miss_set.read() << std::endl;
	1817	}
[331]	1818	#endif
	1819	}
	1820	else
	1821	break;
	1822	}
[789]	1823	else // Switch slot to VALID state
[331]	1824	{
	1825
	1826	#ifdef INSTRUMENTATION
[789]	1827	m_cpt_icache_dir_write++;
[331]	1828	#endif
[789]	1829	r_icache.write_dir(r_icache_vci_paddr.read(),
	1830	r_icache_miss_way.read(),
	1831	r_icache_miss_set.read(),
	1832	CACHE_SLOT_STATE_VALID);
[331]	1833	#if DEBUG_ICACHE
[789]	1834	if (m_debug_icache_fsm)
	1835	{
	1836	std::cout << " <PROC " << name()
	1837	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
	1838	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
	1839	<< " WAY = " << std::dec << r_icache_miss_way.read()
	1840	<< " SET = " << r_icache_miss_set.read() << std::endl;
	1841	}
[331]	1842	#endif
	1843	}
	1844
	1845	r_icache_fsm = ICACHE_IDLE;
	1846	}
	1847	break;
	1848	}
	1849	////////////////////
[789]	1850	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
[331]	1851	{
[468]	1852	// coherence clack interrupt
[789]	1853	if (r_icache_clack_req.read())
[468]	1854	{
[789]	1855	r_icache_fsm = ICACHE_CC_CHECK;
[468]	1856	r_icache_fsm_save = r_icache_fsm.read();
	1857	break;
	1858	}
	1859
[331]	1860	// coherence interrupt
[789]	1861	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
[331]	1862	{
[789]	1863	r_icache_fsm = ICACHE_CC_CHECK;
[331]	1864	r_icache_fsm_save = r_icache_fsm.read();
	1865	break;
	1866	}
	1867
[789]	1868	if (r_vci_rsp_ins_error.read()) // bus error
[331]	1869	{
	1870	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
	1871	r_mmu_ibvar = m_ireq.addr;
	1872	r_vci_rsp_ins_error = false;
	1873	m_irsp.valid = true;
	1874	m_irsp.error = true;
	1875	r_icache_fsm = ICACHE_IDLE;
	1876	}
[789]	1877	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
[331]	1878	{
	1879	vci_rsp_fifo_icache_get = true;
	1880	r_icache_fsm = ICACHE_IDLE;
[789]	1881	if (m_ireq.valid and
	1882	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
[331]	1883	{
	1884	m_irsp.valid = true;
	1885	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
	1886	}
	1887	}
	1888	break;
	1889	}
	1890	/////////////////////
[789]	1891	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
	1892	// handling coherence requests.
	1893	// if there is a matching pending miss, it is
	1894	// signaled in the r_icache_miss_inval flip-flop.
	1895	// The return state is defined in r_icache_fsm_save.
[331]	1896	{
[789]	1897	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
	1898	paddr_t mask = ~((m_icache_words << 2) - 1);
[331]	1899
[484]	1900	// CLACK handler
	1901	// We switch the directory slot to EMPTY state
	1902	// and reset r_icache_miss_clack if the cleanup ack
	1903	// is matching a pending miss.
[789]	1904	if (r_icache_clack_req.read())
[484]	1905	{
[331]	1906
[789]	1907	if (m_ireq.valid) m_cost_ins_miss_frz++;
[484]	1908
	1909	#ifdef INSTRUMENTATION
[789]	1910	m_cpt_icache_dir_write++;
[484]	1911	#endif
[789]	1912	r_icache.write_dir(0,
	1913	r_icache_clack_way.read(),
	1914	r_icache_clack_set.read(),
	1915	CACHE_SLOT_STATE_EMPTY);
[484]	1916
[789]	1917	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
	1918	(r_icache_miss_way.read() == r_icache_clack_way.read()))
[484]	1919	{
	1920	r_icache_miss_clack = false;
	1921	}
	1922
	1923	r_icache_clack_req = false;
	1924
	1925	// return to cc_save state
	1926	r_icache_fsm = r_icache_fsm_save.read();
	1927
	1928	#if DEBUG_ICACHE
[789]	1929	if (m_debug_icache_fsm)
	1930	{
	1931	std::cout << " <PROC " << name()
	1932	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
	1933	<< " set = " << r_icache_clack_set.read()
	1934	<< " / way = " << r_icache_clack_way.read() << std::endl;
	1935	}
[484]	1936	#endif
	1937
	1938	break;
	1939	}
	1940
[789]	1941	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
[487]	1942
[468]	1943	// Match between MISS address and CC address
	1944	if (r_cc_receive_icache_req.read() and
[789]	1945	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
	1946	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
[468]	1947	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
[789]	1948	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
[331]	1949	{
	1950	// signaling the matching
[789]	1951	r_icache_miss_inval = true;
[331]	1952
	1953	// in case of update, go to CC_UPDT
	1954	// JUST TO POP THE FIFO
	1955	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
	1956	{
[789]	1957	r_icache_fsm = ICACHE_CC_UPDT;
	1958	r_icache_cc_word = r_cc_receive_word_idx.read();
[468]	1959
[331]	1960	// just pop the fifo , don't write in icache
	1961	r_icache_cc_need_write = false;
	1962	}
	1963	// the request is dealt with
	1964	else
	1965	{
	1966	r_cc_receive_icache_req = false;
[789]	1967	r_icache_fsm = r_icache_fsm_save.read();
[331]	1968	}
	1969	#if DEBUG_ICACHE
[789]	1970	if (m_debug_icache_fsm)
	1971	{
	1972	std::cout << " <PROC " << name()
	1973	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
	1974	<< " PADDR = " << std::hex << paddr << std::endl;
	1975	}
[331]	1976	#endif
	1977	}
[468]	1978
	1979	// CC request handler
	1980
[789]	1981	int state = 0;
	1982	size_t way = 0;
	1983	size_t set = 0;
	1984	size_t word = 0;
[468]	1985
[331]	1986	#ifdef INSTRUMENTATION
[789]	1987	m_cpt_icache_dir_read++;
[331]	1988	#endif
[468]	1989	r_icache.read_dir(paddr,
	1990	&state,
	1991	&way,
	1992	&set,
	1993	&word);
	1994
	1995	r_icache_cc_way = way;
	1996	r_icache_cc_set = set;
	1997
[789]	1998	if (state == CACHE_SLOT_STATE_VALID) // hit
[331]	1999	{
[468]	2000	// need to update the cache state
	2001	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
	2002	{
	2003	r_icache_cc_need_write = true;
[789]	2004	r_icache_fsm = ICACHE_CC_UPDT;
	2005	r_icache_cc_word = r_cc_receive_word_idx.read();
[468]	2006	}
[789]	2007	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
[468]	2008	{
[789]	2009	r_icache_fsm = ICACHE_CC_INVAL;
[468]	2010	}
[331]	2011	}
[468]	2012	else // miss
[331]	2013	{
[468]	2014	// multicast acknowledgement required in case of update
[789]	2015	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
[468]	2016	{
[789]	2017	r_icache_fsm = ICACHE_CC_UPDT;
	2018	r_icache_cc_word = r_cc_receive_word_idx.read();
[331]	2019
[468]	2020	// just pop the fifo , don't write in icache
	2021	r_icache_cc_need_write = false;
	2022	}
	2023	else // No response needed
	2024	{
	2025	r_cc_receive_icache_req = false;
[789]	2026	r_icache_fsm = r_icache_fsm_save.read();
[468]	2027	}
[331]	2028	}
	2029	break;
	2030	}
[468]	2031	/////////////////////
[789]	2032	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
[331]	2033	{
[468]	2034	assert (not r_icache_cc_send_req.read() &&
	2035	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
	2036	"must not be set");
[331]	2037
[468]	2038	#ifdef INSTRUMENTATION
[789]	2039	m_cpt_icache_dir_read++;
[468]	2040	#endif
	2041
[816]	2042	// Switch slot state to ZOMBI and send CLEANUP command
[789]	2043	r_icache.write_dir(r_icache_cc_way.read(),
	2044	r_icache_cc_set.read(),
	2045	CACHE_SLOT_STATE_ZOMBI);
[468]	2046
	2047	// coherence request completed
	2048	r_icache_cc_send_req = true;
	2049	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
	2050	r_icache_cc_send_way = r_icache_cc_way.read();
	2051	r_icache_cc_send_type = CC_TYPE_CLEANUP;
	2052
[789]	2053	r_icache_fsm = r_icache_fsm_save.read();
[468]	2054
[331]	2055	#if DEBUG_ICACHE
[789]	2056	if (m_debug_icache_fsm)
	2057	{
	2058	std::cout << " <PROC " << name()
	2059	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
	2060	<< " set = " << r_icache_cc_set.read()
	2061	<< " / way = " << r_icache_cc_way.read() << std::endl;
	2062	}
[331]	2063	#endif
	2064
[468]	2065	break;
	2066	}
	2067	////////////////////
[789]	2068	case ICACHE_CC_UPDT: // hit update : write one word per cycle
[468]	2069	{
	2070	assert (not r_icache_cc_send_req.read() &&
	2071	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
	2072	"must not be set");
	2073
[789]	2074	if (not r_cc_receive_updt_fifo_be.rok()) break;
[468]	2075
	2076
[789]	2077	size_t word = r_icache_cc_word.read();
	2078	size_t way = r_icache_cc_way.read();
	2079	size_t set = r_icache_cc_set.read();
[331]	2080
[468]	2081	if (r_icache_cc_need_write.read())
[331]	2082	{
[789]	2083	r_icache.write(way,
	2084	set,
	2085	word,
	2086	r_cc_receive_updt_fifo_data.read(),
	2087	r_cc_receive_updt_fifo_be.read());
[331]	2088
[789]	2089	r_icache_cc_word = word + 1;
[331]	2090
[468]	2091	#ifdef INSTRUMENTATION
[789]	2092	m_cpt_icache_data_write++;
[468]	2093	#endif
[331]	2094
	2095	#if DEBUG_ICACHE
[789]	2096	if (m_debug_icache_fsm)
	2097	{
	2098	std::cout << " <PROC " << name()
	2099	<< " ICACHE_CC_UPDT> Write one word "
	2100	<< " set = " << r_icache_cc_set.read()
	2101	<< " / way = " << r_icache_cc_way.read()
	2102	<< " / word = " << r_icache_cc_word.read() << std::endl;
	2103	}
[331]	2104	#endif
[468]	2105	}
[331]	2106
[789]	2107	if (r_cc_receive_updt_fifo_eop.read()) // last word
[331]	2108	{
	2109	// no need to write in the cache anymore
[789]	2110	r_icache_cc_need_write = false;
[331]	2111
	2112	// coherence request completed
[789]	2113	r_cc_receive_icache_req = false;
[331]	2114
[468]	2115	// request multicast acknowledgement
	2116	r_icache_cc_send_req = true;
	2117	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
	2118	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
	2119	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
	2120
[789]	2121	r_icache_fsm = r_icache_fsm_save.read();
[331]	2122	}
[468]	2123	//consume fifo if not eop
[789]	2124	cc_receive_updt_fifo_get = true;
[468]	2125
[331]	2126	break;
	2127	}
[468]	2128
[331]	2129	} // end switch r_icache_fsm
	2130
	2131	////////////////////////////////////////////////////////////////////////////////////
	2132	// DCACHE FSM
	2133	//
	2134	// 1/ Coherence operations
	2135	// They are handled as interrupts generated by the CC_RECEIVE FSM.
	2136	// - There is a coherence request when r_tgt_dcache_req is set.
	2137	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
	2138	// and SC_WAIT states.
	2139	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
	2140	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
	2141	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
	2142	// - For both types of requests, actions associated to the pre-empted state
	2143	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
	2144	// or CC_CLACK) to execute the requested coherence operation, and returns
	2145	// to the pre-empted state.
	2146	//
	2147	// 2/ TLB miss
	2148	// The page tables are generally cacheable.
	2149	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
	2150	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
	2151	// this sub-fsm implement the table-walk...
	2152	//
	2153	// 3/ processor requests
	2154	// Processor requests are taken in IDLE state only.
	2155	// The IDLE state implements a two stages pipe-line to handle write bursts:
	2156	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
	2157	// - The registration in wbuf and the dcache update is done in stage P1
	2158	// (if the processor request is a write).
	2159	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
	2160	// the operations that must be done in P1 stage, and the access type
	2161	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
	2162	// READ requests are delayed if a cache update is requested.
	2163	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
	2164	// that is done (before handling the processor request) by a dedicated sub-fsm.
	2165	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
	2166	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
	2167	//
	2168	// 4/ Atomic instructions LL/SC
	2169	// The LL/SC address are non cacheable (systematic access to memory).
	2170	// The llsc buffer contains a registration for an active LL/SC operation
	2171	// (with an address, a registration key, an aging counter and a valid bit).
	2172	// - LL requests from the processor are transmitted as a one flit VCI command
	2173	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
	2174	// be 8 as the response is 2 flits long (data and registration key)
	2175	// - SC requests from the processor are systematically transmitted to the
	2176	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
	2177	// as PKTID value). The first flit contains the registration key, the second
	2178	// flit contains the data to write in case of success.
	2179	// The cache is not updated, as this is done in case of success by the
	2180	// coherence transaction.
	2181	//
	2182	// 5/ Non cacheable access:
	2183	// This component implement a strong order between non cacheable access
	2184	// (read or write) : A new non cacheable VCI transaction starts only when
[616]	2185	// the previous non cacheable transaction is completed. After send the VCI
	2186	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
	2187	// So the processor is blocked until the respone arrives in CACHE L1.
[331]	2188	//
	2189	// 6/ Error handling:
	2190	// When the MMU is not activated, Read Bus Errors are synchronous events,
[816]	2191	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
	2192	// but some Write Bus Errors are asynchronous events when the request is cacheable access
[616]	2193	// (processor is not frozen).
	2194	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
[331]	2195	// r_vci_rsp_data_error flip-flop, without writing any data in the
	2196	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
	2197	// by the DCACHE FSM.
[816]	2198	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
[616]	2199	// the asynchronous error using the setWriteBerr() method.
[331]	2200	// When the MMU is activated bus error are rare events, as the MMU
	2201	// checks the physical address before the VCI transaction starts.
	2202	////////////////////////////////////////////////////////////////////////////////////////
	2203
	2204	// default value for m_drsp
	2205	m_drsp.valid = false;
	2206	m_drsp.error = false;
	2207	m_drsp.rdata = 0;
	2208
[789]	2209	switch (r_dcache_fsm.read())
[331]	2210	{
	2211	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
	2212	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
	2213	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
	2214	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
	2215	// 4) XTN request (processor) => DCACHE_XTN_*
	2216	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
	2217	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
	2218	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
[816]	2219	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
[331]	2220	// 9) LL access (processor) => DCACHE_LL_WAIT
	2221	// 10) SC access (processor) => DCACHE_SC_WAIT
	2222	//
	2223	// There is a fixed priority to handle requests to DCACHE:
	2224	// 1/ the ITLB/DTLB invalidate requests
	2225	// 2/ the coherence requests,
	2226	// 3/ the processor requests (including DTLB miss),
	2227	// 4/ the ITLB miss requests,
	2228	// The address space processor request are handled as follows:
	2229	// - WRITE request is blocked if the Dirty bit mus be set.
	2230	// If DTLB hit, the P1 stage is activated (writes WBUF, and
	2231	// updates DCACHE if DCACHE hit) & processor request acknowledged.
	2232	// - READ request generate a simultaneouss access to DCACHE.DATA
	2233	// and DCACHE.DIR, but is delayed if DCACHE update required.
	2234	//
	2235	// There is 4 configurations defining the access type to
	2236	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
	2237	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
	2238	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
	2239	// 0 / 0 / NOP / NOP / NOP /
	2240	// 0 / 1 / NOP / NOP / WRITE /
	2241	// 1 / 0 / READ / READ / NOP /
	2242	// 1 / 1 / READ / READ / WRITE /
	2243	// Those two registers are set at each cycle from the 3 signals
	2244	// updt_request, wbuf_request, wbuf_write_miss.
	2245	{
[789]	2246	paddr_t paddr;
	2247	pte_info_t tlb_flags;
	2248	size_t tlb_way;
	2249	size_t tlb_set;
	2250	paddr_t tlb_nline = 0;
	2251	size_t cache_way;
	2252	size_t cache_set;
	2253	size_t cache_word;
	2254	uint32_t cache_rdata = 0;
	2255	bool tlb_hit = false;
	2256	int cache_state = CACHE_SLOT_STATE_EMPTY;
[331]	2257
[789]	2258	bool tlb_inval_required = false; // request TLB inval after cache update
	2259	bool wbuf_write_miss = false; // miss a WBUF write request
	2260	bool updt_request = false; // request DCACHE update in P1 stage
	2261	bool wbuf_request = false; // request WBUF write in P1 stage
[331]	2262
[789]	2263	// physical address computation : systematic DTLB access if activated
[752]	2264	paddr = (paddr_t) m_dreq.addr;
[789]	2265	if (m_dreq.valid)
[331]	2266	{
[789]	2267	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
[331]	2268	{
[789]	2269	tlb_hit = r_dtlb.translate(m_dreq.addr,
	2270	&paddr,
	2271	&tlb_flags,
	2272	&tlb_nline,
	2273	&tlb_way,
	2274	&tlb_set);
[331]	2275	#ifdef INSTRUMENTATION
[789]	2276	m_cpt_dtlb_read++;
[331]	2277	#endif
	2278	}
[789]	2279	else // identity mapping
[331]	2280	{
[394]	2281	// we take into account the paddr extension
[816]	2282	if (vci_param::N > 32)
[789]	2283	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
[331]	2284	}
	2285	} // end physical address computation
	2286
	2287	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
[789]	2288	if (r_mmu_mode.read() & DATA_CACHE_MASK)
[331]	2289	{
[752]	2290
[789]	2291	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
[331]	2292	{
[789]	2293	r_dcache.read_dir(paddr,
	2294	&cache_state,
	2295	&cache_way,
	2296	&cache_set,
	2297	&cache_word);
[331]	2298
[789]	2299	r_dcache.write(r_dcache_save_cache_way.read(),
	2300	r_dcache_save_cache_set.read(),
	2301	r_dcache_save_cache_word.read(),
	2302	r_dcache_save_wdata.read(),
	2303	r_dcache_save_be.read());
[331]	2304	#ifdef INSTRUMENTATION
[789]	2305	m_cpt_dcache_dir_read++;
	2306	m_cpt_dcache_data_write++;
[331]	2307	#endif
	2308	}
[789]	2309	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
[331]	2310	{
[789]	2311	r_dcache.read(paddr,
	2312	&cache_rdata,
	2313	&cache_way,
	2314	&cache_set,
	2315	&cache_word,
	2316	&cache_state);
[366]	2317
[331]	2318	#ifdef INSTRUMENTATION
[789]	2319	m_cpt_dcache_dir_read++;
	2320	m_cpt_dcache_data_read++;
[331]	2321	#endif
	2322	}
[789]	2323	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
[331]	2324	{
[789]	2325	r_dcache.write(r_dcache_save_cache_way.read(),
	2326	r_dcache_save_cache_set.read(),
	2327	r_dcache_save_cache_word.read(),
	2328	r_dcache_save_wdata.read(),
	2329	r_dcache_save_be.read());
[331]	2330	#ifdef INSTRUMENTATION
[789]	2331	m_cpt_dcache_data_write++;
[331]	2332	#endif
	2333	}
	2334	} // end dcache access
	2335
	2336	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
[789]	2337	if (r_dcache_updt_req.read())
[331]	2338	{
	2339	size_t way = r_dcache_save_cache_way.read();
	2340	size_t set = r_dcache_save_cache_set.read();
	2341
[789]	2342	if (r_dcache_in_tlb[way * m_dcache_sets + set])
[331]	2343	{
[789]	2344	tlb_inval_required = true;
	2345	r_dcache_tlb_inval_set = 0;
	2346	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
	2347	(uint32_log2(m_dcache_words << 2));
	2348	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[331]	2349	}
[789]	2350	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
[331]	2351	{
	2352	r_itlb.reset();
	2353	r_dtlb.reset();
[789]	2354	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	2355	}
	2356
	2357	#if DEBUG_DCACHE
[789]	2358	if (m_debug_dcache_fsm)
	2359	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2360	<< " Cache update in P1 stage" << std::dec
	2361	<< " / WAY = " << r_dcache_save_cache_way.read()
	2362	<< " / SET = " << r_dcache_save_cache_set.read()
	2363	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
	2364	<< " / WDATA = " << r_dcache_save_wdata.read()
	2365	<< " / BE = " << r_dcache_save_be.read() << std::endl;
[331]	2366	#endif
	2367	} // end test TLB inval
	2368
	2369	// Try WBUF update in P1 stage
	2370	// Miss if the write request is non cacheable, and there is a pending
	2371	// non cacheable write, or if the write buffer is full.
[789]	2372	if (r_dcache_wbuf_req.read())
[331]	2373	{
[789]	2374	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
	2375	r_dcache_save_be.read(),
	2376	r_dcache_save_wdata.read(),
	2377	true);
[331]	2378	#ifdef INSTRUMENTATION
[789]	2379	m_cpt_wbuf_write++;
[331]	2380	#endif
[789]	2381	if (not wok ) // miss if write buffer full
[616]	2382	{
	2383	wbuf_write_miss = true;
[331]	2384	}
	2385	} // end WBUF update
	2386
	2387	// Computing the response to processor,
	2388	// and the next value for r_dcache_fsm
	2389
	2390	// itlb/dtlb invalidation self-request
[789]	2391	if (tlb_inval_required)
[331]	2392	{
	2393	r_dcache_fsm_scan_save = r_dcache_fsm.read();
	2394	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
	2395	}
	2396
[468]	2397	// coherence clack request (from DSPIN CLACK)
[789]	2398	else if (r_dcache_clack_req.read())
[468]	2399	{
	2400	r_dcache_fsm = DCACHE_CC_CHECK;
	2401	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	2402	}
[331]	2403	// coherence request (from CC_RECEIVE FSM)
[789]	2404	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	2405	{
	2406	r_dcache_fsm = DCACHE_CC_CHECK;
	2407	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	2408	}
	2409
	2410	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
	2411	// we don't take the processor request, and registers
	2412	// are frozen in case of wbuf_write_miss
[789]	2413	else if (m_dreq.valid and not wbuf_write_miss)
[331]	2414	{
	2415	// register processor request and DCACHE response
	2416	r_dcache_save_vaddr = m_dreq.addr;
	2417	r_dcache_save_be = m_dreq.be;
	2418	r_dcache_save_wdata = m_dreq.wdata;
	2419	r_dcache_save_paddr = paddr;
	2420	r_dcache_save_cache_way = cache_way;
	2421	r_dcache_save_cache_set = cache_set;
	2422	r_dcache_save_cache_word = cache_word;
	2423
	2424	// READ XTN requests from processor
	2425	// They are executed in this DCACHE_IDLE state.
	2426	// The processor must not be in user mode
	2427	if (m_dreq.type == iss_t::XTN_READ)
	2428	{
[836]	2429	int xtn_opcode = (int) m_dreq.addr / 4;
[331]	2430
	2431	// checking processor mode:
	2432	if (m_dreq.mode == iss_t::MODE_USER)
	2433	{
	2434	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
	2435	r_mmu_dbvar = m_dreq.addr;
	2436	m_drsp.valid = true;
	2437	m_drsp.error = true;
	2438	m_drsp.rdata = 0;
	2439	r_dcache_fsm = DCACHE_IDLE;
	2440	}
	2441	else
	2442	{
[789]	2443	switch (xtn_opcode)
[331]	2444	{
	2445	case iss_t::XTN_INS_ERROR_TYPE:
	2446	m_drsp.rdata = r_mmu_ietr.read();
	2447	m_drsp.valid = true;
	2448	m_drsp.error = false;
	2449	break;
	2450
	2451	case iss_t::XTN_DATA_ERROR_TYPE:
	2452	m_drsp.rdata = r_mmu_detr.read();
	2453	m_drsp.valid = true;
	2454	m_drsp.error = false;
	2455	break;
	2456
	2457	case iss_t::XTN_INS_BAD_VADDR:
	2458	m_drsp.rdata = r_mmu_ibvar.read();
	2459	m_drsp.valid = true;
	2460	m_drsp.error = false;
	2461	break;
	2462
	2463	case iss_t::XTN_DATA_BAD_VADDR:
	2464	m_drsp.rdata = r_mmu_dbvar.read();
	2465	m_drsp.valid = true;
	2466	m_drsp.error = false;
	2467	break;
	2468
	2469	case iss_t::XTN_PTPR:
	2470	m_drsp.rdata = r_mmu_ptpr.read();
	2471	m_drsp.valid = true;
	2472	m_drsp.error = false;
	2473	break;
	2474
	2475	case iss_t::XTN_TLB_MODE:
	2476	m_drsp.rdata = r_mmu_mode.read();
	2477	m_drsp.valid = true;
	2478	m_drsp.error = false;
	2479	break;
	2480
	2481	case iss_t::XTN_MMU_PARAMS:
	2482	m_drsp.rdata = r_mmu_params;
	2483	m_drsp.valid = true;
	2484	m_drsp.error = false;
	2485	break;
	2486
	2487	case iss_t::XTN_MMU_RELEASE:
	2488	m_drsp.rdata = r_mmu_release;
	2489	m_drsp.valid = true;
	2490	m_drsp.error = false;
	2491	break;
	2492
	2493	case iss_t::XTN_MMU_WORD_LO:
	2494	m_drsp.rdata = r_mmu_word_lo.read();
	2495	m_drsp.valid = true;
	2496	m_drsp.error = false;
	2497	break;
	2498
	2499	case iss_t::XTN_MMU_WORD_HI:
	2500	m_drsp.rdata = r_mmu_word_hi.read();
	2501	m_drsp.valid = true;
	2502	m_drsp.error = false;
	2503	break;
	2504
[394]	2505	case iss_t::XTN_DATA_PADDR_EXT:
	2506	m_drsp.rdata = r_dcache_paddr_ext.read();
	2507	m_drsp.valid = true;
	2508	m_drsp.error = false;
	2509	break;
	2510
[721]	2511	case iss_t::XTN_INST_PADDR_EXT:
	2512	m_drsp.rdata = r_icache_paddr_ext.read();
	2513	m_drsp.valid = true;
	2514	m_drsp.error = false;
	2515	break;
	2516
[331]	2517	default:
[789]	2518	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
[331]	2519	r_mmu_dbvar = m_dreq.addr;
	2520	m_drsp.valid = true;
	2521	m_drsp.error = true;
	2522	m_drsp.rdata = 0;
	2523	break;
	2524	} // end switch xtn_opcode
	2525	} // end else
	2526	} // end if XTN_READ
	2527
	2528	// Handling WRITE XTN requests from processor.
	2529	// They are not executed in this DCACHE_IDLE state
	2530	// if they require access to the caches or the TLBs
	2531	// that are already accessed.
	2532	// Caches can be invalidated or flushed in user mode,
	2533	// and the sync instruction can be executed in user mode
	2534	else if (m_dreq.type == iss_t::XTN_WRITE)
	2535	{
[789]	2536	int xtn_opcode = (int)m_dreq.addr / 4;
[331]	2537	r_dcache_xtn_opcode = xtn_opcode;
	2538
	2539	// checking processor mode:
[789]	2540	if ((m_dreq.mode == iss_t::MODE_USER) &&
[366]	2541	(xtn_opcode != iss_t::XTN_SYNC) &&
[331]	2542	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
	2543	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
	2544	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
[789]	2545	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
[331]	2546	{
	2547	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
	2548	r_mmu_dbvar = m_dreq.addr;
	2549	m_drsp.valid = true;
	2550	m_drsp.error = true;
	2551	m_drsp.rdata = 0;
	2552	r_dcache_fsm = DCACHE_IDLE;
	2553	}
	2554	else
	2555	{
[789]	2556	switch (xtn_opcode)
[331]	2557	{
[789]	2558	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
[331]	2559	r_dcache_xtn_req = true;
	2560	r_dcache_fsm = DCACHE_XTN_SWITCH;
	2561	break;
	2562
[789]	2563	case iss_t::XTN_TLB_MODE: // no cache or tlb access
	2564	r_mmu_mode = m_dreq.wdata;
	2565	m_drsp.valid = true;
	2566	r_dcache_fsm = DCACHE_IDLE;
[331]	2567	break;
	2568
[789]	2569	case iss_t::XTN_DTLB_INVAL: // dtlb access
	2570	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
[331]	2571	break;
	2572
[789]	2573	case iss_t::XTN_ITLB_INVAL: // itlb access
[331]	2574	r_dcache_xtn_req = true;
	2575	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
	2576	break;
	2577
[789]	2578	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
	2579	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
[331]	2580	break;
	2581
[789]	2582	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
[970]	2583	{
	2584	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
	2585	((uint64_t)r_mmu_word_lo.read());
	2586
	2587	r_dcache_save_paddr = (paddr_t)pa;
[789]	2588	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
[331]	2589	break;
[970]	2590	}
[789]	2591	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
[331]	2592	r_dcache_flush_count = 0;
[789]	2593	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
[331]	2594	break;
	2595
[789]	2596	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
[331]	2597	r_dcache_xtn_req = true;
	2598	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
	2599	break;
	2600
[789]	2601	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
[331]	2602	r_dcache_xtn_req = true;
	2603	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
	2604	break;
	2605
[789]	2606	case iss_t::XTN_ICACHE_FLUSH: // icache access
[331]	2607	r_dcache_xtn_req = true;
	2608	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
	2609	break;
	2610
[789]	2611	case iss_t::XTN_SYNC: // wait until write buffer empty
	2612	r_dcache_fsm = DCACHE_XTN_SYNC;
[331]	2613	break;
	2614
[789]	2615	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
	2616	r_mmu_word_lo = m_dreq.wdata;
	2617	m_drsp.valid = true;
	2618	r_dcache_fsm = DCACHE_IDLE;
[331]	2619	break;
	2620
[789]	2621	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
	2622	r_mmu_word_hi = m_dreq.wdata;
	2623	m_drsp.valid = true;
	2624	r_dcache_fsm = DCACHE_IDLE;
[331]	2625	break;
	2626
[789]	2627	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
[331]	2628	r_dcache_llsc_valid = false;
[789]	2629	m_drsp.valid = true;
	2630	r_dcache_fsm = DCACHE_IDLE;
[331]	2631	break;
	2632
[789]	2633	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
[394]	2634	r_dcache_paddr_ext = m_dreq.wdata;
	2635	m_drsp.valid = true;
	2636	r_dcache_fsm = DCACHE_IDLE;
	2637	break;
	2638
[789]	2639	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
[721]	2640	r_dcache_xtn_req = true;
	2641	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
	2642	break;
	2643
[789]	2644	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
	2645	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
	2646	m_drsp.valid = true;
	2647	r_dcache_fsm = DCACHE_IDLE;
[721]	2648	break;
[331]	2649
[668]	2650	case iss_t::XTN_DEBUG_MASK: // debug mask
	2651	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
	2652	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
	2653	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
	2654	m_drsp.valid = true;
	2655	r_dcache_fsm = DCACHE_IDLE;
	2656	break;
	2657
[331]	2658	default:
	2659	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
	2660	r_mmu_dbvar = m_dreq.addr;
	2661	m_drsp.valid = true;
	2662	m_drsp.error = true;
	2663	r_dcache_fsm = DCACHE_IDLE;
	2664	break;
	2665	} // end switch xtn_opcode
	2666	} // end else
	2667	} // end if XTN_WRITE
	2668
	2669	// Handling processor requests to address space (READ/WRITE/LL/SC)
	2670	// The dtlb and dcache can be activated or not.
	2671	// We compute the cacheability, and check processor request validity:
	2672	// - If DTLB not activated : cacheability is defined by the segment table,
	2673	// and there is no access rights checking.
	2674	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
	2675	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
	2676	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
	2677	else
	2678	{
[789]	2679	bool valid_req;
	2680	bool cacheable;
[331]	2681
[789]	2682	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
[331]	2683	{
[789]	2684	valid_req = true;
[331]	2685
[789]	2686	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
[549]	2687	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
[331]	2688	}
[789]	2689	else // dtlb activated
[331]	2690	{
[789]	2691	if (tlb_hit) // tlb hit
[331]	2692	{
	2693	// cacheability
[789]	2694	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
[331]	2695	else cacheable = tlb_flags.c;
	2696
	2697	// access rights checking
[789]	2698	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
[331]	2699	{
[789]	2700	if ((m_dreq.type == iss_t::DATA_READ) or
	2701	(m_dreq.type == iss_t::DATA_LL))
[331]	2702	{
	2703	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
	2704	}
	2705	else
	2706	{
	2707	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
	2708	}
	2709	valid_req = false;
	2710	r_mmu_dbvar = m_dreq.addr;
	2711	m_drsp.valid = true;
	2712	m_drsp.error = true;
	2713	m_drsp.rdata = 0;
	2714	#if DEBUG_DCACHE
[789]	2715	if (m_debug_dcache_fsm)
	2716	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2717	<< " HIT in dtlb, but privilege violation" << std::endl;
[331]	2718	#endif
	2719	}
[789]	2720	else if (not tlb_flags.w and
[331]	2721	((m_dreq.type == iss_t::DATA_WRITE) or
[789]	2722	(m_dreq.type == iss_t::DATA_SC)))
[331]	2723	{
	2724	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
	2725	valid_req = false;
	2726	r_mmu_dbvar = m_dreq.addr;
	2727	m_drsp.valid = true;
	2728	m_drsp.error = true;
	2729	m_drsp.rdata = 0;
	2730	#if DEBUG_DCACHE
[789]	2731	if (m_debug_dcache_fsm)
	2732	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2733	<< " HIT in dtlb, but writable violation" << std::endl;
[331]	2734	#endif
	2735	}
	2736	else
	2737	{
[789]	2738	valid_req = true;
[331]	2739	}
	2740	}
[789]	2741	else // tlb miss
[331]	2742	{
[789]	2743	valid_req = false;
	2744	r_dcache_tlb_vaddr = m_dreq.addr;
	2745	r_dcache_tlb_ins = false;
	2746	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	2747	}
	2748	} // end DTLB activated
	2749
[789]	2750	if (valid_req) // processor request is valid (after MMU check)
[331]	2751	{
	2752	// READ request
	2753	// The read requests are taken only if there is no cache update.
	2754	// We request a VCI transaction to CMD FSM if miss or uncachable
[366]	2755
[789]	2756	if (((m_dreq.type == iss_t::DATA_READ))
	2757	and not r_dcache_updt_req.read())
[331]	2758	{
[789]	2759	if (cacheable) // cacheable read
[331]	2760	{
[789]	2761	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
[331]	2762	{
	2763	#ifdef INSTRUMENTATION
[789]	2764	m_cpt_dcache_miss++;
[331]	2765	#endif
	2766	// request a VCI DMISS transaction
	2767	r_dcache_vci_paddr = paddr;
	2768	r_dcache_vci_miss_req = true;
	2769	r_dcache_miss_type = PROC_MISS;
	2770	r_dcache_fsm = DCACHE_MISS_SELECT;
	2771	#if DEBUG_DCACHE
[789]	2772	if (m_debug_dcache_fsm)
	2773	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
[816]	2774	<< " READ MISS in dcache"
[789]	2775	<< " / PADDR = " << std::hex << paddr << std::endl;
[331]	2776	#endif
	2777	}
[789]	2778	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
[331]	2779	{
	2780	// stalled until cleanup is acknowledged
	2781	r_dcache_fsm = DCACHE_IDLE;
[394]	2782	#if DEBUG_DCACHE
[789]	2783	if (m_debug_dcache_fsm)
	2784	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2785	<< " Pending cleanup, stalled until cleanup acknowledge"
	2786	<< " / PADDR = " << std::hex << paddr << std::endl;
[394]	2787	#endif
[331]	2788	}
	2789	else // cache hit
	2790	{
	2791	#ifdef INSTRUMENTATION
[789]	2792	m_cpt_data_read++;
[331]	2793	#endif
	2794	// returns data to processor
[789]	2795	m_drsp.valid = true;
	2796	m_drsp.error = false;
	2797	m_drsp.rdata = cache_rdata;
[331]	2798	#if DEBUG_DCACHE
[789]	2799	if (m_debug_dcache_fsm)
	2800	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
[816]	2801	<< " READ HIT in dcache"
	2802	<< " : PADDR = " << std::hex << paddr
[789]	2803	<< " / DATA = " << std::hex << cache_rdata << std::endl;
[331]	2804	#endif
	2805	}
	2806	}
[789]	2807	else // uncacheable read
[331]	2808	{
[789]	2809	r_dcache_vci_paddr = paddr;
	2810	r_dcache_vci_unc_be = m_dreq.be;
	2811	r_dcache_vci_unc_write = false;
	2812	r_dcache_vci_unc_req = true;
	2813	r_dcache_fsm = DCACHE_UNC_WAIT;
[331]	2814	#if DEBUG_DCACHE
[789]	2815	if (m_debug_dcache_fsm)
	2816	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
[816]	2817	<< " READ UNCACHEABLE in dcache"
[789]	2818	<< " / PADDR = " << std::hex << paddr << std::endl;
[331]	2819	#endif
	2820	}
	2821	} // end READ
	2822
	2823	// LL request (non cachable)
	2824	// We request a VCI LL transaction to CMD FSM and register
	2825	// the LL/SC operation in llsc buffer.
	2826	else if (m_dreq.type == iss_t::DATA_LL)
	2827	{
	2828	// register paddr in LLSC buffer
	2829	r_dcache_llsc_paddr = paddr;
	2830	r_dcache_llsc_count = LLSC_TIMEOUT;
	2831	r_dcache_llsc_valid = true;
	2832
	2833	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
	2834	r_dcache_vci_ll_req = true;
	2835	r_dcache_vci_paddr = paddr;
	2836	r_dcache_ll_rsp_count = 0;
	2837	r_dcache_fsm = DCACHE_LL_WAIT;
	2838
	2839	}// end LL
	2840
	2841	// WRITE request:
	2842	// If the TLB is activated and the PTE Dirty bit is not set, we stall
	2843	// the processor and set the Dirty bit before handling the write request,
	2844	// going to the DCACHE_DIRTY_GT_PTE state.
	2845	// If we don't need to set the Dirty bit, we can acknowledge
	2846	// the processor request, as the write arguments (including the
	2847	// physical address) are registered in r_dcache_save registers,
	2848	// and the write will be done in the P1 pipeline stage.
[789]	2849	else if (m_dreq.type == iss_t::DATA_WRITE)
[331]	2850	{
[789]	2851	if ((r_mmu_mode.read() & DATA_TLB_MASK)
	2852	and not tlb_flags.d) // Dirty bit must be set
[331]	2853	{
	2854	// The PTE physical address is obtained from the nline value (dtlb),
	2855	// and from the virtual address (word index)
[789]	2856	if (tlb_flags.b ) // PTE1
[331]	2857	{
[789]	2858	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
	2859	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
[331]	2860	}
[789]	2861	else // PTE2
[331]	2862	{
[789]	2863	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
	2864	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
[331]	2865	}
[789]	2866	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
[331]	2867	}
[789]	2868	else // Write request accepted
[331]	2869	{
	2870	#ifdef INSTRUMENTATION
[789]	2871	m_cpt_data_write++;
[331]	2872	#endif
	2873	// cleaning llsc buffer if address matching
[789]	2874	if (paddr == r_dcache_llsc_paddr.read())
[331]	2875	r_dcache_llsc_valid = false;
	2876
[816]	2877	if (not cacheable) // uncacheable write
	2878	{
[789]	2879	r_dcache_vci_paddr = paddr;
	2880	r_dcache_vci_wdata = m_dreq.wdata;
	2881	r_dcache_vci_unc_write = true;
	2882	r_dcache_vci_unc_be = m_dreq.be;
	2883	r_dcache_vci_unc_req = true;
	2884	r_dcache_fsm = DCACHE_UNC_WAIT;
[892]	2885
	2886	#if DEBUG_DCACHE
	2887	if (m_debug_dcache_fsm)
	2888	{
	2889	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2890	<< " Request WRITE UNCACHEABLE" << std::hex
	2891	<< " / VADDR = " << m_dreq.addr
	2892	<< " / PADDR = " << paddr
	2893	<< std::dec << std::endl;
	2894	}
	2895	#endif
[616]	2896	}
	2897	else
	2898	{
	2899	// response to processor
[789]	2900	m_drsp.valid = true;
[616]	2901	// activating P1 stage
	2902	wbuf_request = true;
	2903	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
[892]	2904
	2905	#if DEBUG_DCACHE
	2906	if (m_debug_dcache_fsm)
	2907	{
	2908	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
	2909	<< " Request WBUF WRITE" << std::hex
	2910	<< " / VADDR = " << m_dreq.addr
	2911	<< " / PADDR = " << paddr
	2912	<< std::dec << std::endl;
	2913	}
	2914	#endif
[616]	2915	}
[331]	2916	}
	2917	} // end WRITE
	2918
	2919	// SC request:
	2920	// If the TLB is activated and the PTE Dirty bit is not set, we stall
	2921	// the processor and set the Dirty bit before handling the write request,
	2922	// going to the DCACHE_DIRTY_GT_PTE state.
	2923	// If we don't need to set the Dirty bit, we test the llsc buffer:
	2924	// If failure, we send a negative response to processor.
	2925	// If success, we request a SC transaction to CMD FSM and go
	2926	// to DCACHE_SC_WAIT state.
	2927	// We don't check a possible write hit in dcache, as the cache update
	2928	// is done by the coherence transaction induced by the SC...
[789]	2929	else if (m_dreq.type == iss_t::DATA_SC)
[331]	2930	{
[789]	2931	if ((r_mmu_mode.read() & DATA_TLB_MASK)
	2932	and not tlb_flags.d) // Dirty bit must be set
[331]	2933	{
	2934	// The PTE physical address is obtained from the nline value (dtlb),
	2935	// and the word index (virtual address)
[789]	2936	if (tlb_flags.b) // PTE1
[331]	2937	{
[789]	2938	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
	2939	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
[331]	2940	}
[789]	2941	else // PTE2
[331]	2942	{
[789]	2943	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
	2944	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
[331]	2945	}
[789]	2946	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
[331]	2947	m_drsp.valid = false;
	2948	m_drsp.error = false;
	2949	m_drsp.rdata = 0;
	2950	}
[789]	2951	else // SC request accepted
[331]	2952	{
	2953	#ifdef INSTRUMENTATION
[789]	2954	m_cpt_data_sc++;
[331]	2955	#endif
	2956	// checking local success
[789]	2957	if (r_dcache_llsc_valid.read() and
	2958	(r_dcache_llsc_paddr.read() == paddr)) // local success
[331]	2959	{
	2960	// request an SC CMD and go to DCACHE_SC_WAIT state
	2961	r_dcache_vci_paddr = paddr;
	2962	r_dcache_vci_sc_req = true;
	2963	r_dcache_vci_sc_data = m_dreq.wdata;
	2964	r_dcache_fsm = DCACHE_SC_WAIT;
	2965	}
[789]	2966	else // local fail
[331]	2967	{
[789]	2968	m_drsp.valid = true;
	2969	m_drsp.error = false;
	2970	m_drsp.rdata = 0x1;
[331]	2971	}
	2972	}
	2973	} // end SC
	2974	} // end valid_req
	2975	} // end if read/write/ll/sc request
	2976	} // end processor request
	2977
	2978	// itlb miss request
[836]	2979	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
[331]	2980	{
	2981	r_dcache_tlb_ins = true;
	2982	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
	2983	r_dcache_fsm = DCACHE_TLB_MISS;
	2984	}
	2985
	2986	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
	2987	r_dcache_updt_req = updt_request;
	2988	r_dcache_wbuf_req = wbuf_request or
	2989	(r_dcache_wbuf_req.read() and wbuf_write_miss);
	2990	break;
	2991	}
	2992	/////////////////////
	2993	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
	2994	// Input arguments are:
	2995	// - r_dcache_tlb_vaddr
	2996	// - r_dcache_tlb_ins (true when itlb miss)
	2997	// The sub-fsm access the dcache to find the missing TLB entry,
	2998	// and activates the cache miss procedure in case of miss.
	2999	// It bypass the first level page table access if possible.
	3000	// It uses atomic access to update the R/L access bits
	3001	// in the page table if required.
	3002	// It directly updates the itlb or dtlb, and writes into the
	3003	// r_mmu_ins_* or r_mmu_data* error reporting registers.
	3004	{
[789]	3005	uint32_t ptba = 0;
	3006	bool bypass;
	3007	paddr_t pte_paddr;
[331]	3008
	3009	// evaluate bypass in order to skip first level page table access
[789]	3010	if (r_dcache_tlb_ins.read()) // itlb miss
[331]	3011	{
	3012	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
	3013	}
[789]	3014	else // dtlb miss
[331]	3015	{
	3016	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
	3017	}
	3018
[789]	3019	if (not bypass) // Try to read PTE1/PTD1 in dcache
[331]	3020	{
[789]	3021	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
	3022	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
[331]	3023	r_dcache_tlb_paddr = pte_paddr;
	3024	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
	3025	}
[789]	3026	else // Try to read PTE2 in dcache
[331]	3027	{
[789]	3028	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
	3029	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
[331]	3030	r_dcache_tlb_paddr = pte_paddr;
	3031	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
	3032	}
	3033
	3034	#if DEBUG_DCACHE
[789]	3035	if (m_debug_dcache_fsm)
	3036	{
	3037	if (r_dcache_tlb_ins.read())
	3038	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
	3039	else
	3040	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
	3041	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
	3042	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
	3043	<< " / BYPASS = " << bypass
	3044	<< " / PTE_ADR = " << pte_paddr << std::endl;
	3045	}
[331]	3046	#endif
	3047
	3048	break;
	3049	}
	3050	/////////////////////////
[789]	3051	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
[331]	3052	{
[468]	3053	// coherence clack request (from DSPIN CLACK)
[789]	3054	if (r_dcache_clack_req.read())
[468]	3055	{
	3056	r_dcache_fsm = DCACHE_CC_CHECK;
	3057	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3058	break;
	3059	}
	3060
[341]	3061	// coherence request (from CC_RECEIVE FSM)
[789]	3062	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[341]	3063	{
	3064	r_dcache_fsm = DCACHE_CC_CHECK;
	3065	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3066	break;
	3067	}
	3068
[789]	3069	uint32_t entry;
	3070	size_t way;
	3071	size_t set;
	3072	size_t word;
	3073	int cache_state;
	3074	r_dcache.read(r_dcache_tlb_paddr.read(),
	3075	&entry,
	3076	&way,
	3077	&set,
	3078	&word,
	3079	&cache_state);
[331]	3080	#ifdef INSTRUMENTATION
[789]	3081	m_cpt_dcache_data_read++;
	3082	m_cpt_dcache_dir_read++;
[331]	3083	#endif
[789]	3084	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
[331]	3085	{
[789]	3086	if (not (entry & PTE_V_MASK)) // unmapped
[331]	3087	{
[789]	3088	if (r_dcache_tlb_ins.read())
[331]	3089	{
	3090	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
	3091	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	3092	r_icache_tlb_miss_req = false;
	3093	r_icache_tlb_rsp_error = true;
	3094	}
	3095	else
	3096	{
[789]	3097	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
	3098	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	3099	m_drsp.valid = true;
	3100	m_drsp.error = true;
[331]	3101	}
[789]	3102	r_dcache_fsm = DCACHE_IDLE;
[331]	3103
	3104	#if DEBUG_DCACHE
[789]	3105	if (m_debug_dcache_fsm)
	3106	{
[816]	3107	std::cout << " <PROC " << name()
[789]	3108	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
	3109	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
	3110	<< std::dec << " / way = " << way
	3111	<< std::dec << " / set = " << set
	3112	<< std::dec << " / word = " << word
	3113	<< std::hex << " / PTE1 = " << entry << std::endl;
	3114	}
[331]	3115	#endif
	3116
	3117	}
[836]	3118	else if (entry & PTE_T_MASK) // PTD : me must access PT2
[331]	3119	{
	3120	// mark the cache line ac containing a PTD
[789]	3121	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
[331]	3122
	3123	// register bypass
[789]	3124	if (r_dcache_tlb_ins.read()) // itlb
[331]	3125	{
	3126	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
	3127	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
[789]	3128	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
[331]	3129	}
[789]	3130	else // dtlb
[331]	3131	{
	3132	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
	3133	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
[789]	3134	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
[331]	3135	}
	3136	r_dcache_tlb_paddr =
[789]	3137	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
[331]	3138	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
[789]	3139	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
[331]	3140
	3141	#if DEBUG_DCACHE
[789]	3142	if (m_debug_dcache_fsm)
	3143	{
[816]	3144	std::cout << " <PROC " << name()
[789]	3145	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
	3146	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
	3147	<< std::dec << " / way = " << way
	3148	<< std::dec << " / set = " << set
	3149	<< std::dec << " / word = " << word
	3150	<< std::hex << " / PTD = " << entry << std::endl;
	3151	}
[331]	3152	#endif
	3153	}
[789]	3154	else // PTE1 : we must update the TLB
[331]	3155	{
[789]	3156	r_dcache_in_tlb[m_icache_sets * way + set] = true;
[331]	3157	r_dcache_tlb_pte_flags = entry;
	3158	r_dcache_tlb_cache_way = way;
	3159	r_dcache_tlb_cache_set = set;
	3160	r_dcache_tlb_cache_word = word;
	3161	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
	3162
	3163	#if DEBUG_DCACHE
[789]	3164	if (m_debug_dcache_fsm)
	3165	{
[816]	3166	std::cout << " <PROC " << name()
[789]	3167	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
	3168	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
	3169	<< std::dec << " / way = " << way
	3170	<< std::dec << " / set = " << set
	3171	<< std::dec << " / word = " << word
	3172	<< std::hex << " / PTE1 = " << entry << std::endl;
	3173	}
[331]	3174	#endif
	3175	}
	3176	}
[789]	3177	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
[338]	3178	{
	3179	// stalled until cleanup is acknowledged
[789]	3180	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
[338]	3181	}
[789]	3182	else // we must load the missing cache line in dcache
[331]	3183	{
[789]	3184	r_dcache_vci_miss_req = true;
	3185	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
	3186	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
	3187	r_dcache_miss_type = PTE1_MISS;
	3188	r_dcache_fsm = DCACHE_MISS_SELECT;
[331]	3189
	3190	#if DEBUG_DCACHE
[789]	3191	if (m_debug_dcache_fsm)
	3192	{
[816]	3193	std::cout << " <PROC " << name()
[789]	3194	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
	3195	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
	3196	}
[331]	3197	#endif
	3198	}
	3199	break;
	3200	}
	3201	////////////////////////////
[789]	3202	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
[331]	3203	{
[789]	3204	size_t way;
	3205	size_t set;
[331]	3206
[789]	3207	if (r_dcache_tlb_ins.read())
[331]	3208	{
[789]	3209	r_itlb.select(r_dcache_tlb_vaddr.read(),
	3210	true, // PTE1
	3211	&way,
	3212	&set);
[331]	3213	#ifdef INSTRUMENTATION
[789]	3214	m_cpt_itlb_read++;
[331]	3215	#endif
	3216	}
	3217	else
	3218	{
[789]	3219	r_dtlb.select(r_dcache_tlb_vaddr.read(),
	3220	true, // PTE1
	3221	&way,
	3222	&set);
[331]	3223	#ifdef INSTRUMENTATION
[789]	3224	m_cpt_dtlb_read++;
[331]	3225	#endif
	3226	}
	3227	r_dcache_tlb_way = way;
	3228	r_dcache_tlb_set = set;
	3229	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
	3230
	3231	#if DEBUG_DCACHE
[789]	3232	if (m_debug_dcache_fsm)
	3233	{
	3234	if (r_dcache_tlb_ins.read())
[816]	3235	std::cout << " <PROC " << name()
[789]	3236	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
	3237	else
[816]	3238	std::cout << " <PROC " << name()
[789]	3239	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
	3240	std::cout << " way = " << std::dec << way
	3241	<< " / set = " << set << std::endl;
	3242	}
[331]	3243	#endif
	3244	break;
	3245	}
	3246	//////////////////////////
[789]	3247	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
[331]	3248	// - if L/R bit already set, exit the sub-fsm.
	3249	// - if not, we update the page table but we dont write
	3250	// neither in DCACHE, nor in TLB, as this will be done by
	3251	// the coherence mechanism.
	3252	{
[789]	3253	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
	3254	uint32_t pte = r_dcache_tlb_pte_flags.read();
	3255	bool pt_updt = false;
	3256	bool local = true;
[331]	3257
	3258	// We should compute the access locality:
	3259	// The PPN MSB bits define the destination cluster index.
[346]	3260	// The m_srcid MSB bits define the source cluster index.
[331]	3261	// The number of bits to compare depends on the number of clusters,
	3262	// and can be obtained in the mapping table.
	3263	// As long as this computation is not done, all access are local.
	3264
[789]	3265	if (local) // local access
[331]	3266	{
[789]	3267	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
[331]	3268	{
	3269	pt_updt = true;
[789]	3270	r_dcache_vci_cas_old = pte;
	3271	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
[331]	3272	pte = pte \| PTE_L_MASK;
	3273	r_dcache_tlb_pte_flags = pte;
	3274	}
	3275	}
[789]	3276	else // remote access
[331]	3277	{
[789]	3278	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
[331]	3279	{
	3280	pt_updt = true;
[789]	3281	r_dcache_vci_cas_old = pte;
	3282	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
[331]	3283	pte = pte \| PTE_R_MASK;
	3284	r_dcache_tlb_pte_flags = pte;
	3285	}
	3286	}
	3287
[789]	3288	if (not pt_updt) // update TLB and return
[331]	3289	{
[789]	3290	if (r_dcache_tlb_ins.read())
[331]	3291	{
[789]	3292	r_itlb.write(true, // 2M page
	3293	pte,
	3294	0, // argument unused for a PTE1
	3295	r_dcache_tlb_vaddr.read(),
	3296	r_dcache_tlb_way.read(),
	3297	r_dcache_tlb_set.read(),
	3298	nline);
[331]	3299	#ifdef INSTRUMENTATION
[789]	3300	m_cpt_itlb_write++;
[331]	3301	#endif
	3302
	3303	#if DEBUG_DCACHE
[789]	3304	if (m_debug_dcache_fsm)
	3305	{
[816]	3306	std::cout << " <PROC " << name()
[789]	3307	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
	3308	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3309	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3310	r_itlb.printTrace();
	3311	}
[331]	3312	#endif
	3313	}
	3314	else
	3315	{
[789]	3316	r_dtlb.write(true, // 2M page
	3317	pte,
	3318	0, // argument unused for a PTE1
	3319	r_dcache_tlb_vaddr.read(),
	3320	r_dcache_tlb_way.read(),
	3321	r_dcache_tlb_set.read(),
	3322	nline);
[331]	3323	#ifdef INSTRUMENTATION
[789]	3324	m_cpt_dtlb_write++;
[331]	3325	#endif
	3326
	3327	#if DEBUG_DCACHE
[789]	3328	if (m_debug_dcache_fsm)
	3329	{
[816]	3330	std::cout << " <PROC " << name()
[789]	3331	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
	3332	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3333	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3334	r_dtlb.printTrace();
	3335	}
[331]	3336	#endif
	3337	}
	3338	r_dcache_fsm = DCACHE_TLB_RETURN;
	3339	}
	3340	else // update page table but not TLB
	3341	{
	3342	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
	3343
	3344	#if DEBUG_DCACHE
[789]	3345	if (m_debug_dcache_fsm)
	3346	{
[816]	3347	std::cout << " <PROC " << name()
[789]	3348	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
	3349	<< std::endl;
	3350	}
[331]	3351	#endif
	3352	}
	3353	break;
	3354	}
	3355	/////////////////////////
[789]	3356	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
[331]	3357	{
[468]	3358	// coherence clack request (from DSPIN CLACK)
[789]	3359	if (r_dcache_clack_req.read())
[468]	3360	{
	3361	r_dcache_fsm = DCACHE_CC_CHECK;
	3362	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3363	break;
	3364	}
	3365
[341]	3366	// coherence request (from CC_RECEIVE FSM)
[789]	3367	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[341]	3368	{
	3369	r_dcache_fsm = DCACHE_CC_CHECK;
	3370	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3371	break;
	3372	}
	3373
[789]	3374	uint32_t pte_flags;
	3375	uint32_t pte_ppn;
	3376	size_t way;
	3377	size_t set;
	3378	size_t word;
	3379	int cache_state;
[331]	3380
[789]	3381	r_dcache.read(r_dcache_tlb_paddr.read(),
	3382	&pte_flags,
	3383	&pte_ppn,
	3384	&way,
	3385	&set,
	3386	&word,
	3387	&cache_state);
[331]	3388	#ifdef INSTRUMENTATION
[789]	3389	m_cpt_dcache_data_read++;
	3390	m_cpt_dcache_dir_read++;
[331]	3391	#endif
[789]	3392	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
[331]	3393	{
[789]	3394	if (not (pte_flags & PTE_V_MASK)) // unmapped
[331]	3395	{
[789]	3396	if (r_dcache_tlb_ins.read())
[331]	3397	{
	3398	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
	3399	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	3400	r_icache_tlb_miss_req = false;
	3401	r_icache_tlb_rsp_error = true;
	3402	}
	3403	else
	3404	{
[789]	3405	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
	3406	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	3407	m_drsp.valid = true;
	3408	m_drsp.error = true;
[331]	3409	}
[789]	3410	r_dcache_fsm = DCACHE_IDLE;
[331]	3411
	3412	#if DEBUG_DCACHE
[789]	3413	if (m_debug_dcache_fsm)
	3414	{
	3415	std::cout << " <PROC " << name()
	3416	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
	3417	<< " PTE_FLAGS = " << std::hex << pte_flags
	3418	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
	3419	}
[331]	3420	#endif
	3421	}
[789]	3422	else // mapped : we must update the TLB
[331]	3423	{
[789]	3424	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
[331]	3425	r_dcache_tlb_pte_flags = pte_flags;
	3426	r_dcache_tlb_pte_ppn = pte_ppn;
	3427	r_dcache_tlb_cache_way = way;
	3428	r_dcache_tlb_cache_set = set;
	3429	r_dcache_tlb_cache_word = word;
	3430	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
	3431
	3432	#if DEBUG_DCACHE
[789]	3433	if (m_debug_dcache_fsm)
	3434	{
[816]	3435	std::cout << " <PROC " << name()
[789]	3436	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
	3437	<< " PTE_FLAGS = " << std::hex << pte_flags
	3438	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
	3439	}
[331]	3440	#endif
	3441	}
	3442	}
[789]	3443	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
[338]	3444	{
	3445	// stalled until cleanup is acknowledged
	3446	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
[386]	3447
	3448	#if DEBUG_DCACHE
[789]	3449	if (m_debug_dcache_fsm)
	3450	{
[816]	3451	std::cout << " <PROC " << name()
[789]	3452	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
	3453	<< std::endl;
	3454	}
[386]	3455	#endif
[338]	3456	}
[331]	3457	else // we must load the missing cache line in dcache
	3458	{
	3459	r_dcache_fsm = DCACHE_MISS_SELECT;
	3460	r_dcache_vci_miss_req = true;
	3461	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
	3462	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
	3463	r_dcache_miss_type = PTE2_MISS;
	3464
	3465	#if DEBUG_DCACHE
[789]	3466	if (m_debug_dcache_fsm)
	3467	{
	3468	std::cout << " <PROC " << name()
	3469	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
	3470	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
	3471	}
[331]	3472	#endif
	3473	}
	3474	break;
	3475	}
	3476	////////////////////////////
	3477	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
	3478	{
	3479	size_t way;
	3480	size_t set;
	3481
[789]	3482	if (r_dcache_tlb_ins.read())
[331]	3483	{
[789]	3484	r_itlb.select(r_dcache_tlb_vaddr.read(),
	3485	false, // PTE2
	3486	&way,
	3487	&set);
[331]	3488	#ifdef INSTRUMENTATION
[789]	3489	m_cpt_itlb_read++;
[331]	3490	#endif
	3491	}
	3492	else
	3493	{
[789]	3494	r_dtlb.select(r_dcache_tlb_vaddr.read(),
	3495	false, // PTE2
	3496	&way,
	3497	&set);
[331]	3498	#ifdef INSTRUMENTATION
[789]	3499	m_cpt_dtlb_read++;
[331]	3500	#endif
	3501	}
	3502
	3503	#if DEBUG_DCACHE
[789]	3504	if (m_debug_dcache_fsm)
	3505	{
	3506	if (r_dcache_tlb_ins.read())
	3507	std::cout << " <PROC " << name()
	3508	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
	3509	else
	3510	std::cout << " <PROC " << name()
	3511	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
	3512	std::cout << " way = " << std::dec << way
	3513	<< " / set = " << set << std::endl;
	3514	}
[331]	3515	#endif
	3516	r_dcache_tlb_way = way;
	3517	r_dcache_tlb_set = set;
	3518	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
	3519	break;
	3520	}
	3521	//////////////////////////
[789]	3522	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
[331]	3523	// - if L/R bit already set, exit the sub-fsm.
	3524	// - if not, we update the page table but we dont write
	3525	// neither in DCACHE, nor in TLB, as this will be done by
	3526	// the coherence mechanism.
	3527	{
[789]	3528	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
	3529	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
	3530	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
	3531	bool pt_updt = false;
	3532	bool local = true;
[331]	3533
	3534	// We should compute the access locality:
	3535	// The PPN MSB bits define the destination cluster index.
[346]	3536	// The m_srcid MSB bits define the source cluster index.
[331]	3537	// The number of bits to compare depends on the number of clusters,
	3538	// and can be obtained in the mapping table.
	3539	// As long as this computation is not done, all access are local.
	3540
[789]	3541	if (local) // local access
[331]	3542	{
[789]	3543	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
[331]	3544	{
	3545	pt_updt = true;
[355]	3546	r_dcache_vci_cas_old = pte_flags;
	3547	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
[331]	3548	pte_flags = pte_flags \| PTE_L_MASK;
[789]	3549	r_dcache_tlb_pte_flags = pte_flags;
[331]	3550	}
	3551	}
	3552	else // remote access
	3553	{
[789]	3554	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
[331]	3555	{
	3556	pt_updt = true;
[355]	3557	r_dcache_vci_cas_old = pte_flags;
	3558	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
[331]	3559	pte_flags = pte_flags \| PTE_R_MASK;
[789]	3560	r_dcache_tlb_pte_flags = pte_flags;
[331]	3561	}
	3562	}
	3563
[789]	3564	if (not pt_updt) // update TLB
[331]	3565	{
[789]	3566	if (r_dcache_tlb_ins.read())
[331]	3567	{
[789]	3568	r_itlb.write( false, // 4K page
[331]	3569	pte_flags,
	3570	pte_ppn,
	3571	r_dcache_tlb_vaddr.read(),
	3572	r_dcache_tlb_way.read(),
	3573	r_dcache_tlb_set.read(),
	3574	nline );
	3575	#ifdef INSTRUMENTATION
[789]	3576	m_cpt_itlb_write++;
[331]	3577	#endif
	3578
	3579	#if DEBUG_DCACHE
[789]	3580	if (m_debug_dcache_fsm)
	3581	{
	3582	std::cout << " <PROC " << name()
	3583	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
	3584	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3585	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3586	r_itlb.printTrace();
	3587	}
[331]	3588	#endif
	3589	}
	3590	else
	3591	{
[789]	3592	r_dtlb.write(false, // 4K page
	3593	pte_flags,
	3594	pte_ppn,
	3595	r_dcache_tlb_vaddr.read(),
	3596	r_dcache_tlb_way.read(),
	3597	r_dcache_tlb_set.read(),
	3598	nline);
[331]	3599	#ifdef INSTRUMENTATION
[789]	3600	m_cpt_dtlb_write++;
[331]	3601	#endif
	3602
	3603	#if DEBUG_DCACHE
[789]	3604	if (m_debug_dcache_fsm)
	3605	{
	3606	std::cout << " <PROC " << name()
	3607	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
	3608	<< " / set = " << std::dec << r_dcache_tlb_set.read()
	3609	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
	3610	r_dtlb.printTrace();
	3611	}
[331]	3612	#endif
	3613
	3614	}
	3615	r_dcache_fsm = DCACHE_TLB_RETURN;
	3616	}
	3617	else // update page table but not TLB
	3618	{
[789]	3619	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
[331]	3620
	3621	#if DEBUG_DCACHE
[789]	3622	if (m_debug_dcache_fsm)
	3623	{
	3624	std::cout << " <PROC " << name()
	3625	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
	3626	}
[331]	3627	#endif
	3628	}
	3629	break;
	3630	}
	3631	////////////////////////
	3632	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
	3633	{
	3634	#if DEBUG_DCACHE
[789]	3635	if (m_debug_dcache_fsm)
	3636	{
	3637	std::cout << " <PROC " << name()
	3638	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
	3639	}
[331]	3640	#endif
	3641	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
	3642	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
	3643
	3644	// checking llsc reservation buffer
[789]	3645	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
[331]	3646	r_dcache_llsc_valid = false;
	3647
	3648	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
	3649	r_dcache_vci_cas_req = true;
[789]	3650	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
[331]	3651	break;
	3652	}
	3653	////////////////////////
[789]	3654	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
[331]	3655	// We consume the response in rsp FIFO,
	3656	// and exit the sub-fsm, but we don't
	3657	// analyse the response, because we don't
	3658	// care if the L/R bit update is not done.
	3659	// We must take the coherence requests because
	3660	// there is a risk of dead-lock
	3661
	3662	{
[468]	3663	// coherence clack request (from DSPIN CLACK)
[789]	3664	if (r_dcache_clack_req.read())
[468]	3665	{
	3666	r_dcache_fsm = DCACHE_CC_CHECK;
	3667	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3668	break;
	3669	}
	3670
[331]	3671	// coherence request (from CC_RECEIVE FSM)
[789]	3672	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	3673	{
	3674	r_dcache_fsm = DCACHE_CC_CHECK;
	3675	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3676	break;
	3677	}
	3678
[789]	3679	if (r_vci_rsp_data_error.read()) // bus error
[331]	3680	{
	3681	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
	3682	std::cout << "This should not happen in this state" << std::endl;
	3683	exit(0);
	3684	}
[789]	3685	else if (r_vci_rsp_fifo_dcache.rok()) // response available
[506]	3686	{
[331]	3687	#if DEBUG_DCACHE
[789]	3688	if (m_debug_dcache_fsm)
	3689	{
	3690	std::cout << " <PROC " << name()
	3691	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
	3692	}
[331]	3693	#endif
	3694	vci_rsp_fifo_dcache_get = true;
[789]	3695	r_dcache_fsm = DCACHE_TLB_RETURN;
[331]	3696	}
	3697	break;
	3698	}
	3699	///////////////////////
[789]	3700	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
[331]	3701	{
	3702	#if DEBUG_DCACHE
[789]	3703	if (m_debug_dcache_fsm)
	3704	{
	3705	std::cout << " <PROC " << name()
	3706	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
	3707	}
[331]	3708	#endif
[789]	3709	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
[331]	3710	r_dcache_fsm = DCACHE_IDLE;
	3711	break;
	3712	}
	3713	///////////////////////
[789]	3714	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
[331]	3715	// and both itlb and dtlb must be flushed.
	3716	// Caution : the itlb miss requests must be taken
	3717	// to avoid dead-lock in case of simultaneous ITLB miss
[521]	3718	// Caution : the clack and cc requests must be taken
	3719	// to avoid dead-lock
[331]	3720	{
[521]	3721	// coherence clack request (from DSPIN CLACK)
[789]	3722	if (r_dcache_clack_req.read())
[521]	3723	{
	3724	r_dcache_fsm = DCACHE_CC_CHECK;
	3725	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3726	break;
	3727	}
	3728
	3729	// coherence request (from CC_RECEIVE FSM)
[789]	3730	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[521]	3731	{
	3732	r_dcache_fsm = DCACHE_CC_CHECK;
	3733	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3734	break;
	3735	}
	3736
[331]	3737	// itlb miss request
[789]	3738	if (r_icache_tlb_miss_req.read())
[331]	3739	{
[789]	3740	r_dcache_tlb_ins = true;
	3741	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
	3742	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	3743	break;
	3744	}
	3745
[789]	3746	if (not r_dcache_xtn_req.read())
[331]	3747	{
	3748	r_dtlb.flush();
	3749	r_mmu_ptpr = m_dreq.wdata;
	3750	r_dcache_fsm = DCACHE_IDLE;
	3751	m_drsp.valid = true;
	3752	}
	3753	break;
	3754	}
	3755	/////////////////////
[789]	3756	case DCACHE_XTN_SYNC: // waiting until write buffer empty
	3757	// The coherence request must be taken
	3758	// as there is a risk of dead-lock
[331]	3759	{
[468]	3760	// coherence clack request (from DSPIN CLACK)
[789]	3761	if (r_dcache_clack_req.read())
[468]	3762	{
	3763	r_dcache_fsm = DCACHE_CC_CHECK;
	3764	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3765	break;
	3766	}
	3767
[331]	3768	// coherence request (from CC_RECEIVE FSM)
[789]	3769	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	3770	{
	3771	r_dcache_fsm = DCACHE_CC_CHECK;
	3772	r_dcache_fsm_cc_save = r_dcache_fsm.read();
[468]	3773	break;
[331]	3774	}
	3775
[789]	3776	if (r_wbuf.empty())
[331]	3777	{
[789]	3778	m_drsp.valid = true;
[331]	3779	r_dcache_fsm = DCACHE_IDLE;
	3780	}
	3781	break;
	3782	}
	3783	////////////////////////
[721]	3784	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
	3785	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
	3786	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
	3787	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
	3788	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
	3789
[331]	3790	{
[468]	3791	// coherence clack request (from DSPIN CLACK)
[789]	3792	if (r_dcache_clack_req.read())
[468]	3793	{
	3794	r_dcache_fsm = DCACHE_CC_CHECK;
	3795	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3796	break;
	3797	}
	3798
[331]	3799	// coherence request (from CC_RECEIVE FSM)
[789]	3800	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	3801	{
	3802	r_dcache_fsm = DCACHE_CC_CHECK;
	3803	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3804	break;
	3805	}
	3806
	3807	// itlb miss request
[789]	3808	if (r_icache_tlb_miss_req.read())
[331]	3809	{
[789]	3810	r_dcache_tlb_ins = true;
	3811	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
	3812	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	3813	break;
	3814	}
	3815
	3816	// test if XTN request to icache completed
[789]	3817	if (not r_dcache_xtn_req.read())
[331]	3818	{
	3819	r_dcache_fsm = DCACHE_IDLE;
	3820	m_drsp.valid = true;
	3821	}
	3822	break;
	3823	}
	3824	/////////////////////////
[789]	3825	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
[331]	3826	// r_dcache_flush_count as a slot counter,
	3827	// looping in this state until all slots have been visited.
	3828	// It can require two cycles per slot:
	3829	// We test here the slot state, and make the actual inval
	3830	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
	3831	// A cleanup request is generated for each valid line.
	3832	// returns to IDLE and flush TLBs when last slot
	3833	{
[468]	3834	// coherence clack request (from DSPIN CLACK)
[789]	3835	if (r_dcache_clack_req.read())
[468]	3836	{
	3837	r_dcache_fsm = DCACHE_CC_CHECK;
	3838	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3839	break;
	3840	}
	3841
[384]	3842	// coherence request (from CC_RECEIVE FSM)
[789]	3843	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[384]	3844	{
	3845	r_dcache_fsm = DCACHE_CC_CHECK;
	3846	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	3847	break;
	3848	}
	3849
[789]	3850	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
[331]	3851	{
[789]	3852	int state;
	3853	paddr_t tag;
[836]	3854	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
	3855	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
[331]	3856
	3857	#ifdef INSTRUMENTATION
[789]	3858	m_cpt_dcache_dir_read++;
[331]	3859	#endif
[789]	3860	r_dcache.read_dir(way,
	3861	set,
	3862	&tag,
	3863	&state);
[331]	3864
[789]	3865	if (state == CACHE_SLOT_STATE_VALID) // inval required
[331]	3866	{
	3867	// request cleanup
	3868	r_dcache_cc_send_req = true;
[384]	3869	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
[331]	3870	r_dcache_cc_send_way = way;
	3871	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	3872
	3873	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
[789]	3874	r_dcache_miss_way = way;
	3875	r_dcache_miss_set = set;
	3876	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
[331]	3877	}
[789]	3878	else if (r_dcache_flush_count.read() ==
	3879	(m_dcache_sets*m_dcache_ways - 1)) // last slot
[331]	3880	{
	3881	r_dtlb.reset();
	3882	r_itlb.reset();
	3883	r_dcache_fsm = DCACHE_IDLE;
	3884	m_drsp.valid = true;
	3885	}
	3886
	3887	// saturation counter
[789]	3888	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
[331]	3889	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
	3890	}
	3891	break;
	3892	}
	3893	////////////////////////////
	3894	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
	3895	// and reset directory extension.
	3896	// returns to IDLE and flush TLBs when last slot
	3897	{
	3898	size_t way = r_dcache_miss_way.read();
	3899	size_t set = r_dcache_miss_set.read();
	3900
[789]	3901	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
	3902	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
[331]	3903
	3904	#ifdef INSTRUMENTATION
[789]	3905	m_cpt_dcache_dir_write++;
[331]	3906	#endif
[789]	3907	r_dcache.write_dir(way,
	3908	set,
	3909	CACHE_SLOT_STATE_ZOMBI);
[331]	3910
[789]	3911	if (r_dcache_flush_count.read() ==
	3912	(m_dcache_sets*m_dcache_ways - 1)) // last slot
[331]	3913	{
	3914	r_dtlb.reset();
	3915	r_itlb.reset();
	3916	r_dcache_fsm = DCACHE_IDLE;
	3917	m_drsp.valid = true;
	3918	}
	3919	else
	3920	{
	3921	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
	3922	}
	3923	break;
	3924	}
	3925	/////////////////////////
[789]	3926	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
[331]	3927	{
	3928	r_dtlb.inval(r_dcache_save_wdata.read());
[789]	3929	r_dcache_fsm = DCACHE_IDLE;
	3930	m_drsp.valid = true;
[331]	3931	break;
	3932	}
	3933	////////////////////////////
	3934	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
	3935	// requires 3 cycles: access tlb, read cache, inval cache
[789]	3936	// we compute the physical address in this state
[331]	3937	{
	3938	paddr_t paddr;
[789]	3939	bool hit;
[331]	3940
[789]	3941	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
[331]	3942	{
	3943
	3944	#ifdef INSTRUMENTATION
[789]	3945	m_cpt_dtlb_read++;
[331]	3946	#endif
[789]	3947	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
	3948	&paddr);
[331]	3949	}
[789]	3950	else // dtlb not activated
[331]	3951	{
	3952	paddr = (paddr_t)r_dcache_save_wdata.read();
[816]	3953	if (vci_param::N > 32)
[487]	3954	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
[789]	3955	hit = true;
[331]	3956	}
	3957
[789]	3958	if (hit) // tlb hit
[331]	3959	{
	3960	r_dcache_save_paddr = paddr;
[789]	3961	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
[331]	3962	}
[789]	3963	else // tlb miss
	3964	{
[331]	3965
	3966	#ifdef INSTRUMENTATION
[789]	3967	m_cpt_dtlb_miss++;
[331]	3968	#endif
[789]	3969	r_dcache_tlb_ins = false; // dtlb
	3970	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
	3971	r_dcache_fsm = DCACHE_TLB_MISS;
[331]	3972	}
	3973
	3974	#if DEBUG_DCACHE
[789]	3975	if (m_debug_dcache_fsm)
	3976	{
	3977	std::cout << " <PROC " << name()
	3978	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
	3979	<< " / VADDR = " << r_dcache_save_wdata.read()
	3980	<< " / PADDR = " << paddr << std::endl;
	3981	}
[331]	3982	#endif
	3983
	3984	break;
	3985	}
	3986	////////////////////////////
	3987	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
	3988	// requires 2 cycles: read cache / inval cache
	3989	// In this state we read dcache.
	3990	{
[789]	3991	size_t way;
	3992	size_t set;
	3993	size_t word;
	3994	int state;
[331]	3995
	3996	#ifdef INSTRUMENTATION
[789]	3997	m_cpt_dcache_dir_read++;
[331]	3998	#endif
[789]	3999	r_dcache.read_dir(r_dcache_save_paddr.read(),
	4000	&state,
	4001	&way,
	4002	&set,
	4003	&word);
[331]	4004
[789]	4005	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
[331]	4006	{
	4007	r_dcache_xtn_way = way;
	4008	r_dcache_xtn_set = set;
[789]	4009	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
[331]	4010	}
[789]	4011	else // miss : nothing to do
[331]	4012	{
[789]	4013	r_dcache_fsm = DCACHE_IDLE;
	4014	m_drsp.valid = true;
[331]	4015	}
	4016
	4017	#if DEBUG_DCACHE
[789]	4018	if (m_debug_dcache_fsm)
	4019	{
	4020	std::cout << " <PROC " << name()
	4021	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
	4022	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
	4023	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
	4024	<< " / SET = " << set
	4025	<< " / WAY = " << way << std::endl;
	4026	}
[331]	4027	#endif
	4028	break;
	4029	}
	4030	////////////////////////////
	4031	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
[789]	4032	// Blocked if previous cleanup not completed
[331]	4033	// Test if itlb or dtlb inval is required
	4034	{
[789]	4035	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
[331]	4036	{
[789]	4037	size_t way = r_dcache_xtn_way.read();
	4038	size_t set = r_dcache_xtn_set.read();
	4039	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
[331]	4040
	4041	#ifdef INSTRUMENTATION
[789]	4042	m_cpt_dcache_dir_write++;
[331]	4043	#endif
[789]	4044	r_dcache.write_dir(way,
	4045	set,
	4046	CACHE_SLOT_STATE_ZOMBI);
[331]	4047
	4048	// request cleanup
	4049	r_dcache_cc_send_req = true;
	4050	r_dcache_cc_send_nline = nline;
	4051	r_dcache_cc_send_way = way;
	4052	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	4053
	4054	// possible itlb & dtlb invalidate
[789]	4055	if (r_dcache_in_tlb[way * m_dcache_sets + set])
[331]	4056	{
	4057	r_dcache_tlb_inval_line = nline;
	4058	r_dcache_tlb_inval_set = 0;
	4059	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
	4060	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[789]	4061	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[331]	4062	}
[789]	4063	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
[331]	4064	{
	4065	r_itlb.reset();
	4066	r_dtlb.reset();
[789]	4067	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	4068	r_dcache_fsm = DCACHE_IDLE;
	4069	m_drsp.valid = true;
	4070	}
	4071	else
	4072	{
	4073	r_dcache_fsm = DCACHE_IDLE;
	4074	m_drsp.valid = true;
	4075	}
	4076
	4077	#if DEBUG_DCACHE
[789]	4078	if (m_debug_dcache_fsm)
	4079	{
	4080	std::cout << " <PROC " << name()
	4081	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
	4082	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
	4083	}
[331]	4084	#endif
[789]	4085	}
[331]	4086	break;
	4087	}
	4088	//////////////////////////////
[789]	4089	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
[331]	4090	{
	4091	r_dcache_fsm = DCACHE_IDLE;
	4092	m_drsp.valid = true;
	4093	break;
	4094	}
	4095	////////////////////////
[487]	4096	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
	4097	// Waiting in this state if no slot available.
[816]	4098	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
	4099	// we send the cleanup request in this state.
[487]	4100	// If not, a r_icache_cleanup_victim_req flip-flop is
	4101	// utilized for saving this cleanup request, and it will be sent later
[816]	4102	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
[487]	4103	// The r_icache_miss_clack flip-flop is set
	4104	// when a cleanup is required
[331]	4105	{
[789]	4106	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4107
[468]	4108	// coherence clack request (from DSPIN CLACK)
[789]	4109	if (r_dcache_clack_req.read())
[468]	4110	{
	4111	r_dcache_fsm = DCACHE_CC_CHECK;
	4112	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4113	break;
	4114	}
	4115
[331]	4116	// coherence request (from CC_RECEIVE FSM)
[789]	4117	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4118	{
	4119	r_dcache_fsm = DCACHE_CC_CHECK;
	4120	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4121	break;
	4122	}
	4123
[789]	4124	bool found = false;
	4125	bool cleanup = false;
	4126	size_t way = 0;
	4127	size_t set = 0;
	4128	paddr_t victim = 0;
[331]	4129
	4130	#ifdef INSTRUMENTATION
[789]	4131	m_cpt_dcache_dir_read++;
[331]	4132	#endif
[789]	4133	r_dcache.read_select(r_dcache_save_paddr.read(),
	4134	&victim,
	4135	&way,
	4136	&set,
	4137	&found,
	4138	&cleanup);
[355]	4139
[789]	4140	if (not found)
[487]	4141	{
	4142	break;
	4143	}
	4144	else
	4145	{
	4146	r_dcache_miss_way = way;
	4147	r_dcache_miss_set = set;
	4148
[789]	4149	if (cleanup)
[331]	4150	{
[789]	4151	if (not r_dcache_cc_send_req.read())
[487]	4152	{
[789]	4153	r_dcache_cc_send_req = true;
	4154	r_dcache_cc_send_nline = victim;
	4155	r_dcache_cc_send_way = way;
[816]	4156	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
[331]	4157
	4158	}
	4159	else
	4160	{
[487]	4161	r_dcache_cleanup_victim_req = true;
	4162	r_dcache_cleanup_victim_nline = victim;
[331]	4163	}
	4164
[789]	4165	r_dcache_miss_clack = true;
	4166	r_dcache_fsm = DCACHE_MISS_CLEAN;
[487]	4167	}
	4168	else
	4169	{
[789]	4170	r_dcache_fsm = DCACHE_MISS_WAIT;
[487]	4171	}
	4172
[331]	4173	#if DEBUG_DCACHE
[789]	4174	if (m_debug_dcache_fsm)
	4175	{
	4176	std::cout << " <PROC " << name()
	4177	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
	4178	<< " / WAY = " << way
	4179	<< " / SET = " << set
	4180	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
	4181	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
	4182	else std::cout << std::endl;
	4183	}
[331]	4184	#endif
[487]	4185	} // end found
[331]	4186	break;
	4187	}
	4188	///////////////////////
[789]	4189	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
[331]	4190	// and possibly request itlb or dtlb invalidate
	4191	{
[789]	4192	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4193
[789]	4194	size_t way = r_dcache_miss_way.read();
	4195	size_t set = r_dcache_miss_set.read();
[331]	4196
	4197	#ifdef INSTRUMENTATION
[789]	4198	m_cpt_dcache_dir_read++;
[331]	4199	#endif
[789]	4200	r_dcache.write_dir(way,
	4201	set,
	4202	CACHE_SLOT_STATE_ZOMBI);
[331]	4203	#if DEBUG_DCACHE
[789]	4204	if (m_debug_dcache_fsm)
	4205	{
	4206	std::cout << " <PROC " << name()
	4207	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
	4208	<< " / way = " << way
	4209	<< " / set = " << set << std::endl;
	4210	}
[331]	4211	#endif
	4212	// if selective itlb & dtlb invalidate are required
	4213	// the miss response is not handled before invalidate completed
[789]	4214	if (r_dcache_in_tlb[way * m_dcache_sets + set])
[331]	4215	{
[789]	4216	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[532]	4217
[789]	4218	if (not r_dcache_cleanup_victim_req.read())
	4219	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
[532]	4220	else
	4221	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
	4222
[789]	4223	r_dcache_tlb_inval_set = 0;
	4224	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
	4225	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[331]	4226	}
[789]	4227	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
[331]	4228	{
	4229	r_itlb.reset();
	4230	r_dtlb.reset();
[789]	4231	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	4232	r_dcache_fsm = DCACHE_MISS_WAIT;
	4233	}
	4234	else
	4235	{
	4236	r_dcache_fsm = DCACHE_MISS_WAIT;
	4237	}
	4238	break;
	4239	}
	4240	//////////////////////
[789]	4241	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
[331]	4242	// This state is in charge of error signaling
	4243	// There is 5 types of error depending on the requester
	4244	{
[789]	4245	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4246
[487]	4247	// send cleanup victim request
[789]	4248	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
[487]	4249	{
	4250	r_dcache_cc_send_req = true;
	4251	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
	4252	r_dcache_cc_send_way = r_dcache_miss_way;
[816]	4253	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
[487]	4254	r_dcache_cleanup_victim_req = false;
[816]	4255	}
[487]	4256
[488]	4257	// coherence clack request (from DSPIN CLACK)
[789]	4258	if (r_dcache_clack_req.read())
[488]	4259	{
	4260	r_dcache_fsm = DCACHE_CC_CHECK;
	4261	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4262	break;
	4263	}
	4264
[331]	4265	// coherence request (from CC_RECEIVE FSM)
[816]	4266	if (r_cc_receive_dcache_req.read() and
	4267	not r_dcache_cc_send_req.read() and
[711]	4268	not r_dcache_cleanup_victim_req.read())
[331]	4269	{
	4270	r_dcache_fsm = DCACHE_CC_CHECK;
	4271	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4272	break;
	4273	}
	4274
[789]	4275	if (r_vci_rsp_data_error.read()) // bus error
[331]	4276	{
[789]	4277	switch (r_dcache_miss_type.read())
[331]	4278	{
	4279	case PROC_MISS:
	4280	{
[789]	4281	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
	4282	r_mmu_dbvar = r_dcache_save_vaddr.read();
	4283	m_drsp.valid = true;
	4284	m_drsp.error = true;
	4285	r_dcache_fsm = DCACHE_IDLE;
[331]	4286	break;
	4287	}
	4288	case PTE1_MISS:
	4289	{
[789]	4290	if (r_dcache_tlb_ins.read())
[331]	4291	{
[789]	4292	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
	4293	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	4294	r_icache_tlb_miss_req = false;
	4295	r_icache_tlb_rsp_error = true;
[331]	4296	}
	4297	else
	4298	{
[789]	4299	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
	4300	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	4301	m_drsp.valid = true;
	4302	m_drsp.error = true;
[331]	4303	}
[789]	4304	r_dcache_fsm = DCACHE_IDLE;
[331]	4305	break;
	4306	}
	4307	case PTE2_MISS:
	4308	{
[789]	4309	if (r_dcache_tlb_ins.read())
[331]	4310	{
[789]	4311	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
	4312	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
	4313	r_icache_tlb_miss_req = false;
	4314	r_icache_tlb_rsp_error = true;
[331]	4315	}
	4316	else
	4317	{
[789]	4318	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
	4319	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
	4320	m_drsp.valid = true;
	4321	m_drsp.error = true;
[331]	4322	}
[789]	4323	r_dcache_fsm = DCACHE_IDLE;
[331]	4324	break;
	4325	}
	4326	} // end switch type
	4327	r_vci_rsp_data_error = false;
	4328	}
[789]	4329	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
[331]	4330	{
	4331	r_dcache_miss_word = 0;
[789]	4332	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
[331]	4333	}
	4334	break;
	4335	}
	4336	//////////////////////////
[789]	4337	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
[331]	4338	{
[789]	4339	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4340
[789]	4341	if (r_vci_rsp_fifo_dcache.rok()) // one word available
[331]	4342	{
	4343	#ifdef INSTRUMENTATION
[789]	4344	m_cpt_dcache_data_write++;
[331]	4345	#endif
[789]	4346	r_dcache.write(r_dcache_miss_way.read(),
	4347	r_dcache_miss_set.read(),
	4348	r_dcache_miss_word.read(),
	4349	r_vci_rsp_fifo_dcache.read());
[331]	4350	#if DEBUG_DCACHE
[789]	4351	if (m_debug_dcache_fsm)
	4352	{
	4353	std::cout << " <PROC " << name()
	4354	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
	4355	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
	4356	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
	4357	<< " / SET = " << r_dcache_miss_set.read()
	4358	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
	4359	}
[331]	4360	#endif
	4361	vci_rsp_fifo_dcache_get = true;
	4362	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
	4363
[789]	4364	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
[331]	4365	{
	4366	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
	4367	}
	4368	}
	4369	break;
	4370	}
	4371	//////////////////////////
	4372	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
	4373	// and the cleanup ack has not been received,
	4374	// as indicated by the r_dcache_miss clack.
	4375	// - If no matching coherence request (r_dcache_inval_miss)
	4376	// switch directory slot to VALID state.
	4377	// - If matching coherence request, switch directory slot
	4378	// to ZOMBI state, and send a cleanup request.
	4379	{
[789]	4380	if (m_dreq.valid) m_cost_data_miss_frz++;
[331]	4381
[487]	4382	// send cleanup victim request
[789]	4383	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
[487]	4384	{
	4385	r_dcache_cc_send_req = true;
	4386	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
	4387	r_dcache_cc_send_way = r_dcache_miss_way;
[816]	4388	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
[487]	4389	r_dcache_cleanup_victim_req = false;
[816]	4390	}
[487]	4391
[488]	4392	// coherence clack request (from DSPIN CLACK)
[789]	4393	if (r_dcache_clack_req.read())
[488]	4394	{
	4395	r_dcache_fsm = DCACHE_CC_CHECK;
	4396	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4397	break;
	4398	}
	4399
[331]	4400	// coherence request (from CC_RECEIVE FSM)
[816]	4401	if (r_cc_receive_dcache_req.read() and
	4402	not r_dcache_cc_send_req.read() and
[789]	4403	not r_dcache_cleanup_victim_req.read())
[331]	4404	{
	4405	r_dcache_fsm = DCACHE_CC_CHECK;
	4406	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4407	break;
	4408	}
	4409
[789]	4410	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
[331]	4411	{
[789]	4412	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
[331]	4413	{
[789]	4414	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
[331]	4415	{
	4416	r_dcache_miss_inval = false;
	4417	// request cleanup
	4418	r_dcache_cc_send_req = true;
[789]	4419	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
[331]	4420	r_dcache_cc_send_way = r_dcache_miss_way.read();
	4421	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	4422
	4423	#ifdef INSTRUMENTATION
[789]	4424	m_cpt_dcache_dir_write++;
[331]	4425	#endif
	4426	r_dcache.write_dir( r_dcache_save_paddr.read(),
	4427	r_dcache_miss_way.read(),
	4428	r_dcache_miss_set.read(),
	4429	CACHE_SLOT_STATE_ZOMBI );
	4430	#if DEBUG_DCACHE
[789]	4431	if (m_debug_dcache_fsm)
	4432	std::cout << " <PROC " << name()
	4433	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
	4434	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
	4435	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
	4436	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
[331]	4437	#endif
	4438	}
	4439	else
	4440	break;
	4441	}
	4442	else // switch slot to VALID state
	4443	{
	4444
	4445	#ifdef INSTRUMENTATION
[789]	4446	m_cpt_dcache_dir_write++;
[331]	4447	#endif
[789]	4448	r_dcache.write_dir(r_dcache_save_paddr.read(),
	4449	r_dcache_miss_way.read(),
	4450	r_dcache_miss_set.read(),
	4451	CACHE_SLOT_STATE_VALID);
[331]	4452
	4453	#if DEBUG_DCACHE
[789]	4454	if (m_debug_dcache_fsm)
	4455	std::cout << " <PROC " << name()
	4456	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
	4457	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
	4458	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
	4459	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
[331]	4460	#endif
	4461	// reset directory extension
	4462	size_t way = r_dcache_miss_way.read();
	4463	size_t set = r_dcache_miss_set.read();
[789]	4464	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
	4465	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[331]	4466	}
[836]	4467	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
	4468	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
	4469	else r_dcache_fsm = DCACHE_IDLE;
[331]	4470	}
	4471	break;
	4472	}
	4473	/////////////////////
[816]	4474	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
[331]	4475	{
[468]	4476	// coherence clack request (from DSPIN CLACK)
[789]	4477	if (r_dcache_clack_req.read())
[468]	4478	{
	4479	r_dcache_fsm = DCACHE_CC_CHECK;
	4480	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4481	break;
	4482	}
	4483
[331]	4484	// coherence request (from CC_RECEIVE FSM)
[789]	4485	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4486	{
	4487	r_dcache_fsm = DCACHE_CC_CHECK;
	4488	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4489	break;
	4490	}
	4491
[789]	4492	if (r_vci_rsp_data_error.read()) // bus error
[331]	4493	{
[789]	4494	if (r_dcache_vci_unc_write.read())
	4495	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
[616]	4496	else
[789]	4497	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
[816]	4498
[331]	4499	r_mmu_dbvar = m_dreq.addr;
	4500	r_vci_rsp_data_error = false;
	4501	m_drsp.error = true;
	4502	m_drsp.valid = true;
	4503	r_dcache_fsm = DCACHE_IDLE;
	4504	break;
	4505	}
[789]	4506	else if (r_vci_rsp_fifo_dcache.rok()) // data available
	4507	{
[331]	4508	// consume data
	4509	vci_rsp_fifo_dcache_get = true;
	4510	r_dcache_fsm = DCACHE_IDLE;
	4511
	4512	// acknowledge the processor request if it has not been modified
[789]	4513	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
[331]	4514	{
[789]	4515	m_drsp.valid = true;
	4516	m_drsp.error = false;
	4517	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
[331]	4518	}
[789]	4519	}
[331]	4520	break;
	4521	}
	4522	/////////////////////
	4523	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
	4524	{
[468]	4525	// coherence clack request (from DSPIN CLACK)
[789]	4526	if (r_dcache_clack_req.read())
[468]	4527	{
	4528	r_dcache_fsm = DCACHE_CC_CHECK;
	4529	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4530	break;
	4531	}
	4532
[331]	4533	// coherence request (from CC_RECEIVE FSM)
[789]	4534	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4535	{
	4536	r_dcache_fsm = DCACHE_CC_CHECK;
	4537	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4538	break;
	4539	}
	4540
[789]	4541	if (r_vci_rsp_data_error.read()) // bus error
[331]	4542	{
	4543	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
	4544	r_mmu_dbvar = m_dreq.addr;
	4545	r_vci_rsp_data_error = false;
	4546	m_drsp.error = true;
	4547	m_drsp.valid = true;
	4548	r_dcache_fsm = DCACHE_IDLE;
	4549	break;
	4550	}
[789]	4551	else if (r_vci_rsp_fifo_dcache.rok()) // data available
	4552	{
[331]	4553	// consume data
	4554	vci_rsp_fifo_dcache_get = true;
	4555
[789]	4556	if (r_dcache_ll_rsp_count.read() == 0) // first flit
[331]	4557	{
	4558	// set key value in llsc reservation buffer
	4559	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
[789]	4560	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
[331]	4561	}
	4562	else // last flit
	4563	{
	4564	// acknowledge the processor request if it has not been modified
[789]	4565	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
[331]	4566	{
[789]	4567	m_drsp.valid = true;
	4568	m_drsp.error = false;
	4569	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
[331]	4570	}
	4571	r_dcache_fsm = DCACHE_IDLE;
	4572	}
[789]	4573	}
[331]	4574	break;
	4575	}
	4576	////////////////////
[789]	4577	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
[331]	4578	{
[468]	4579	// coherence clack request (from DSPIN CLACK)
[789]	4580	if (r_dcache_clack_req.read())
[468]	4581	{
	4582	r_dcache_fsm = DCACHE_CC_CHECK;
	4583	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4584	break;
	4585	}
	4586
[331]	4587	// coherence request (from CC_RECEIVE FSM)
[789]	4588	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4589	{
	4590	r_dcache_fsm = DCACHE_CC_CHECK;
	4591	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4592	break;
	4593	}
	4594
[789]	4595	if (r_vci_rsp_data_error.read()) // bus error
[331]	4596	{
	4597	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
	4598	r_mmu_dbvar = m_dreq.addr;
	4599	r_vci_rsp_data_error = false;
	4600	m_drsp.error = true;
	4601	m_drsp.valid = true;
	4602	r_dcache_fsm = DCACHE_IDLE;
	4603	break;
	4604	}
[789]	4605	else if (r_vci_rsp_fifo_dcache.rok()) // response available
	4606	{
[331]	4607	// consume response
	4608	vci_rsp_fifo_dcache_get = true;
	4609	m_drsp.valid = true;
	4610	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
	4611	r_dcache_fsm = DCACHE_IDLE;
[789]	4612	}
[331]	4613	break;
	4614	}
	4615	//////////////////////////
[789]	4616	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
	4617	// before handling a processor WRITE or SC request
	4618	// Input argument is r_dcache_dirty_paddr
	4619	// In this first state, we get PTE value in dcache
	4620	// and post a CAS request to CMD FSM
[331]	4621	{
	4622	// get PTE in dcache
	4623	uint32_t pte;
	4624	size_t way;
	4625	size_t set;
[468]	4626	size_t word; // unused
[331]	4627	int state;
	4628
	4629	#ifdef INSTRUMENTATION
[789]	4630	m_cpt_dcache_data_read++;
	4631	m_cpt_dcache_dir_read++;
[331]	4632	#endif
[789]	4633	r_dcache.read(r_dcache_dirty_paddr.read(),
	4634	&pte,
	4635	&way,
	4636	&set,
	4637	&word,
	4638	&state);
[331]	4639
	4640	assert( (state == CACHE_SLOT_STATE_VALID) and
	4641	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
	4642
	4643	// request CAS transaction to CMD_FSM
[789]	4644	r_dcache_dirty_way = way;
	4645	r_dcache_dirty_set = set;
[331]	4646
	4647	// check llsc reservation buffer
[789]	4648	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
[331]	4649	r_dcache_llsc_valid = false;
	4650
	4651	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
	4652	r_dcache_vci_cas_req = true;
	4653	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
	4654	r_dcache_vci_cas_old = pte;
	4655	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
	4656	r_dcache_fsm = DCACHE_DIRTY_WAIT;
	4657
	4658	#if DEBUG_DCACHE
[789]	4659	if (m_debug_dcache_fsm)
	4660	{
	4661	std::cout << " <PROC " << name()
	4662	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
	4663	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
	4664	<< " / PTE_VALUE = " << pte << std::dec
	4665	<< " / SET = " << set
	4666	<< " / WAY = " << way << std::endl;
	4667	}
[331]	4668	#endif
	4669	break;
	4670	}
	4671	///////////////////////
[789]	4672	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
	4673	// and return to IDLE state when response is received.
	4674	// we don't care if the CAS is a failure:
	4675	// - if the CAS is a success, the coherence mechanism
	4676	// updates the local copy.
	4677	// - if the CAS is a failure, we just retry the write.
[331]	4678	{
[468]	4679	// coherence clack request (from DSPIN CLACK)
[789]	4680	if (r_dcache_clack_req.read())
[468]	4681	{
	4682	r_dcache_fsm = DCACHE_CC_CHECK;
	4683	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4684	break;
	4685	}
	4686
[331]	4687	// coherence request (from CC_RECEIVE FSM)
[789]	4688	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
[331]	4689	{
	4690	r_dcache_fsm = DCACHE_CC_CHECK;
	4691	r_dcache_fsm_cc_save = r_dcache_fsm.read();
	4692	break;
	4693	}
	4694
[789]	4695	if (r_vci_rsp_data_error.read()) // bus error
[331]	4696	{
	4697	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
	4698	std::cout << "This should not happen in this state" << std::endl;
	4699	exit(0);
	4700	}
[789]	4701	else if (r_vci_rsp_fifo_dcache.rok()) // response available
[331]	4702	{
	4703	vci_rsp_fifo_dcache_get = true;
	4704	r_dcache_fsm = DCACHE_IDLE;
	4705
	4706	#if DEBUG_DCACHE
[789]	4707	if (m_debug_dcache_fsm)
	4708	{
	4709	std::cout << " <PROC " << name()
	4710	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
	4711	}
[331]	4712	#endif
	4713	}
	4714	break;
	4715	}
	4716	/////////////////////
	4717	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
	4718	// handling coherence requests for DCACHE.
	4719	// If there is a matching pending miss on the modified cache
	4720	// line this is signaled in the r_dcache_miss inval flip-flop.
	4721	// If the updated (or invalidated) cache line has copies in TLBs
	4722	// these TLB copies are invalidated.
	4723	// The return state is defined in r_dcache_fsm_cc_save
	4724	{
[789]	4725	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
	4726	paddr_t mask = ~((m_dcache_words << 2) - 1);
[331]	4727
[484]	4728	// CLACK handler
	4729	// We switch the directory slot to EMPTY state and reset
	4730	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
[789]	4731	if (r_dcache_clack_req.read())
[484]	4732	{
[789]	4733	if (m_dreq.valid ) m_cost_data_miss_frz++;
[331]	4734
[484]	4735	#ifdef INSTRUMENTATION
[789]	4736	m_cpt_dcache_dir_write++;
[484]	4737	#endif
[789]	4738	r_dcache.write_dir(0,
	4739	r_dcache_clack_way.read(),
	4740	r_dcache_clack_set.read(),
	4741	CACHE_SLOT_STATE_EMPTY);
[484]	4742
[789]	4743	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
	4744	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
[484]	4745	{
	4746	r_dcache_miss_clack = false;
	4747	}
	4748
	4749	r_dcache_clack_req = false;
	4750
	4751	// return to cc_save state
	4752	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
	4753
	4754	#if DEBUG_DCACHE
[789]	4755	if (m_debug_dcache_fsm)
	4756	{
	4757	std::cout << " <PROC " << name()
	4758	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
	4759	<< " Switch slot to EMPTY state : "
	4760	<< " set = " << r_dcache_clack_set.read()
	4761	<< " / way = " << r_dcache_clack_way.read() << std::endl;
	4762	}
[484]	4763	#endif
	4764	break;
	4765	}
	4766
[836]	4767	assert(not r_dcache_cc_send_req.read() and
	4768	"CC_SEND must be available in DCACHE_CC_CHECK");
[487]	4769
[468]	4770	// Match between MISS address and CC address
[816]	4771	if (r_cc_receive_dcache_req.read() and
[789]	4772	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
	4773	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
[468]	4774	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
	4775	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
[331]	4776	{
	4777	// signaling matching
	4778	r_dcache_miss_inval = true;
	4779
	4780	// in case of update, go to CC_UPDT
	4781	// JUST TO POP THE FIFO
	4782	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
	4783	{
[789]	4784	r_dcache_fsm = DCACHE_CC_UPDT;
	4785	r_dcache_cc_word = r_cc_receive_word_idx.read();
[468]	4786
[331]	4787	// just pop the fifo , don't write in icache
	4788	r_dcache_cc_need_write = false;
	4789	}
	4790	// the request is dealt with
	4791	else
	4792	{
	4793	r_cc_receive_dcache_req = false;
[468]	4794	r_dcache_fsm = r_dcache_fsm_cc_save.read();
[331]	4795	}
	4796
	4797	#if DEBUG_DCACHE
[789]	4798	if (m_debug_dcache_fsm)
	4799	{
	4800	std::cout << " <PROC " << name()
	4801	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
	4802	<< " PADDR = " << std::hex << paddr << std::endl;
	4803	}
[331]	4804	#endif
[468]	4805	}
[331]	4806
[468]	4807	// CC request handler
[816]	4808
[468]	4809	int state = 0;
	4810	size_t way = 0;
	4811	size_t set = 0;
	4812	size_t word = 0;
	4813
[331]	4814	#ifdef INSTRUMENTATION
[789]	4815	m_cpt_dcache_dir_read++;
[331]	4816	#endif
[789]	4817	r_dcache.read_dir(paddr,
	4818	&state,
	4819	&way,
	4820	&set,
	4821	&word); // unused
[331]	4822
[468]	4823	r_dcache_cc_way = way;
	4824	r_dcache_cc_set = set;
[331]	4825
[789]	4826	if (state == CACHE_SLOT_STATE_VALID) // hit
[468]	4827	{
	4828	// need to update the cache state
	4829	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
[331]	4830	{
	4831	r_dcache_cc_need_write = true;
[468]	4832	r_dcache_fsm = DCACHE_CC_UPDT;
	4833	r_dcache_cc_word = r_cc_receive_word_idx.read();
[331]	4834	}
[789]	4835	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
[331]	4836	{
[789]	4837	r_dcache_fsm = DCACHE_CC_INVAL;
[331]	4838	}
[468]	4839	}
	4840	else // miss
	4841	{
	4842	// multicast acknowledgement required in case of update
[789]	4843	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
[468]	4844	{
[789]	4845	r_dcache_fsm = DCACHE_CC_UPDT;
	4846	r_dcache_cc_word = r_cc_receive_word_idx.read();
[331]	4847
[468]	4848	// just pop the fifo , don't write in icache
	4849	r_dcache_cc_need_write = false;
	4850	}
	4851	else // No response needed
	4852	{
	4853	r_cc_receive_dcache_req = false;
[789]	4854	r_dcache_fsm = r_dcache_fsm_cc_save.read();
[468]	4855	}
	4856	}
	4857
[331]	4858	#if DEBUG_DCACHE
[789]	4859	if (m_debug_dcache_fsm)
	4860	{
	4861	std::cout << " <PROC " << name()
	4862	<< " DCACHE_CC_CHECK> Coherence request received:"
	4863	<< " PADDR = " << std::hex << paddr
	4864	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
	4865	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
	4866	}
[331]	4867	#endif
[468]	4868
[331]	4869	break;
	4870	}
	4871	/////////////////////
[468]	4872	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
	4873	// CLEANUP after possible invalidation of copies in
	4874	// TLBs
[331]	4875	{
[789]	4876	size_t way = r_dcache_cc_way.read();
	4877	size_t set = r_dcache_cc_set.read();
[331]	4878
[789]	4879	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
[331]	4880	{
[789]	4881	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
	4882	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
	4883	r_dcache_tlb_inval_set = 0;
	4884	r_dcache_fsm_scan_save = r_dcache_fsm.read();
	4885	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[468]	4886	break;
	4887	}
[331]	4888
[789]	4889	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
[468]	4890	{
	4891	r_itlb.reset();
	4892	r_dtlb.reset();
[789]	4893	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[468]	4894
[331]	4895	#if DEBUG_DCACHE
[789]	4896	if (m_debug_dcache_fsm)
	4897	{
	4898	std::cout << " <PROC " << name()
	4899	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
	4900	}
[331]	4901	#endif
[468]	4902	}
[331]	4903
[789]	4904	assert(not r_dcache_cc_send_req.read() &&
[468]	4905	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
	4906	"must not be set");
[331]	4907
[816]	4908	// Switch slot state to ZOMBI and send CLEANUP command
[789]	4909	r_dcache.write_dir(way,
	4910	set,
	4911	CACHE_SLOT_STATE_ZOMBI);
[331]	4912
[468]	4913	// coherence request completed
	4914	r_cc_receive_dcache_req = false;
	4915	r_dcache_cc_send_req = true;
	4916	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
	4917	r_dcache_cc_send_way = r_dcache_cc_way.read();
	4918	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
	4919	r_dcache_fsm = r_dcache_fsm_cc_save.read();
	4920
[331]	4921	#if DEBUG_DCACHE
[789]	4922	if (m_debug_dcache_fsm)
	4923	{
	4924	std::cout << " <PROC " << name()
	4925	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
	4926	<< " / WAY = " << way
	4927	<< " / SET = " << set << std::endl;
	4928	}
[331]	4929	#endif
	4930	break;
	4931	}
	4932	///////////////////
[789]	4933	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
	4934	// after possible invalidation of copies in TLBs
[331]	4935	{
[789]	4936	size_t word = r_dcache_cc_word.read();
	4937	size_t way = r_dcache_cc_way.read();
	4938	size_t set = r_dcache_cc_set.read();
[331]	4939
[789]	4940	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
[331]	4941	{
[789]	4942	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
[468]	4943	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
	4944	r_dcache_tlb_inval_set = 0;
	4945	r_dcache_fsm_scan_save = r_dcache_fsm.read();
	4946	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
[331]	4947
[468]	4948	break;
	4949	}
[331]	4950
[789]	4951	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
[468]	4952	{
	4953	r_itlb.reset();
	4954	r_dtlb.reset();
[789]	4955	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
[468]	4956
[331]	4957	#if DEBUG_DCACHE
[789]	4958	if (m_debug_dcache_fsm)
	4959	{
	4960	std::cout << " <PROC " << name()
	4961	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
	4962	}
[331]	4963	#endif
[468]	4964	}
[331]	4965
[468]	4966	assert (not r_dcache_cc_send_req.read() &&
	4967	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
	4968	"must not be set");
[816]	4969
[789]	4970	if (not r_cc_receive_updt_fifo_be.rok()) break;
[468]	4971
	4972	if (r_dcache_cc_need_write.read())
	4973	{
[816]	4974
[331]	4975	#ifdef INSTRUMENTATION
[789]	4976	m_cpt_dcache_data_write++;
[331]	4977	#endif
[789]	4978	r_dcache.write(way,
	4979	set,
	4980	word,
	4981	r_cc_receive_updt_fifo_data.read(),
	4982	r_cc_receive_updt_fifo_be.read());
[331]	4983
[468]	4984	r_dcache_cc_word = word + 1;
[331]	4985
	4986	#if DEBUG_DCACHE
[789]	4987	if (m_debug_dcache_fsm)
	4988	{
	4989	std::cout << " <PROC " << name()
	4990	<< " DCACHE_CC_UPDT> Write one word" << std::dec
	4991	<< " / WAY = " << way
	4992	<< " / SET = " << set
	4993	<< " / WORD = " << word
	4994	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
	4995	}
[331]	4996	#endif
	4997	}
	4998
[789]	4999	if (r_cc_receive_updt_fifo_eop.read()) // last word
[331]	5000	{
[468]	5001	// no need to write in the cache anymore
	5002	r_dcache_cc_need_write = false;
[331]	5003
[468]	5004	// coherence request completed
	5005	r_cc_receive_dcache_req = false;
[331]	5006
[468]	5007	// request multicast acknowledgement
	5008	r_dcache_cc_send_req = true;
	5009	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
	5010	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
	5011	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
	5012	r_dcache_fsm = r_dcache_fsm_cc_save.read();
[331]	5013	}
	5014
[468]	5015	//consume fifo if not eop
	5016	cc_receive_updt_fifo_get = true;
	5017
[331]	5018	break;
	5019	}
	5020	///////////////////////////
[789]	5021	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
	5022	// It makes assumption: m_itlb_sets == m_dtlb_sets
	5023	// All ways are handled in parallel.
	5024	// We enter this state when a DCACHE line is modified,
	5025	// and there is a copy in itlb or dtlb.
	5026	// It can be caused by:
	5027	// - a coherence inval or updt transaction,
	5028	// - a line inval caused by a cache miss
	5029	// - a processor XTN inval request,
	5030	// - a WRITE hit,
	5031	// - a Dirty bit update
	5032	// Input arguments are:
	5033	// - r_dcache_tlb_inval_line
	5034	// - r_dcache_tlb_inval_set
	5035	// - r_dcache_fsm_scan_save
[331]	5036	{
[789]	5037	paddr_t line = r_dcache_tlb_inval_line.read();
	5038	size_t set = r_dcache_tlb_inval_set.read();
	5039	size_t way;
	5040	bool ok;
[331]	5041
[789]	5042	for (way = 0; way < m_itlb_ways; way++)
[331]	5043	{
[789]	5044	ok = r_itlb.inval(line, way, set);
[331]	5045
	5046	#if DEBUG_DCACHE
[789]	5047	if (m_debug_dcache_fsm and ok)
	5048	{
	5049	std::cout << " <PROC " << name()
	5050	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
	5051	<< " line = " << line << std::dec
	5052	<< " / set = " << set
	5053	<< " / way = " << way << std::endl;
	5054	}
[331]	5055	#endif
	5056	}
	5057
[789]	5058	for (way = 0; way < m_dtlb_ways; way++)
[331]	5059	{
[789]	5060	ok = r_dtlb.inval( line, way, set);
[331]	5061
	5062	#if DEBUG_DCACHE
[789]	5063	if (m_debug_dcache_fsm and ok)
	5064	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
	5065	<< " Invalidate DTLB entry" << std::hex
	5066	<< " / line = " << line << std::dec
	5067	<< " / set = " << set
	5068	<< " / way = " << way << std::endl;
[331]	5069	#endif
	5070	}
	5071
	5072	// return to the calling state when TLB inval completed
[789]	5073	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
[331]	5074	{
	5075	r_dcache_fsm = r_dcache_fsm_scan_save.read();
	5076	}
	5077	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
	5078	break;
	5079	}
	5080	} // end switch r_dcache_fsm
	5081
	5082	///////////////// wbuf update ///////////////////////////////////////////////////////
	5083	r_wbuf.update();
	5084
	5085	///////////////// llsc update ///////////////////////////////////////////////////////
	5086	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
	5087	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
	5088
	5089	//////////////// test processor frozen //////////////////////////////////////////////
	5090	// The simulation exit if the number of consecutive frozen cycles
	5091	// is larger than the m_max_frozen_cycles (constructor parameter)
[789]	5092	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
[331]	5093	{
[789]	5094	m_cpt_frz_cycles++; // used for instrumentation
	5095	m_cpt_stop_simulation++; // used for debug
	5096	if (m_cpt_stop_simulation > m_max_frozen_cycles)
[331]	5097	{
	5098	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
	5099	<< " stop at cycle " << m_cpt_total_cycles << std::endl
	5100	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
	5101	<< std::endl;
	5102	r_iss.dump();
[896]	5103	r_wbuf.printTrace();
	5104	raise(SIGINT);
[331]	5105	}
	5106	}
	5107	else
	5108	{
	5109	m_cpt_stop_simulation = 0;
	5110	}
	5111
	5112	/////////// execute one iss cycle /////////////////////////////////
	5113	{
[789]	5114	uint32_t it = 0;
	5115	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
	5116	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
[331]	5117	}
	5118
	5119	////////////////////////////////////////////////////////////////////////////
	5120	// The VCI_CMD FSM controls the following ressources:
	5121	// - r_vci_cmd_fsm
	5122	// - r_vci_cmd_min
	5123	// - r_vci_cmd_max
	5124	// - r_vci_cmd_cpt
	5125	// - r_vci_cmd_imiss_prio
	5126	// - wbuf (reset)
	5127	// - r_icache_miss_req (reset)
	5128	// - r_icache_unc_req (reset)
	5129	// - r_dcache_vci_miss_req (reset)
	5130	// - r_dcache_vci_unc_req (reset)
	5131	// - r_dcache_vci_ll_req (reset)
	5132	// - r_dcache_vci_sc_req (reset in case of local sc fail)
	5133	// - r_dcache_vci_cas_req (reset)
	5134	//
	5135	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
	5136	// There are 8 request types, with the following priorities :
	5137	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
	5138	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
	5139	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
	5140	// 4 - Instruction Uncachable : r_icache_unc_req
	5141	// 5 - Data Write : r_wbuf.rok()
	5142	// 6 - Data Linked Load : r_dcache_vci_ll_req
	5143	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
	5144	// 8 - Compare And Swap : r_dcache_vci_cas_req
	5145	//
	5146	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
	5147	// and the VCI_RSP_FSM are fully desynchronized.
	5148	//
	5149	// VCI formats:
	5150	// According to the VCI advanced specification, all read requests packets
	5151	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
	5152	// are one word packets.
	5153	// For write burst packets, all words are in the same cache line,
	5154	// and addresses must be contiguous (the BE field is 0 in case of "holes").
	5155	// The sc command packet implements actually a compare-and-swap mechanism
	5156	// and the packet contains two flits.
	5157	////////////////////////////////////////////////////////////////////////////////////
	5158
[423]	5159
[789]	5160	switch (r_vci_cmd_fsm.read())
[331]	5161	{
	5162	//////////////
	5163	case CMD_IDLE:
	5164	{
[394]	5165	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
[331]	5166	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
	5167	// to check a possible pending write on the same cache line.
	5168	// As there is only one possible access per cycle to write buffer, we implement
	5169	// a round-robin priority between DCACHE and ICACHE for this access,
	5170	// using the r_vci_cmd_imiss_prio flip-flop.
	5171
[789]	5172	size_t wbuf_min;
	5173	size_t wbuf_max;
[331]	5174
	5175	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
[789]	5176	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[331]	5177
[789]	5178	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
	5179	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[331]	5180
[789]	5181	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
	5182	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[616]	5183
[789]	5184	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
	5185	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
[616]	5186
[331]	5187	bool icache_miss_req = r_icache_miss_req.read() and
[789]	5188	(not (r_dcache_vci_miss_req.read() or
	5189	r_dcache_vci_ll_req.read() or
	5190	r_dcache_vci_cas_req.read() or
	5191	r_dcache_vci_sc_req.read()) or
	5192	r_vci_cmd_imiss_prio.read());
[331]	5193
[616]	5194	// 1 - Data unc write
[789]	5195	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
[331]	5196	{
[616]	5197	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
	5198	r_dcache_vci_unc_req = false;
	5199	}
	5200	// 2 data read miss
[789]	5201	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[616]	5202	{
[331]	5203	r_vci_cmd_fsm = CMD_DATA_MISS;
	5204	r_dcache_vci_miss_req = false;
	5205	r_vci_cmd_imiss_prio = true;
	5206	}
[616]	5207	// 3 - Data Read Uncachable
[789]	5208	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
[331]	5209	{
[616]	5210	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
[331]	5211	r_dcache_vci_unc_req = false;
	5212	}
[616]	5213	// 4 - Data Linked Load
[789]	5214	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[331]	5215	{
[616]	5216	r_vci_cmd_fsm = CMD_DATA_LL;
	5217	r_dcache_vci_ll_req = false;
	5218	r_vci_cmd_imiss_prio = true;
[331]	5219	}
[616]	5220	// 5 - Instruction Miss
[789]	5221	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
[331]	5222	{
	5223	r_vci_cmd_fsm = CMD_INS_MISS;
	5224	r_icache_miss_req = false;
	5225	r_vci_cmd_imiss_prio = false;
	5226	}
[616]	5227	// 6 - Instruction Uncachable
[789]	5228	else if (r_icache_unc_req.read())
[331]	5229	{
[789]	5230	r_vci_cmd_fsm = CMD_INS_UNC;
	5231	r_icache_unc_req = false;
[331]	5232	}
[616]	5233	// 7 - Data Write
[789]	5234	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
[331]	5235	{
[789]	5236	r_vci_cmd_fsm = CMD_DATA_WRITE;
	5237	r_vci_cmd_cpt = wbuf_min;
	5238	r_vci_cmd_min = wbuf_min;
	5239	r_vci_cmd_max = wbuf_max;
[331]	5240	}
[616]	5241	// 8 - Data Store Conditionnal
[789]	5242	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[331]	5243	{
[789]	5244	r_vci_cmd_fsm = CMD_DATA_SC;
	5245	r_dcache_vci_sc_req = false;
	5246	r_vci_cmd_imiss_prio = true;
	5247	r_vci_cmd_cpt = 0;
[331]	5248	}
[616]	5249	// 9 - Compare And Swap
[789]	5250	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
[331]	5251	{
[789]	5252	r_vci_cmd_fsm = CMD_DATA_CAS;
	5253	r_dcache_vci_cas_req = false;
	5254	r_vci_cmd_imiss_prio = true;
	5255	r_vci_cmd_cpt = 0;
[331]	5256	}
[394]	5257
	5258	#if DEBUG_CMD
[789]	5259	if (m_debug_cmd_fsm )
	5260	{
	5261	std::cout << " <PROC " << name() << " CMD_IDLE>"
	5262	<< " / dmiss_req = " << dcache_miss_req
	5263	<< " / imiss_req = " << icache_miss_req
	5264	<< std::endl;
	5265	}
[394]	5266	#endif
[331]	5267	break;
	5268	}
	5269	////////////////////
	5270	case CMD_DATA_WRITE:
	5271	{
[789]	5272	if (p_vci.cmdack.read())
[331]	5273	{
	5274	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
	5275	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
	5276	{
[789]	5277	r_vci_cmd_fsm = CMD_IDLE;
	5278	r_wbuf.sent();
[331]	5279	}
	5280	}
	5281	break;
	5282	}
	5283	/////////////////
	5284	case CMD_DATA_SC:
	5285	case CMD_DATA_CAS:
	5286	{
	5287	// The CAS and SC VCI commands contain two flits
[789]	5288	if (p_vci.cmdack.read())
[331]	5289	{
	5290	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
	5291	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
	5292	}
	5293	break;
	5294	}
	5295	//////////////////
	5296	case CMD_INS_MISS:
	5297	case CMD_INS_UNC:
	5298	case CMD_DATA_MISS:
[616]	5299	case CMD_DATA_UNC_READ:
	5300	case CMD_DATA_UNC_WRITE:
[331]	5301	case CMD_DATA_LL:
	5302	{
	5303	// all read VCI commands contain one single flit
[789]	5304	if (p_vci.cmdack.read()) {
[423]	5305	r_vci_cmd_fsm = CMD_IDLE;
	5306	}
[331]	5307	break;
	5308	}
	5309
	5310	} // end switch r_vci_cmd_fsm
	5311
	5312	//////////////////////////////////////////////////////////////////////////
	5313	// The VCI_RSP FSM controls the following ressources:
	5314	// - r_vci_rsp_fsm:
	5315	// - r_vci_rsp_fifo_icache (push)
	5316	// - r_vci_rsp_fifo_dcache (push)
	5317	// - r_vci_rsp_data_error (set)
	5318	// - r_vci_rsp_ins_error (set)
	5319	// - r_vci_rsp_cpt
	5320	// - r_dcache_vci_sc_req (reset when SC response recieved)
	5321	//
	5322	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
	5323	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
	5324	// to identify the transactions.
	5325	//
	5326	// VCI vormat:
	5327	// This component checks the response packet length and accepts only
	5328	// single word packets for write response packets.
	5329	//
	5330	// Error handling:
	5331	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
	5332	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
	5333	// flip_flop and the error is signaled by the DCACHE FSM.
	5334	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
	5335	// flip_flop and the error is signaled by the ICACHE FSM.
	5336	// In case of Cleanup Error, the simulation stops with an error message...
	5337	//////////////////////////////////////////////////////////////////////////
	5338
[789]	5339	switch (r_vci_rsp_fsm.read())
[331]	5340	{
	5341	//////////////
	5342	case RSP_IDLE:
	5343	{
[789]	5344	if (p_vci.rspval.read())
[331]	5345	{
	5346	r_vci_rsp_cpt = 0;
	5347
[789]	5348	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
[331]	5349	{
	5350	r_vci_rsp_fsm = RSP_DATA_UNC;
	5351	}
[789]	5352	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
[331]	5353	{
	5354	r_vci_rsp_fsm = RSP_DATA_MISS;
	5355	}
[789]	5356	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
[331]	5357	{
	5358	r_vci_rsp_fsm = RSP_INS_UNC;
	5359	}
[789]	5360	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
[331]	5361	{
	5362	r_vci_rsp_fsm = RSP_INS_MISS;
	5363	}
[789]	5364	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
[331]	5365	{
	5366	r_vci_rsp_fsm = RSP_DATA_WRITE;
	5367	}
[789]	5368	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
[331]	5369	{
	5370	r_vci_rsp_fsm = RSP_DATA_UNC;
	5371	}
[789]	5372	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
[331]	5373	{
	5374	r_vci_rsp_fsm = RSP_DATA_LL;
	5375	}
[789]	5376	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
[331]	5377	{
	5378	r_vci_rsp_fsm = RSP_DATA_UNC;
	5379	}
	5380	else
	5381	{
	5382	assert(false and "Unexpected VCI response");
	5383	}
	5384	}
	5385	break;
	5386	}
	5387	//////////////////
	5388	case RSP_INS_MISS:
	5389	{
[789]	5390	if (p_vci.rspval.read())
[331]	5391	{
[789]	5392	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5393	{
	5394	r_vci_rsp_ins_error = true;
[789]	5395	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
[331]	5396	}
	5397	else // no error reported
	5398	{
[789]	5399	if (r_vci_rsp_fifo_icache.wok())
[331]	5400	{
[789]	5401	if (r_vci_rsp_cpt.read() >= m_icache_words)
[473]	5402	{
	5403	std::cout << "ERROR in VCI_CC_VCACHE " << name()
	5404	<< " VCI response packet too long "
	5405	<< " for instruction miss" << std::endl;
	5406	exit(0);
	5407	}
[789]	5408	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
	5409	vci_rsp_fifo_icache_put = true,
	5410	vci_rsp_fifo_icache_data = p_vci.rdata.read();
	5411	if (p_vci.reop.read())
[331]	5412	{
[789]	5413	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
[473]	5414	{
	5415	std::cout << "ERROR in VCI_CC_VCACHE " << name()
[816]	5416	<< " VCI response packet too short"
[473]	5417	<< " for instruction miss" << std::endl;
	5418	exit(0);
	5419	}
[789]	5420	r_vci_rsp_fsm = RSP_IDLE;
[331]	5421	}
	5422	}
	5423	}
	5424	}
	5425	break;
	5426	}
	5427	/////////////////
	5428	case RSP_INS_UNC:
	5429	{
[789]	5430	if (p_vci.rspval.read())
[331]	5431	{
[789]	5432	assert(p_vci.reop.read() and
[331]	5433	"illegal VCI response packet for uncachable instruction");
	5434
[789]	5435	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5436	{
	5437	r_vci_rsp_ins_error = true;
	5438	r_vci_rsp_fsm = RSP_IDLE;
	5439	}
	5440	else // no error reported
	5441	{
[789]	5442	if (r_vci_rsp_fifo_icache.wok())
[331]	5443	{
[789]	5444	vci_rsp_fifo_icache_put = true;
	5445	vci_rsp_fifo_icache_data = p_vci.rdata.read();
[331]	5446	r_vci_rsp_fsm = RSP_IDLE;
	5447	}
	5448	}
	5449	}
	5450	break;
	5451	}
	5452	///////////////////
	5453	case RSP_DATA_MISS:
	5454	{
[789]	5455	if (p_vci.rspval.read())
[331]	5456	{
[789]	5457	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5458	{
	5459	r_vci_rsp_data_error = true;
[789]	5460	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
[331]	5461	}
	5462	else // no error reported
	5463	{
[789]	5464	if (r_vci_rsp_fifo_dcache.wok())
[331]	5465	{
[789]	5466	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
[331]	5467	"The VCI response packet for data miss is too long");
	5468
[789]	5469	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
	5470	vci_rsp_fifo_dcache_put = true,
	5471	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
	5472	if (p_vci.reop.read())
[331]	5473	{
[789]	5474	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
[331]	5475	"The VCI response packet for data miss is too short");
	5476
[789]	5477	r_vci_rsp_fsm = RSP_IDLE;
[331]	5478	}
	5479	}
	5480	}
	5481	}
	5482	break;
	5483	}
	5484	//////////////////
	5485	case RSP_DATA_UNC:
	5486	{
[789]	5487	if (p_vci.rspval.read())
[331]	5488	{
[789]	5489	assert(p_vci.reop.read() and
[331]	5490	"illegal VCI response packet for uncachable read data");
	5491
[789]	5492	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5493	{
	5494	r_vci_rsp_data_error = true;
	5495	r_vci_rsp_fsm = RSP_IDLE;
	5496	}
[789]	5497	else // no error reported
[331]	5498	{
[789]	5499	if (r_vci_rsp_fifo_dcache.wok())
[331]	5500	{
[789]	5501	vci_rsp_fifo_dcache_put = true;
	5502	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
[331]	5503	r_vci_rsp_fsm = RSP_IDLE;
	5504	}
	5505	}
	5506	}
	5507	break;
	5508	}
[434]	5509	/////////////////
[331]	5510	case RSP_DATA_LL:
	5511	{
[789]	5512	if (p_vci.rspval.read())
[331]	5513	{
[789]	5514	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
[331]	5515	{
	5516	r_vci_rsp_data_error = true;
	5517	r_vci_rsp_fsm = RSP_IDLE;
[434]	5518	break;
[331]	5519	}
	5520	if (r_vci_rsp_cpt.read() == 0) //first flit
	5521	{
[789]	5522	if (r_vci_rsp_fifo_dcache.wok())
[331]	5523	{
[346]	5524	assert(!p_vci.reop.read() &&
[331]	5525	"illegal VCI response packet for LL");
	5526	vci_rsp_fifo_dcache_put = true;
[346]	5527	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
[331]	5528	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
	5529	}
	5530	break;
	5531	}
	5532	else // last flit
	5533	{
[789]	5534	if (r_vci_rsp_fifo_dcache.wok())
[331]	5535	{
[346]	5536	assert(p_vci.reop.read() &&
[331]	5537	"illegal VCI response packet for LL");
	5538	vci_rsp_fifo_dcache_put = true;
[346]	5539	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
[331]	5540	r_vci_rsp_fsm = RSP_IDLE;
	5541	}
	5542	break;
	5543	}
	5544	}
	5545	break;
	5546	}
	5547	////////////////////
	5548	case RSP_DATA_WRITE:
	5549	{
[346]	5550	if (p_vci.rspval.read())
[331]	5551	{
[789]	5552	assert(p_vci.reop.read() and
[331]	5553	"a VCI response packet must contain one flit for a write transaction");
	5554
	5555	r_vci_rsp_fsm = RSP_IDLE;
[789]	5556	uint32_t wbuf_index = p_vci.rtrdid.read();
[616]	5557	r_wbuf.completed(wbuf_index);
[789]	5558	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
[331]	5559	}
	5560	break;
	5561	}
	5562	} // end switch r_vci_rsp_fsm
	5563
	5564	/////////////////////////////////////////////////////////////////////////////////////
	5565	// The CC_SEND FSM is in charge of sending cleanups and the multicast
	5566	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
	5567	// and ICACHE FSM) that are served with a round-robin priority.
	5568	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
	5569	// soon as the request has been sent.
	5570	/////////////////////////////////////////////////////////////////////////////////////
[789]	5571	switch (r_cc_send_fsm.read())
[331]	5572	{
	5573	///////////////////////////
	5574	case CC_SEND_IDLE:
	5575	{
	5576	///////////////////////////////////////////////////////
	5577	// handling round robin between icache and dcache : //
	5578	// we first check for the last client and listen for //
	5579	// a request of the other, then update the client //
[386]	5580	// r_cc_send_last_client : 0 dcache / 1 icache
[331]	5581	///////////////////////////////////////////////////////
[333]	5582	bool update_last_client = r_cc_send_last_client.read();
[789]	5583	if (r_cc_send_last_client.read() == 0) // last client was dcache
[331]	5584	{
[333]	5585	if (r_icache_cc_send_req.read()) // request from icache
[331]	5586	update_last_client = 1; // update last client to icache
	5587	}
	5588	else // last client was icache
	5589	{
[333]	5590	if (r_dcache_cc_send_req.read()) // request from dcache
[331]	5591	update_last_client = 0; // update last client to dcache
	5592	}
	5593	r_cc_send_last_client = update_last_client;
	5594
	5595	// if there is an actual request
	5596	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
	5597	{
[386]	5598	// the new client is dcache and has a cleanup request
[816]	5599	if ((update_last_client == 0) and
[386]	5600	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
[331]	5601	r_cc_send_fsm = CC_SEND_CLEANUP_1;
[386]	5602	// the new client is dcache and has a multi acknowledgement request
[816]	5603	else if ((update_last_client == 0) and
[386]	5604	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
[331]	5605	r_cc_send_fsm = CC_SEND_MULTI_ACK;
[386]	5606	// the new client is icache and has a cleanup request
[816]	5607	else if ((update_last_client == 1) and
[386]	5608	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
[331]	5609	r_cc_send_fsm = CC_SEND_CLEANUP_1;
[386]	5610	// the new client is icache and has a multi acknowledgement request
[789]	5611	else if ((update_last_client == 1) and
[386]	5612	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
[331]	5613	r_cc_send_fsm = CC_SEND_MULTI_ACK;
	5614	}
	5615	break;
	5616	}
	5617	///////////////////////////
	5618	case CC_SEND_CLEANUP_1:
	5619	{
	5620	// wait for the first flit to be consumed
[468]	5621	if (p_dspin_p2m.read.read())
[331]	5622	r_cc_send_fsm = CC_SEND_CLEANUP_2;
	5623
	5624	break;
	5625	}
	5626	///////////////////////////
	5627	case CC_SEND_CLEANUP_2:
	5628	{
	5629	// wait for the second flit to be consumed
[468]	5630	if (p_dspin_p2m.read.read())
[331]	5631	{
[333]	5632	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	5633	r_dcache_cc_send_req = false; // reset dcache request
	5634	else // icache active request
	5635	r_icache_cc_send_req = false; // reset icache request
	5636
	5637	// go back to idle state
	5638	r_cc_send_fsm = CC_SEND_IDLE;
	5639	}
	5640	break;
	5641	}
	5642	///////////////////////////
	5643	case CC_SEND_MULTI_ACK:
	5644	{
	5645	// wait for the flit to be consumed
[789]	5646	if (p_dspin_p2m.read.read())
[331]	5647	{
[789]	5648	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	5649	r_dcache_cc_send_req = false; // reset dcache request
	5650	else // icache active request
	5651	r_icache_cc_send_req = false; // reset icache request
	5652	// go back to idle state
	5653	r_cc_send_fsm = CC_SEND_IDLE;
	5654	}
	5655	break;
	5656	}
	5657	} // end switch CC_SEND FSM
	5658
	5659	///////////////////////////////////////////////////////////////////////////////
[468]	5660	// CC_RECEIVE FSM
[331]	5661	// This FSM receive all coherence packets on a DSPIN40 port.
[468]	5662	// There is 5 packet types:
[331]	5663	// - CC_DATA_INVAL : DCACHE invalidate request
	5664	// - CC_DATA_UPDT : DCACHE update request (multi-words)
	5665	// - CC_INST_INVAL : ICACHE invalidate request
	5666	// - CC_INST_UPDT : ICACHE update request (multi-words)
	5667	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
	5668	//////////////////////////////////////////////////////////////////////////////
[789]	5669	switch (r_cc_receive_fsm.read())
[331]	5670	{
	5671	/////////////////////
	5672	case CC_RECEIVE_IDLE:
	5673	{
	5674	// a coherence request has arrived
[468]	5675	if (p_dspin_m2p.write.read())
[331]	5676	{
	5677	// initialize dspin received data
[468]	5678	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5679	// initialize coherence packet type
[386]	5680	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
[468]	5681	DspinDhccpParam::M2P_TYPE);
[331]	5682	// test for a broadcast
[468]	5683	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
[331]	5684	{
	5685	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
	5686	}
[468]	5687	// test for a multi updt
[816]	5688	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
[331]	5689	{
[468]	5690	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
[331]	5691	}
[468]	5692	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
[331]	5693	{
[468]	5694	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
[331]	5695	}
	5696	// test for a multi inval
[468]	5697	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
	5698	{
	5699	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
	5700	}
[331]	5701	else
	5702	{
[468]	5703	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
[331]	5704	}
	5705	}
	5706	break;
	5707	}
	5708	///////////////////////////////
	5709	case CC_RECEIVE_BRDCAST_HEADER:
	5710	{
	5711	// no actual data in the HEADER, just skip to second flit
	5712	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
	5713	break;
	5714	}
	5715	//////////////////////////////
	5716	case CC_RECEIVE_BRDCAST_NLINE:
	5717	{
	5718	// initialize dspin received data
[468]	5719	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5720	// wait for both dcache and icache to take the request
	5721	// TODO maybe we need to wait for both only to leave the state, but
	5722	// not to actually post a request to an available cache => need a
	5723	// flip_flop to check that ?
[816]	5724	if (not (r_cc_receive_icache_req.read()) and
[484]	5725	not (r_cc_receive_dcache_req.read()) and
[468]	5726	(p_dspin_m2p.write.read()))
[331]	5727	{
	5728	// request dcache to handle the BROADCAST
[468]	5729	r_cc_receive_dcache_req = true;
[789]	5730	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
[386]	5731	DspinDhccpParam::BROADCAST_NLINE);
[468]	5732	r_cc_receive_dcache_type = CC_TYPE_INVAL;
[331]	5733	// request icache to handle the BROADCAST
[468]	5734	r_cc_receive_icache_req = true;
[789]	5735	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
[386]	5736	DspinDhccpParam::BROADCAST_NLINE);
[468]	5737	r_cc_receive_icache_type = CC_TYPE_INVAL;
[331]	5738	// get back to idle state
	5739	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	5740	break;
	5741	}
	5742	// keep waiting for the caches to accept the request
	5743	break;
	5744	}
	5745	/////////////////////////////
[468]	5746	case CC_RECEIVE_DATA_INVAL_HEADER:
[331]	5747	{
[346]	5748	// sample updt tab index in the HEADER, then skip to second flit
[468]	5749	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
[331]	5750	break;
	5751	}
[468]	5752	/////////////////////////////
	5753	case CC_RECEIVE_INS_INVAL_HEADER:
	5754	{
	5755	// sample updt tab index in the HEADER, then skip to second flit
	5756	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
	5757	break;
	5758	}
[331]	5759	////////////////////////////
[468]	5760	case CC_RECEIVE_DATA_INVAL_NLINE:
[331]	5761	{
	5762	// sample nline in the second flit
[468]	5763	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5764	// for data INVAL, wait for dcache to take the request
[816]	5765	if (p_dspin_m2p.write.read() and
[789]	5766	not r_cc_receive_dcache_req.read())
[331]	5767	{
	5768	// request dcache to handle the INVAL
[468]	5769	r_cc_receive_dcache_req = true;
	5770	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
[331]	5771	r_cc_receive_dcache_type = CC_TYPE_INVAL;
	5772	// get back to idle state
	5773	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	5774	break;
	5775	}
[468]	5776	break;
	5777	}
	5778	//////////////////////////////
	5779	case CC_RECEIVE_INS_INVAL_NLINE:
	5780	{
	5781	// sample nline in the second flit
	5782	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5783	// for ins INVAL, wait for icache to take the request
[816]	5784	if (p_dspin_m2p.write.read() and
[789]	5785	not r_cc_receive_icache_req.read())
[331]	5786	{
	5787	// request icache to handle the INVAL
[468]	5788	r_cc_receive_icache_req = true;
	5789	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
[331]	5790	r_cc_receive_icache_type = CC_TYPE_INVAL;
	5791	// get back to idle state
	5792	r_cc_receive_fsm = CC_RECEIVE_IDLE;
	5793	break;
	5794	}
[468]	5795	break;
[331]	5796	}
	5797	////////////////////////////
[468]	5798	case CC_RECEIVE_DATA_UPDT_HEADER:
[331]	5799	{
	5800	// sample updt tab index in the HEADER, than skip to second flit
[468]	5801	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5802	// for data INVAL, wait for dcache to take the request and fifo to
	5803	// be empty
[468]	5804	if (not r_cc_receive_dcache_req.read())
[331]	5805	{
[789]	5806	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
[468]	5807	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
[331]	5808	break;
	5809	}
[468]	5810	break;
	5811	}
	5812	////////////////////////////
	5813	case CC_RECEIVE_INS_UPDT_HEADER:
	5814	{
	5815	// sample updt tab index in the HEADER, than skip to second flit
	5816	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5817	// for ins INVAL, wait for icache to take the request and fifo to be
	5818	// empty
[468]	5819	if (not r_cc_receive_icache_req.read())
[331]	5820	{
[789]	5821	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
[468]	5822	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
[331]	5823	break;
	5824	}
	5825	// keep waiting for the correct cache to accept the request
	5826	break;
	5827	}
	5828	///////////////////////////
[468]	5829	case CC_RECEIVE_DATA_UPDT_NLINE:
[331]	5830	{
	5831	// sample nline and word index in the second flit
[468]	5832	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5833	// for data INVAL, wait for dcache to take the request and fifo to
	5834	// be empty
[789]	5835	if (r_cc_receive_updt_fifo_be.empty() and
	5836	p_dspin_m2p.write.read())
[331]	5837	{
[789]	5838	r_cc_receive_dcache_req = true;
	5839	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
	5840	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
	5841	r_cc_receive_dcache_type = CC_TYPE_UPDT;
[331]	5842	// get back to idle state
[468]	5843	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
[331]	5844	break;
	5845	}
[468]	5846	break;
	5847	}
	5848	////////////////////////////
	5849	case CC_RECEIVE_INS_UPDT_NLINE:
	5850	{
	5851	// sample nline and word index in the second flit
	5852	uint64_t receive_data = p_dspin_m2p.data.read();
[331]	5853	// for ins INVAL, wait for icache to take the request and fifo to be
	5854	// empty
[789]	5855	if (r_cc_receive_updt_fifo_be.empty() and
	5856	p_dspin_m2p.write.read())
[331]	5857	{
[789]	5858	r_cc_receive_icache_req = true;
	5859	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
	5860	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
	5861	r_cc_receive_icache_type = CC_TYPE_UPDT;
[331]	5862	// get back to idle state
[468]	5863	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
[331]	5864	break;
	5865	}
	5866	break;
	5867	}
	5868	//////////////////////////
[468]	5869	case CC_RECEIVE_DATA_UPDT_DATA:
[331]	5870	{
	5871	// wait for the fifo
[468]	5872	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
[331]	5873	{
[468]	5874	uint64_t receive_data = p_dspin_m2p.data.read();
	5875	bool receive_eop = p_dspin_m2p.eop.read();
[403]	5876	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
[331]	5877	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
[403]	5878	cc_receive_updt_fifo_eop = receive_eop;
[331]	5879	cc_receive_updt_fifo_put = true;
[789]	5880	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
[331]	5881	}
	5882	break;
	5883	}
[468]	5884	//////////////////////////
	5885	case CC_RECEIVE_INS_UPDT_DATA:
	5886	{
	5887	// wait for the fifo
	5888	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
	5889	{
	5890	uint64_t receive_data = p_dspin_m2p.data.read();
	5891	bool receive_eop = p_dspin_m2p.eop.read();
	5892	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
	5893	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
	5894	cc_receive_updt_fifo_eop = receive_eop;
	5895	cc_receive_updt_fifo_put = true;
[789]	5896	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
[468]	5897	}
	5898	break;
	5899	}
	5900
[331]	5901	} // end switch CC_RECEIVE FSM
	5902
[468]	5903	///////////////// DSPIN CLACK interface ///////////////
[816]	5904
[468]	5905	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
	5906	DspinDhccpParam::CLACK_TYPE);
	5907
[789]	5908	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
[468]	5909	DspinDhccpParam::CLACK_WAY);
	5910
[789]	5911	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
[468]	5912	DspinDhccpParam::CLACK_SET);
	5913
[789]	5914	bool dspin_clack_get = false;
[468]	5915	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
	5916	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
	5917
	5918	if (r_dspin_clack_req.read())
	5919	{
	5920	// CLACK DATA: Send request to DCACHE FSM
[789]	5921	if (dcache_clack_request and not r_dcache_clack_req.read())
	5922	{
[468]	5923	r_dcache_clack_req = true;
[789]	5924	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
	5925	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
[468]	5926	dspin_clack_get = true;
	5927	}
	5928
	5929	// CLACK INST: Send request to ICACHE FSM
[789]	5930	else if (icache_clack_request and not r_icache_clack_req.read())
	5931	{
[468]	5932	r_icache_clack_req = true;
	5933	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
	5934	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
	5935	dspin_clack_get = true;
	5936	}
	5937	}
	5938	else
	5939	{
	5940	dspin_clack_get = true;
	5941	}
	5942
	5943	if (dspin_clack_get)
	5944	{
	5945	r_dspin_clack_req = p_dspin_clack.write.read();
	5946	r_dspin_clack_flit = p_dspin_clack.data.read();
	5947	}
	5948
[331]	5949	///////////////// Response FIFOs update //////////////////////
	5950	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
	5951	vci_rsp_fifo_icache_put,
	5952	vci_rsp_fifo_icache_data);
	5953
	5954	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
	5955	vci_rsp_fifo_dcache_put,
	5956	vci_rsp_fifo_dcache_data);
[346]	5957
[331]	5958	///////////////// updt FIFO update //////////////////////
	5959	//TODO check this
	5960	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
	5961	cc_receive_updt_fifo_put,
	5962	cc_receive_updt_fifo_be);
	5963	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
	5964	cc_receive_updt_fifo_put,
	5965	cc_receive_updt_fifo_data);
	5966	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
	5967	cc_receive_updt_fifo_put,
	5968	cc_receive_updt_fifo_eop);
	5969
	5970	} // end transition()
	5971
	5972	///////////////////////
	5973	tmpl(void)::genMoore()
	5974	///////////////////////
	5975	{
	5976
	5977	// VCI initiator command on the direct network
	5978	// it depends on the CMD FSM state
	5979
[336]	5980	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
[789]	5981	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
[336]	5982
[346]	5983	p_vci.pktid = 0;
	5984	p_vci.srcid = m_srcid;
[816]	5985	p_vci.cons = is_sc_or_cas;
	5986	p_vci.contig = not is_sc_or_cas;
[346]	5987	p_vci.wrap = false;
	5988	p_vci.clen = 0;
	5989	p_vci.cfixed = false;
[331]	5990
[789]	5991	if (m_monitor_ok) {
	5992	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
[816]	5993	if (((p_vci.address.read()) >= m_monitor_base) and
[789]	5994	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
[423]	5995	std::cout << "CC_VCACHE Monitor " << name() << std::hex
[816]	5996	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
[423]	5997	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
	5998	<< " : address = " << p_vci.address.read()
[816]	5999	<< " / be = " << p_vci.be.read();
[789]	6000	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
[423]	6001	std::cout << " / data = " << p_vci.wdata.read();
	6002	}
	6003	std::cout << std::dec << std::endl;
	6004	}
	6005	}
	6006	}
	6007
[789]	6008	switch (r_vci_cmd_fsm.read()) {
[331]	6009
	6010	case CMD_IDLE:
[346]	6011	p_vci.cmdval = false;
	6012	p_vci.address = 0;
	6013	p_vci.wdata = 0;
	6014	p_vci.be = 0;
	6015	p_vci.trdid = 0;
	6016	p_vci.pktid = 0;
	6017	p_vci.plen = 0;
	6018	p_vci.cmd = vci_param::CMD_NOP;
	6019	p_vci.eop = false;
[331]	6020	break;
	6021
	6022	case CMD_INS_MISS:
[346]	6023	p_vci.cmdval = true;
	6024	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
	6025	p_vci.wdata = 0;
	6026	p_vci.be = 0xF;
	6027	p_vci.trdid = 0;
	6028	p_vci.pktid = TYPE_READ_INS_MISS;
[836]	6029	p_vci.plen = m_icache_words << 2;
[346]	6030	p_vci.cmd = vci_param::CMD_READ;
	6031	p_vci.eop = true;
[331]	6032	break;
	6033
	6034	case CMD_INS_UNC:
[346]	6035	p_vci.cmdval = true;
	6036	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
	6037	p_vci.wdata = 0;
	6038	p_vci.be = 0xF;
	6039	p_vci.trdid = 0;
	6040	p_vci.pktid = TYPE_READ_INS_UNC;
	6041	p_vci.plen = 4;
	6042	p_vci.cmd = vci_param::CMD_READ;
	6043	p_vci.eop = true;
[331]	6044	break;
	6045
	6046	case CMD_DATA_MISS:
[346]	6047	p_vci.cmdval = true;
	6048	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
	6049	p_vci.wdata = 0;
	6050	p_vci.be = 0xF;
	6051	p_vci.trdid = 0;
	6052	p_vci.pktid = TYPE_READ_DATA_MISS;
	6053	p_vci.plen = m_dcache_words << 2;
	6054	p_vci.cmd = vci_param::CMD_READ;
	6055	p_vci.eop = true;
[331]	6056	break;
	6057
[616]	6058	case CMD_DATA_UNC_READ:
[346]	6059	p_vci.cmdval = true;
	6060	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
	6061	p_vci.wdata = 0;
	6062	p_vci.be = r_dcache_vci_unc_be.read();
	6063	p_vci.trdid = 0;
[616]	6064	p_vci.pktid = TYPE_DATA_UNC;
[346]	6065	p_vci.plen = 4;
	6066	p_vci.cmd = vci_param::CMD_READ;
	6067	p_vci.eop = true;
[331]	6068	break;
	6069
[616]	6070	case CMD_DATA_UNC_WRITE:
	6071	p_vci.cmdval = true;
	6072	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
	6073	p_vci.wdata = r_dcache_vci_wdata.read();
	6074	p_vci.be = r_dcache_vci_unc_be.read();
	6075	p_vci.trdid = 0;
	6076	p_vci.pktid = TYPE_DATA_UNC;
	6077	p_vci.plen = 4;
	6078	p_vci.cmd = vci_param::CMD_WRITE;
	6079	p_vci.eop = true;
	6080	break;
	6081
[331]	6082	case CMD_DATA_WRITE:
[346]	6083	p_vci.cmdval = true;
	6084	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
	6085	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
	6086	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
	6087	p_vci.trdid = r_wbuf.getIndex();
	6088	p_vci.pktid = TYPE_WRITE;
	6089	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
	6090	p_vci.cmd = vci_param::CMD_WRITE;
	6091	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
[331]	6092	break;
	6093
	6094	case CMD_DATA_LL:
[346]	6095	p_vci.cmdval = true;
	6096	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
	6097	p_vci.wdata = 0;
	6098	p_vci.be = 0xF;
	6099	p_vci.trdid = 0;
	6100	p_vci.pktid = TYPE_LL;
	6101	p_vci.plen = 8;
	6102	p_vci.cmd = vci_param::CMD_LOCKED_READ;
	6103	p_vci.eop = true;
[331]	6104	break;
	6105
	6106	case CMD_DATA_SC:
[346]	6107	p_vci.cmdval = true;
	6108	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
[789]	6109	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
	6110	else p_vci.wdata = r_dcache_vci_sc_data.read();
[346]	6111	p_vci.be = 0xF;
	6112	p_vci.trdid = 0;
	6113	p_vci.pktid = TYPE_SC;
	6114	p_vci.plen = 8;
	6115	p_vci.cmd = vci_param::CMD_NOP;
	6116	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
[331]	6117	break;
	6118
	6119	case CMD_DATA_CAS:
[346]	6120	p_vci.cmdval = true;
	6121	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
[789]	6122	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
	6123	else p_vci.wdata = r_dcache_vci_cas_new.read();
[346]	6124	p_vci.be = 0xF;
	6125	p_vci.trdid = 0;
	6126	p_vci.pktid = TYPE_CAS;
	6127	p_vci.plen = 8;
	6128	p_vci.cmd = vci_param::CMD_NOP;
	6129	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
[331]	6130	break;
	6131	} // end switch r_vci_cmd_fsm
	6132
	6133	// VCI initiator response on the direct network
[346]	6134	// it depends on the VCI_RSP FSM
[331]	6135
[789]	6136	switch (r_vci_rsp_fsm.read())
[331]	6137	{
[346]	6138	case RSP_DATA_WRITE : p_vci.rspack = true; break;
	6139	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
	6140	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
	6141	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
	6142	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
	6143	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
	6144	case RSP_IDLE : p_vci.rspack = false; break;
[331]	6145	} // end switch r_vci_rsp_fsm
	6146
[346]	6147
[816]	6148	// Send coherence packets on DSPIN P2M
	6149	// it depends on the CC_SEND FSM
	6150
[331]	6151	uint64_t dspin_send_data = 0;
[789]	6152	switch (r_cc_send_fsm.read())
[331]	6153	{
[346]	6154	//////////////////
[331]	6155	case CC_SEND_IDLE:
	6156	{
[468]	6157	p_dspin_p2m.write = false;
[331]	6158	break;
	6159	}
[346]	6160	///////////////////////
[331]	6161	case CC_SEND_CLEANUP_1:
	6162	{
	6163	// initialize dspin send data
[346]	6164	DspinDhccpParam::dspin_set(dspin_send_data,
	6165	m_cc_global_id,
	6166	DspinDhccpParam::CLEANUP_SRCID);
	6167	DspinDhccpParam::dspin_set(dspin_send_data,
	6168	0,
[468]	6169	DspinDhccpParam::P2M_BC);
[346]	6170
[789]	6171	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	6172	{
[816]	6173	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
	6174	>> (m_nline_width - m_x_width - m_y_width)
[346]	6175	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[816]	6176
[331]	6177	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6178	dest,
	6179	DspinDhccpParam::CLEANUP_DEST);
[331]	6180
	6181	DspinDhccpParam::dspin_set(dspin_send_data,
[394]	6182	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
[346]	6183	DspinDhccpParam::CLEANUP_NLINE_MSB);
[331]	6184
	6185	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6186	r_dcache_cc_send_way.read(),
	6187	DspinDhccpParam::CLEANUP_WAY_INDEX);
[331]	6188
	6189	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6190	DspinDhccpParam::TYPE_CLEANUP_DATA,
[468]	6191	DspinDhccpParam::P2M_TYPE);
[331]	6192	}
[346]	6193	else // icache active request
[331]	6194	{
[816]	6195	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
	6196	>> (m_nline_width - m_x_width - m_y_width)
[346]	6197	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[331]	6198
	6199	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6200	dest,
	6201	DspinDhccpParam::CLEANUP_DEST);
[331]	6202
	6203	DspinDhccpParam::dspin_set(dspin_send_data,
[789]	6204	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
[346]	6205	DspinDhccpParam::CLEANUP_NLINE_MSB);
[331]	6206
	6207	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6208	r_icache_cc_send_way.read(),
	6209	DspinDhccpParam::CLEANUP_WAY_INDEX);
[331]	6210
	6211	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6212	DspinDhccpParam::TYPE_CLEANUP_INST,
[468]	6213	DspinDhccpParam::P2M_TYPE);
[331]	6214	}
	6215	// send flit
[468]	6216	p_dspin_p2m.data = dspin_send_data;
	6217	p_dspin_p2m.write = true;
	6218	p_dspin_p2m.eop = false;
[331]	6219	break;
	6220	}
[346]	6221	///////////////////////
[331]	6222	case CC_SEND_CLEANUP_2:
	6223	{
	6224	// initialize dspin send data
[346]	6225
[789]	6226	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	6227	{
	6228	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6229	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
	6230	DspinDhccpParam::CLEANUP_NLINE_LSB);
[331]	6231	}
[346]	6232	else // icache active request
[331]	6233	{
	6234	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6235	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
	6236	DspinDhccpParam::CLEANUP_NLINE_LSB);
[331]	6237	}
	6238	// send flit
[468]	6239	p_dspin_p2m.data = dspin_send_data;
	6240	p_dspin_p2m.write = true;
	6241	p_dspin_p2m.eop = true;
[331]	6242	break;
	6243	}
[346]	6244	///////////////////////
[331]	6245	case CC_SEND_MULTI_ACK:
	6246	{
	6247	// initialize dspin send data
	6248	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6249	0,
[468]	6250	DspinDhccpParam::P2M_BC);
[346]	6251	DspinDhccpParam::dspin_set(dspin_send_data,
	6252	DspinDhccpParam::TYPE_MULTI_ACK,
[468]	6253	DspinDhccpParam::P2M_TYPE);
[346]	6254
[789]	6255	if (r_cc_send_last_client.read() == 0) // dcache active request
[331]	6256	{
[816]	6257	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
	6258	>> (m_nline_width - m_x_width - m_y_width)
[346]	6259	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[816]	6260
[331]	6261	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6262	dest,
	6263	DspinDhccpParam::MULTI_ACK_DEST);
[331]	6264
	6265	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6266	r_dcache_cc_send_updt_tab_idx.read(),
	6267	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
[331]	6268	}
[346]	6269	else // icache active request
[331]	6270	{
[816]	6271	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
	6272	>> (m_nline_width - m_x_width - m_y_width)
[346]	6273	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
[331]	6274
[816]	6275
[331]	6276	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6277	dest,
	6278	DspinDhccpParam::MULTI_ACK_DEST);
[331]	6279
	6280	DspinDhccpParam::dspin_set(dspin_send_data,
[346]	6281	r_icache_cc_send_updt_tab_idx.read(),
	6282	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
[331]	6283	}
	6284	// send flit
[468]	6285	p_dspin_p2m.data = dspin_send_data;
	6286	p_dspin_p2m.write = true;
	6287	p_dspin_p2m.eop = true;
[355]	6288
[331]	6289	break;
	6290	}
	6291	} // end switch CC_SEND FSM
	6292
[346]	6293	// Receive coherence packets
[816]	6294	// It depends on the CC_RECEIVE FSM
[789]	6295	switch (r_cc_receive_fsm.read())
[331]	6296	{
	6297	/////////////////////
	6298	case CC_RECEIVE_IDLE:
	6299	{
[468]	6300	p_dspin_m2p.read = false;
[331]	6301	break;
	6302	}
	6303	///////////////////////////////
	6304	case CC_RECEIVE_BRDCAST_HEADER:
	6305	{
[468]	6306	p_dspin_m2p.read = true;
[331]	6307	break;
	6308	}
	6309	//////////////////////////////
	6310	case CC_RECEIVE_BRDCAST_NLINE:
	6311	{
	6312	// TODO maybe we need to wait for both only to leave the state, but
	6313	// not to actually post a request to an available cache => need a
	6314	// flip_flop to check that ?
	6315	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
[468]	6316	p_dspin_m2p.read = true;
[331]	6317	else
[468]	6318	p_dspin_m2p.read = false;
[331]	6319	break;
	6320	}
	6321	/////////////////////////////
[468]	6322	case CC_RECEIVE_DATA_INVAL_HEADER:
	6323	case CC_RECEIVE_INS_INVAL_HEADER:
[331]	6324	{
[468]	6325	p_dspin_m2p.read = true;
[331]	6326	break;
	6327	}
	6328	////////////////////////////
[468]	6329	case CC_RECEIVE_DATA_INVAL_NLINE:
[331]	6330	{
[468]	6331	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
[331]	6332	break;
	6333	}
[468]	6334	case CC_RECEIVE_INS_INVAL_NLINE:
	6335	{
	6336	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
	6337	break;
	6338	}
	6339	///////////////////////////
	6340	case CC_RECEIVE_DATA_UPDT_HEADER:
	6341	{
	6342	if (not r_cc_receive_dcache_req.read())
	6343	p_dspin_m2p.read = true;
	6344	else
	6345	p_dspin_m2p.read = false;
	6346	break;
	6347	}
[331]	6348	////////////////////////////
[468]	6349	case CC_RECEIVE_INS_UPDT_HEADER:
[331]	6350	{
[816]	6351	if (not r_cc_receive_icache_req.read())
[468]	6352	p_dspin_m2p.read = true;
[331]	6353	else
[468]	6354	p_dspin_m2p.read = false;
[331]	6355	break;
	6356	}
	6357	///////////////////////////
[468]	6358	case CC_RECEIVE_DATA_UPDT_NLINE:
	6359	case CC_RECEIVE_INS_UPDT_NLINE:
[331]	6360	{
[789]	6361	if (r_cc_receive_updt_fifo_be.empty())
[468]	6362	p_dspin_m2p.read = true;
[331]	6363	else
[468]	6364	p_dspin_m2p.read = false;
[331]	6365	break;
	6366	}
[468]	6367	///////////////////////////
	6368	case CC_RECEIVE_DATA_UPDT_DATA:
	6369	case CC_RECEIVE_INS_UPDT_DATA:
[331]	6370	{
	6371	if (r_cc_receive_updt_fifo_be.wok())
[468]	6372	p_dspin_m2p.read = true;
[331]	6373	else
[468]	6374	p_dspin_m2p.read = false;
[331]	6375	break;
	6376	}
	6377	} // end switch CC_RECEIVE FSM
	6378
[468]	6379
	6380	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
	6381	DspinDhccpParam::CLACK_TYPE);
	6382
[789]	6383	bool dspin_clack_get = false;
[468]	6384	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
	6385	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
	6386
	6387	if (r_dspin_clack_req.read())
	6388	{
	6389	// CLACK DATA: wait if pending request to DCACHE FSM
	6390	if (dcache_clack_request and not r_dcache_clack_req.read())
	6391	{
	6392	dspin_clack_get = true;
	6393	}
	6394
	6395	// CLACK INST: wait if pending request to ICACHE FSM
	6396	else if (icache_clack_request and not r_icache_clack_req.read())
	6397	{
	6398	dspin_clack_get = true;
	6399	}
	6400	}
	6401	else
	6402	{
	6403	dspin_clack_get = true;
	6404	}
	6405
[816]	6406	p_dspin_clack.read = dspin_clack_get;
[331]	6407	} // end genMoore
	6408
[423]	6409	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
	6410	// This version of monitor print both Read and Write request
	6411	{
[789]	6412	m_monitor_ok = true;
	6413	m_monitor_base = base;
	6414	m_monitor_length = length;
[423]	6415	}
	6416
	6417	tmpl(void)::stop_monitor()
	6418	{
[789]	6419	m_monitor_ok = false;
[423]	6420	}
	6421
[331]	6422	}}
	6423
	6424	// Local Variables:
	6425	// tab-width: 4
	6426	// c-basic-offset: 4
	6427	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	6428	// indent-tabs-mode: nil
	6429	// End:
	6430
	6431	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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PO-Revision-Date: 2010-07-19 23:05+0200
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