Context Navigation

vci_cc_xcache_wrapper_v4.h @ 165

Last change on this file since 165 was 165, checked in by kane, 13 years ago
In vci_cc_xcache_wrapper : (1) fix compilation directive, (2) replace std::queue by generic_fifo, (3) delete vci_cc_xcache_wrapper_v4_cmp
Property svn:eol-style set to `native` Property svn:keywords set to `"Author Date Id Rev URL Revision"` Property svn:mime-type set to `text/plain`
File size: 19.7 KB

Rev	Line
[2]	1	/* -- c++ --
	2	*
	3	* SOCLIB_LGPL_HEADER_BEGIN
	4	*
	5	* This file is part of SoCLib, GNU LGPLv2.1.
	6	*
	7	* SoCLib is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU Lesser General Public License as published
	9	* by the Free Software Foundation; version 2.1 of the License.
	10	*
	11	* SoCLib is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with SoCLib; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* SOCLIB_LGPL_HEADER_END
	22	*
	23	* Copyright (c) UPMC, Lip6, SoC
	24	* Alain Greiner <alain.greiner@lip6.fr>, 2008
	25	*
	26	* Maintainers: alain
	27	*/
	28
	29	#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
	30	#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
	31
	32	#include <inttypes.h>
[165]	33	#include <fstream>
[2]	34	#include <systemc>
[134]	35	#include <queue>
[2]	36	#include "caba_base_module.h"
[134]	37	#include "multi_write_buffer.h"
[2]	38	#include "generic_cache.h"
[165]	39	#include "generic_fifo.h"
[2]	40	#include "vci_initiator.h"
	41	#include "vci_target.h"
	42	#include "mapping_table.h"
	43	#include "static_assert.h"
	44
[134]	45	/*
[165]	46	* ----------------------------------------------------------
	47	* Implementation
	48	* ----------------------------------------------------------
[147]	49	*
[165]	50	* CC_XCACHE_WRAPPER_MULTI_CACHE
	51	* 1 - icache static partitionnement
	52	* 2 - icache dedicated
[134]	53	*
[165]	54	* ----------------------------------------------------------
	55	* Debug
	56	* ----------------------------------------------------------
	57	*
	58	* CC_XCACHE_WRAPPER_STOP_SIMULATION
[134]	59	* stop simulation if processor is stall after a long time
	60	* (configurable with "stop_simulation" function)
	61	*
[165]	62	* CC_XCACHE_WRAPPER_DEBUG
[134]	63	* Add log to help the debugging
	64	*
[165]	65	* CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
[134]	66	* Number of cycle before to prinf debug message
	67	*
[165]	68	* CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
	69	* Print transaction between :
	70	* - the cpu and the cache (icache and dcache)
	71	* - vci
	72	* - cleanup
	73	* - coherency
	74	*
	75	* MWBUF_VHDL_TESTBENCH
	76	* generate a vhdl testbench for multi write buffer
[134]	77	*/
[2]	78
[134]	79	// implementation
[165]	80	#ifndef CC_XCACHE_WRAPPER_MULTI_CACHE
	81	#define CC_XCACHE_WRAPPER_MULTI_CACHE 2
	82	// if multi_cache :
	83	// <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1
[147]	84	#endif
[165]	85
	86	// debug
[134]	87	#ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION
[165]	88	#define CC_XCACHE_WRAPPER_STOP_SIMULATION 1
[134]	89	#endif
	90	#ifndef CC_XCACHE_WRAPPER_DEBUG
[165]	91	#define CC_XCACHE_WRAPPER_DEBUG 0
[134]	92	#endif
	93	#ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN
[165]	94	#define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 4725000
[134]	95	#endif
[165]	96	#ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
	97	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0
	98	#define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log"
[134]	99	#endif
[165]	100	#ifndef MWBUF_VHDL_TESTBENCH
	101	#define MWBUF_VHDL_TESTBENCH 0
	102	#endif
[134]	103
[2]	104	namespace soclib {
	105	namespace caba {
	106
	107	using namespace sc_core;
	108
	109	////////////////////////////////////////////
	110	template<typename vci_param, typename iss_t>
	111	class VciCcXCacheWrapperV4
	112	///////////////////////////////////////////
	113	: public soclib::caba::BaseModule
	114	{
[165]	115	typedef uint64_t vhdl_tb_t;
[90]	116	typedef sc_dt::sc_uint<40> addr_40;
	117	typedef uint32_t data_t;
	118	typedef uint32_t tag_t;
	119	typedef uint32_t be_t;
[2]	120	typedef typename vci_param::fast_addr_t vci_addr_t;
[165]	121	typedef enum
	122	{
	123	WRITE_THROUGH,
	124	RELEASE_WRITE_THROUGH
	125	} write_policy_t;
	126
[2]	127	enum dcache_fsm_state_e {
	128	DCACHE_IDLE,
	129	DCACHE_WRITE_UPDT,
[134]	130	DCACHE_MISS_VICTIM,
[2]	131	DCACHE_MISS_WAIT,
	132	DCACHE_MISS_UPDT,
	133	DCACHE_UNC_WAIT,
	134	DCACHE_SC_WAIT,
	135	DCACHE_INVAL,
[134]	136	DCACHE_SYNC,
[2]	137	DCACHE_ERROR,
	138	DCACHE_CC_CHECK,
	139	DCACHE_CC_INVAL,
	140	DCACHE_CC_UPDT,
	141	DCACHE_CC_CLEANUP,
	142	};
	143
	144	enum icache_fsm_state_e {
	145	ICACHE_IDLE,
[134]	146	ICACHE_MISS_VICTIM,
[2]	147	ICACHE_MISS_WAIT,
	148	ICACHE_MISS_UPDT,
	149	ICACHE_UNC_WAIT,
	150	ICACHE_ERROR,
	151	ICACHE_CC_CLEANUP,
	152	ICACHE_CC_CHECK,
	153	ICACHE_CC_INVAL,
	154	ICACHE_CC_UPDT,
	155	};
	156
	157	enum cmd_fsm_state_e {
	158	CMD_IDLE,
	159	CMD_INS_MISS,
	160	CMD_INS_UNC,
	161	CMD_DATA_MISS,
	162	CMD_DATA_UNC,
	163	CMD_DATA_WRITE,
	164	CMD_DATA_SC,
	165	};
	166
	167	enum rsp_fsm_state_e {
	168	RSP_IDLE,
	169	RSP_INS_MISS,
	170	RSP_INS_UNC,
	171	RSP_DATA_MISS,
	172	RSP_DATA_UNC,
	173	RSP_DATA_WRITE,
	174	RSP_DATA_SC,
	175	};
	176
	177	enum tgt_fsm_state_e {
	178	TGT_IDLE,
	179	TGT_UPDT_WORD,
	180	TGT_UPDT_DATA,
	181	TGT_REQ_BROADCAST,
	182	TGT_REQ_ICACHE,
	183	TGT_REQ_DCACHE,
	184	TGT_RSP_BROADCAST,
	185	TGT_RSP_ICACHE,
	186	TGT_RSP_DCACHE,
	187	};
	188
[134]	189	enum cleanup_fsm_state_e {
	190	CLEANUP_IDLE,
[165]	191	CLEANUP_REQ,
	192	CLEANUP_RSP_DCACHE,
	193	CLEANUP_RSP_ICACHE,
[134]	194	};
	195
	196	enum transaction_type_c_e {
	197	// convention with memcache
	198	TYPE_DATA_CLEANUP = 0x0,
	199	TYPE_INS_CLEANUP = 0x1
	200	};
	201
	202	enum transaction_type_rw_e {
	203	// convention with memcache
	204	// b0 : 1 if cached
	205	// b1 : 1 if instruction
	206	// b2 : 1 if sc
	207	TYPE_DATA_UNC = 0x0,
	208	TYPE_DATA_MISS = 0x1,
	209	TYPE_INS_UNC = 0x2,
	210	TYPE_INS_MISS = 0x3,
	211	TYPE_DATA_SC = 0x4, // sc is data and no cached
	212	};
	213
[2]	214	public:
	215
	216	// PORTS
	217	sc_in<bool> p_clk;
	218	sc_in<bool> p_resetn;
[165]	219	sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq];
[2]	220	soclib::caba::VciInitiator<vci_param> p_vci_ini_rw;
	221	soclib::caba::VciInitiator<vci_param> p_vci_ini_c;
	222	soclib::caba::VciTarget<vci_param> p_vci_tgt;
	223
	224	private:
	225
	226	// STRUCTURAL PARAMETERS
	227	const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table;
	228	const soclib::common::Segment m_segment;
[165]	229	iss_t ** m_iss; //[m_nb_cpu]
[2]	230	const uint32_t m_srcid_rw;
	231	const uint32_t m_srcid_c;
	232
[165]	233	const size_t m_nb_cpu;
	234	const size_t m_nb_icache;
	235	const size_t m_nb_dcache;
	236	const size_t m_nb_cache;
	237	const size_t m_dcache_ways;
	238	const size_t m_dcache_words;
	239	const uint32_t m_dcache_words_shift;
	240	const size_t m_dcache_yzmask;
	241	const size_t m_icache_ways;
	242	const size_t m_icache_words;
	243	const uint32_t m_icache_words_shift;
	244	const size_t m_icache_yzmask;
	245	const write_policy_t m_write_policy;
	246	const size_t m_cache_words; // max between m_dcache_words and m_icache_words
[2]	247
[134]	248	#if CC_XCACHE_WRAPPER_STOP_SIMULATION
	249	bool m_stop_simulation;
	250	uint32_t m_stop_simulation_nb_frz_cycles_max;
[165]	251	uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu]
[134]	252	#endif // CC_XCACHE_WRAPPER_STOP_SIMULATION
	253
[2]	254	// REGISTERS
[165]	255	sc_signal<uint32_t> r_cpu_prior;
	256	sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache]
	257	sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache]
	258	sc_signal<bool> * r_dcache_sync;//[m_nb_dcache]
[2]	259
[165]	260	sc_signal<int> * r_dcache_fsm; //[m_nb_dcache]
	261	sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache]
	262	sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache]
	263	sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache]
	264	sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache]
	265	sc_signal<int> * r_dcache_type_save; //[m_nb_dcache]
	266	sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache]
	267	sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache]
	268	sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache]
	269	sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache]
	270	sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache]
	271	sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache]
	272	sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache]
	273	sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache]
	274	sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache]
	275	sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache]
	276	sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache]
	277	sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache]
	278	sc_signal<data_t> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu]
	279	sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu]
	280	sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu]
	281	sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache]
	282
	283	sc_signal<int> * r_icache_fsm; //[m_nb_icache]
	284	sc_signal<int> * r_icache_fsm_save; //[m_nb_icache]
	285	sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache]
	286	sc_signal<bool> * r_icache_miss_req; //[m_nb_icache]
	287	sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache]
	288	sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache]
	289	sc_signal<bool> * r_icache_unc_req; //[m_nb_icache]
	290	sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache]
	291	sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache]
	292	sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache]
	293	sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache]
	294	sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache]
[2]	295
	296	sc_signal<int> r_vci_cmd_fsm;
	297	sc_signal<size_t> r_vci_cmd_min;
	298	sc_signal<size_t> r_vci_cmd_max;
	299	sc_signal<size_t> r_vci_cmd_cpt;
[134]	300	sc_signal<bool> r_vci_cmd_dcache_prior;
[165]	301	sc_signal<uint32_t> r_vci_cmd_num_icache_prior;
	302	sc_signal<uint32_t> r_vci_cmd_num_dcache_prior;
	303	sc_signal<uint32_t> r_vci_cmd_num_cache;
	304
[2]	305	sc_signal<int> r_vci_rsp_fsm;
	306	sc_signal<size_t> r_vci_rsp_cpt;
[165]	307	sc_signal<uint32_t> r_vci_rsp_num_cache;
	308	sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache]
	309	sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache]
[2]	310
[165]	311	GenericFifo<data_t> r_vci_rsp_fifo_icache_data;
	312	GenericFifo<uint32_t> r_vci_rsp_fifo_icache_num_cache;
	313	GenericFifo<data_t> r_vci_rsp_fifo_dcache_data;
	314	GenericFifo<uint32_t> r_vci_rsp_fifo_dcache_num_cache;
[147]	315
[165]	316	data_t * r_tgt_buf; //[m_cache_words]
	317	be_t * r_tgt_be; //[m_cache_words]
[134]	318	sc_signal<uint32_t> r_cache_word;
[2]	319
	320	sc_signal<int> r_vci_tgt_fsm;
[165]	321	sc_signal<addr_40> r_tgt_iaddr;
	322	sc_signal<addr_40> r_tgt_daddr;
[2]	323	sc_signal<size_t> r_tgt_word;
	324	sc_signal<bool> r_tgt_update;
	325	sc_signal<bool> r_tgt_update_data;
[134]	326	//sc_signal<bool> r_tgt_brdcast;
[2]	327	sc_signal<size_t> r_tgt_srcid;
	328	sc_signal<size_t> r_tgt_pktid;
	329	sc_signal<size_t> r_tgt_trdid;
[134]	330	//sc_signal<size_t> r_tgt_plen;
[165]	331	sc_signal<uint32_t> r_tgt_num_cache;
	332	sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache]
	333	sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache]
	334	sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache]
	335	sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache]
[2]	336
[134]	337	sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network
[165]	338	sc_signal<uint32_t> r_cleanup_num_cache;
	339	sc_signal<bool> r_cleanup_icache;
[134]	340
[165]	341	MultiWriteBuffer<addr_40>** r_wbuf;
	342	GenericCache<vci_addr_t> ** r_icache;
	343	GenericCache<vci_addr_t> ** r_dcache;
[2]	344
[165]	345	#if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION
	346	bool generate_log_transaction_file_icache;
	347	bool generate_log_transaction_file_dcache;
	348	bool generate_log_transaction_file_cmd;
	349	bool generate_log_transaction_file_tgt;
	350	bool generate_log_transaction_file_cleanup;
	351
	352	std::ofstream * log_transaction_file_icache; //[m_nb_cpu]
	353	std::ofstream * log_transaction_file_dcache; //[m_nb_cpu]
	354	std::ofstream log_transaction_file_cmd;
	355	std::ofstream log_transaction_file_tgt;
	356	std::ofstream log_transaction_file_cleanup;
[134]	357	#endif
	358
[165]	359	#if MWBUF_VHDL_TESTBENCH
	360	bool simulation_started;
	361	bool generate_vhdl_testbench_mwbuf;
	362	std::ofstream * vhdl_testbench_mwbuf; //[m_nb_dcache]
	363	#endif
	364
[2]	365	// Activity counters
[165]	366	uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ
	367	uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE
	368	uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ
	369	uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE
	370
	371	uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ
	372	uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE
	373	uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ
	374	uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE
	375
	376	uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache)
	377	uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache)
	378	uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets
	379	uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets
	380	uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets
	381	uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets
	382	uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets
	383
	384	uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen
	385	uint32_t m_cpt_total_cycles; // total number of cycles
	386
	387	uint32_t m_cpt_data_read; // number of data read
	388	uint32_t m_cpt_data_read_miss; // number of data read miss
	389	uint32_t m_cpt_data_read_uncached; // number of data read uncached
	390	uint32_t m_cpt_data_write; // number of data write
	391	uint32_t m_cpt_data_write_miss; // number of data write miss
	392	uint32_t m_cpt_data_write_uncached; // number of data write uncached
	393	uint32_t m_cpt_ins_miss; // * number of instruction miss
	394
	395	uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer
	396	uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss
	397	uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read
	398	uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss
	399
	400	uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions
	401	uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions
	402	uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions
	403	uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions
	404
	405	uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions
	406	uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions
	407	uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions
	408	uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions
	409	uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions
[2]	410
[165]	411	uint32_t * m_cpt_icache_access; //[m_nb_icache]
	412	uint32_t * m_cpt_dcache_access; //[m_nb_dcache]
	413	uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache]
	414	uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache]
	415	uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache]
	416	uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache]
	417	uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache]
[2]	418
[165]	419	uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache]
	420	uint32_t ** m_cpt_fsm_icache; //[m_nb_icache]
	421	uint32_t * m_cpt_fsm_cmd;
	422	uint32_t * m_cpt_fsm_rsp;
	423	uint32_t * m_cpt_fsm_tgt;
	424	uint32_t * m_cpt_fsm_cleanup;
[2]	425
[165]	426	// Non blocking multi-cache
	427	typename iss_t::InstructionRequest * ireq ; //[m_nb_icache]
	428	typename iss_t::InstructionResponse * irsp ; //[m_nb_icache]
	429	bool * ireq_cached ; //[m_nb_icache]
	430	uint32_t * ireq_num_cpu; //[m_nb_dcache]
	431	typename iss_t::DataRequest * dreq ; //[m_nb_dcache]
	432	typename iss_t::DataResponse * drsp ; //[m_nb_dcache]
	433	bool * dreq_cached ; //[m_nb_dcache]
	434	uint32_t * dreq_num_cpu; //[m_nb_dcache]
[2]	435
[165]	436	const uint32_t m_num_cache_LSB;
	437	const uint32_t m_num_cache_MSB;
	438	addr_40 m_num_cache_LSB_mask;
	439	addr_40 m_num_cache_mask;
[2]	440
	441	protected:
	442	SC_HAS_PROCESS(VciCcXCacheWrapperV4);
	443
	444	public:
	445
	446	VciCcXCacheWrapperV4(
	447	sc_module_name insname,
	448	int proc_id,
	449	const soclib::common::MappingTable &mtp,
	450	const soclib::common::MappingTable &mtc,
	451	const soclib::common::IntTab &initiator_index_rw,
	452	const soclib::common::IntTab &initiator_index_c,
	453	const soclib::common::IntTab &target_index,
[165]	454	size_t nb_cpu,
	455	size_t nb_dcache,
[2]	456	size_t icache_ways,
	457	size_t icache_sets,
	458	size_t icache_words,
	459	size_t dcache_ways,
	460	size_t dcache_sets,
[134]	461	size_t dcache_words,
	462	size_t wbuf_nwords,
	463	size_t wbuf_nlines,
[165]	464	size_t wbuf_timeout,
	465	write_policy_t write_policy=WRITE_THROUGH
[134]	466	);
[2]	467
	468	~VciCcXCacheWrapperV4();
	469
[165]	470	void print_trace(size_t mode = 0);
	471	void print_cpi();
	472	void print_stats(bool print_wbuf=true, bool print_fsm=true);
[2]	473
[165]	474	void stop_simulation (uint32_t);
	475	void log_transaction ( bool generate_file_icache
	476	,bool generate_file_dcache
	477	,bool generate_file_cmd
	478	,bool generate_file_tgt
	479	,bool generate_file_cleanup);
[134]	480
[165]	481	void vhdl_testbench (bool generate_file_mwbuf);
	482
[2]	483	private:
	484
	485	void transition();
	486	void genMoore();
	487
[165]	488	uint32_t get_num_cache (addr_40 & addr);
	489	uint32_t get_num_cache_only(addr_40 addr);
	490	void set_num_cache (addr_40 & addr, uint32_t num_cache);
	491	addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache);
	492
	493	soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
[2]	494	soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
	495	};
	496
	497	}}
	498
	499	#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H */
	500
	501	// Local Variables:
	502	// tab-width: 4
	503	// c-basic-offset: 4
	504	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	505	// indent-tabs-mode: nil
	506	// End:
	507
	508	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format