Changeset 165 for trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
- Timestamp:
- May 11, 2011, 1:36:38 PM (13 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
r147 r165 31 31 32 32 #include <inttypes.h> 33 #include <fstream> 33 34 #include <systemc> 34 35 #include <queue> … … 36 37 #include "multi_write_buffer.h" 37 38 #include "generic_cache.h" 39 #include "generic_fifo.h" 38 40 #include "vci_initiator.h" 39 41 #include "vci_target.h" … … 42 44 43 45 /* 44 * CC_XCACHE_WRAPPER_SELECT_VICTIM : 45 * The selection and the update of cache (after a read miss) 46 * are separated in two step 47 * Also, the cleanup can be send in parallel at the read miss. 48 * 49 * CC_XCACHE_WRAPPER_FIFO_RSP 50 * Two simple fifo (each 2x32 depth) receive the cache line from 51 * RAM. Instead of two buffers (m_icache_words and m_dcache_words) 52 * 53 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 54 * Update cache in "2*cache_words" cycles (read+mask, write) 55 * 56 * CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 57 * Update cache with only modified data (be != 0) 58 * 59 * CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 60 * Write buffer scheme for update step : 61 * 1 - multi_scan 62 * 2 - round_robin_scan 63 * 3 - one_scan 64 * else - default scheme 65 * 66 * CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 67 * Write buffer access is conditionnal with dcache_miss_req and icache_miss_req 68 * 1 - two access authorized 69 * 2 - one access with static priority (dcache prior) 70 * 3 - one access with static priority (icache prior) 71 * 4 - one access with round robin priority 72 * 73 * CC_XCACHE_WRAPPER_STOP_SIMULATION : 46 * ---------------------------------------------------------- 47 * Implementation 48 * ---------------------------------------------------------- 49 * 50 * CC_XCACHE_WRAPPER_MULTI_CACHE 51 * 1 - icache static partitionnement 52 * 2 - icache dedicated 53 * 54 * ---------------------------------------------------------- 55 * Debug 56 * ---------------------------------------------------------- 57 * 58 * CC_XCACHE_WRAPPER_STOP_SIMULATION 74 59 * stop simulation if processor is stall after a long time 75 60 * (configurable with "stop_simulation" function) 76 61 * 77 * CC_XCACHE_WRAPPER_DEBUG :62 * CC_XCACHE_WRAPPER_DEBUG 78 63 * Add log to help the debugging 79 64 * 80 * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN :65 * CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 81 66 * Number of cycle before to prinf debug message 82 67 * 83 * CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 84 * Print transaction between the cpu and the cache 68 * CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 69 * Print transaction between : 70 * - the cpu and the cache (icache and dcache) 71 * - vci 72 * - cleanup 73 * - coherency 74 * 75 * MWBUF_VHDL_TESTBENCH 76 * generate a vhdl testbench for multi write buffer 85 77 */ 86 78 87 79 // implementation 88 #ifndef CC_XCACHE_WRAPPER_SELECT_VICTIM 89 #define CC_XCACHE_WRAPPER_SELECT_VICTIM 0 90 #endif 91 #ifndef CC_XCACHE_WRAPPER_FIFO_RSP 92 #define CC_XCACHE_WRAPPER_FIFO_RSP 0 93 #endif 94 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 95 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 1 96 #endif 97 #ifndef CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 98 #define CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE_OPT 1 99 #endif 100 #ifndef CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 101 #define CC_XCACHE_WRAPPER_WBUF_UPDATE_SCHEME 0 102 #endif 103 #ifndef CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 104 #define CC_XCACHE_WRAPPER_VCI_CMD_PRIORITY 2 105 #endif 106 // debugging 80 #ifndef CC_XCACHE_WRAPPER_MULTI_CACHE 81 #define CC_XCACHE_WRAPPER_MULTI_CACHE 2 82 // if multi_cache : 83 // <tsar toplevel>/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h : L1_MULTI_CACHE 1 84 #endif 85 86 // debug 107 87 #ifndef CC_XCACHE_WRAPPER_STOP_SIMULATION 108 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 188 #define CC_XCACHE_WRAPPER_STOP_SIMULATION 1 109 89 #endif 110 90 #ifndef CC_XCACHE_WRAPPER_DEBUG 111 #define CC_XCACHE_WRAPPER_DEBUG 091 #define CC_XCACHE_WRAPPER_DEBUG 0 112 92 #endif 113 93 #ifndef CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 114 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 200000 115 #endif 116 #ifndef CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 117 #define CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 0 94 #define CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN 4725000 95 #endif 96 #ifndef CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 97 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 0 98 #define CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION_PATH "log" 99 #endif 100 #ifndef MWBUF_VHDL_TESTBENCH 101 #define MWBUF_VHDL_TESTBENCH 0 118 102 #endif 119 103 … … 129 113 : public soclib::caba::BaseModule 130 114 { 115 typedef uint64_t vhdl_tb_t; 131 116 typedef sc_dt::sc_uint<40> addr_40; 132 typedef sc_dt::sc_uint<64> data_64;133 117 typedef uint32_t data_t; 134 118 typedef uint32_t tag_t; 135 119 typedef uint32_t be_t; 136 120 typedef typename vci_param::fast_addr_t vci_addr_t; 137 121 typedef enum 122 { 123 WRITE_THROUGH, 124 RELEASE_WRITE_THROUGH 125 } write_policy_t; 126 138 127 enum dcache_fsm_state_e { 139 128 DCACHE_IDLE, 140 129 DCACHE_WRITE_UPDT, 141 #if CC_XCACHE_WRAPPER_SELECT_VICTIM142 130 DCACHE_MISS_VICTIM, 143 #endif144 131 DCACHE_MISS_WAIT, 145 132 DCACHE_MISS_UPDT, … … 157 144 enum icache_fsm_state_e { 158 145 ICACHE_IDLE, 159 #if CC_XCACHE_WRAPPER_SELECT_VICTIM160 146 ICACHE_MISS_VICTIM, 161 #endif162 147 ICACHE_MISS_WAIT, 163 148 ICACHE_MISS_UPDT, … … 204 189 enum cleanup_fsm_state_e { 205 190 CLEANUP_IDLE, 206 CLEANUP_DCACHE, 207 CLEANUP_ICACHE, 191 CLEANUP_REQ, 192 CLEANUP_RSP_DCACHE, 193 CLEANUP_RSP_ICACHE, 208 194 }; 209 195 … … 231 217 sc_in<bool> p_clk; 232 218 sc_in<bool> p_resetn; 233 sc_in<bool> p_irq[iss_t::n_irq];219 sc_in<bool> ** p_irq;//[m_nb_cpu][iss_t::n_irq]; 234 220 soclib::caba::VciInitiator<vci_param> p_vci_ini_rw; 235 221 soclib::caba::VciInitiator<vci_param> p_vci_ini_c; … … 241 227 const soclib::common::AddressDecodingTable<vci_addr_t, bool> m_cacheability_table; 242 228 const soclib::common::Segment m_segment; 243 iss_t m_iss;229 iss_t ** m_iss; //[m_nb_cpu] 244 230 const uint32_t m_srcid_rw; 245 231 const uint32_t m_srcid_c; 246 232 247 const size_t m_dcache_ways; 248 const size_t m_dcache_words; 249 const uint32_t m_dcache_words_shift; 250 const size_t m_dcache_yzmask; 251 const size_t m_icache_ways; 252 const size_t m_icache_words; 253 const uint32_t m_icache_words_shift; 254 const size_t m_icache_yzmask; 255 const size_t m_cache_words; // max between m_dcache_words and m_icache_words 233 const size_t m_nb_cpu; 234 const size_t m_nb_icache; 235 const size_t m_nb_dcache; 236 const size_t m_nb_cache; 237 const size_t m_dcache_ways; 238 const size_t m_dcache_words; 239 const uint32_t m_dcache_words_shift; 240 const size_t m_dcache_yzmask; 241 const size_t m_icache_ways; 242 const size_t m_icache_words; 243 const uint32_t m_icache_words_shift; 244 const size_t m_icache_yzmask; 245 const write_policy_t m_write_policy; 246 const size_t m_cache_words; // max between m_dcache_words and m_icache_words 256 247 257 248 #if CC_XCACHE_WRAPPER_STOP_SIMULATION 258 249 bool m_stop_simulation; 259 250 uint32_t m_stop_simulation_nb_frz_cycles_max; 260 uint32_t m_stop_simulation_nb_frz_cycles;251 uint32_t * m_stop_simulation_nb_frz_cycles; //[m_nb_cpu] 261 252 #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 262 253 263 254 // REGISTERS 264 sc_signal<int> r_dcache_fsm; 265 sc_signal<int> r_dcache_fsm_save; 266 sc_signal<addr_40> r_dcache_addr_save; 267 sc_signal<data_t> r_dcache_wdata_save; 268 sc_signal<data_t> r_dcache_rdata_save; 269 sc_signal<int> r_dcache_type_save; 270 sc_signal<be_t> r_dcache_be_save; 271 sc_signal<bool> r_dcache_cached_save; 272 sc_signal<bool> r_dcache_cleanup_req; 273 sc_signal<addr_40> r_dcache_cleanup_line; 274 sc_signal<bool> r_dcache_miss_req; 275 sc_signal<size_t> r_dcache_miss_way; 276 sc_signal<size_t> r_dcache_miss_set; 277 sc_signal<bool> r_dcache_unc_req; 278 sc_signal<bool> r_dcache_sc_req; 279 sc_signal<bool> r_dcache_inval_rsp; 280 sc_signal<size_t> r_dcache_update_addr; 281 sc_signal<data_64> r_dcache_ll_data; 282 sc_signal<addr_40> r_dcache_ll_addr; 283 sc_signal<bool> r_dcache_ll_valid; 284 sc_signal<bool> r_dcache_previous_unc; 285 286 sc_signal<int> r_icache_fsm; 287 sc_signal<int> r_icache_fsm_save; 288 sc_signal<addr_40> r_icache_addr_save; 289 sc_signal<bool> r_icache_miss_req; 290 sc_signal<size_t> r_icache_miss_way; 291 sc_signal<size_t> r_icache_miss_set; 292 sc_signal<bool> r_icache_unc_req; 293 sc_signal<bool> r_icache_cleanup_req; 294 sc_signal<addr_40> r_icache_cleanup_line; 295 sc_signal<bool> r_icache_inval_rsp; 296 sc_signal<size_t> r_icache_update_addr; 255 sc_signal<uint32_t> r_cpu_prior; 256 sc_signal<uint32_t> * r_icache_lock;//[m_nb_icache] 257 sc_signal<uint32_t> * r_dcache_lock;//[m_nb_dcache] 258 sc_signal<bool> * r_dcache_sync;//[m_nb_dcache] 259 260 sc_signal<int> * r_dcache_fsm; //[m_nb_dcache] 261 sc_signal<int> * r_dcache_fsm_save; //[m_nb_dcache] 262 sc_signal<addr_40> * r_dcache_addr_save; //[m_nb_dcache] 263 sc_signal<data_t> * r_dcache_wdata_save; //[m_nb_dcache] 264 sc_signal<data_t> * r_dcache_rdata_save; //[m_nb_dcache] 265 sc_signal<int> * r_dcache_type_save; //[m_nb_dcache] 266 sc_signal<be_t> * r_dcache_be_save; //[m_nb_dcache] 267 sc_signal<bool> * r_dcache_cached_save; //[m_nb_dcache] 268 sc_signal<uint32_t> * r_dcache_num_cpu_save; //[m_nb_dcache] 269 sc_signal<bool> * r_dcache_cleanup_req; //[m_nb_dcache] 270 sc_signal<addr_40> * r_dcache_cleanup_line; //[m_nb_dcache] 271 sc_signal<bool> * r_dcache_miss_req; //[m_nb_dcache] 272 sc_signal<size_t> * r_dcache_miss_way; //[m_nb_dcache] 273 sc_signal<size_t> * r_dcache_miss_set; //[m_nb_dcache] 274 sc_signal<bool> * r_dcache_unc_req; //[m_nb_dcache] 275 sc_signal<bool> * r_dcache_sc_req; //[m_nb_dcache] 276 sc_signal<bool> * r_dcache_inval_rsp; //[m_nb_dcache] 277 sc_signal<size_t> * r_dcache_update_addr; //[m_nb_dcache] 278 sc_signal<data_t> ** r_dcache_ll_data; //[m_nb_dcache][m_nb_cpu] 279 sc_signal<addr_40> ** r_dcache_ll_addr; //[m_nb_dcache][m_nb_cpu] 280 sc_signal<bool> ** r_dcache_ll_valid; //[m_nb_dcache][m_nb_cpu] 281 sc_signal<bool> * r_dcache_previous_unc; //[m_nb_dcache] 282 283 sc_signal<int> * r_icache_fsm; //[m_nb_icache] 284 sc_signal<int> * r_icache_fsm_save; //[m_nb_icache] 285 sc_signal<addr_40> * r_icache_addr_save; //[m_nb_icache] 286 sc_signal<bool> * r_icache_miss_req; //[m_nb_icache] 287 sc_signal<size_t> * r_icache_miss_way; //[m_nb_icache] 288 sc_signal<size_t> * r_icache_miss_set; //[m_nb_icache] 289 sc_signal<bool> * r_icache_unc_req; //[m_nb_icache] 290 sc_signal<bool> * r_icache_cleanup_req; //[m_nb_icache] 291 sc_signal<addr_40> * r_icache_cleanup_line; //[m_nb_icache] 292 sc_signal<bool> * r_icache_inval_rsp; //[m_nb_icache] 293 sc_signal<size_t> * r_icache_update_addr; //[m_nb_icache] 294 sc_signal<bool> * r_icache_buf_unc_valid;//[m_nb_icache] 297 295 298 296 sc_signal<int> r_vci_cmd_fsm; … … 301 299 sc_signal<size_t> r_vci_cmd_cpt; 302 300 sc_signal<bool> r_vci_cmd_dcache_prior; 303 301 sc_signal<uint32_t> r_vci_cmd_num_icache_prior; 302 sc_signal<uint32_t> r_vci_cmd_num_dcache_prior; 303 sc_signal<uint32_t> r_vci_cmd_num_cache; 304 304 305 sc_signal<int> r_vci_rsp_fsm; 305 sc_signal<bool> r_vci_rsp_ins_error;306 sc_signal<bool> r_vci_rsp_data_error;307 306 sc_signal<size_t> r_vci_rsp_cpt; 308 sc_signal<bool> r_vci_rsp_ack; 309 310 #if CC_XCACHE_WRAPPER_FIFO_RSP 311 std::queue<data_t> r_icache_miss_buf; 312 std::queue<data_t> r_dcache_miss_buf; 313 #else 314 bool *r_icache_miss_val; //[m_icache_words] 315 data_t *r_icache_miss_buf; //[m_icache_words] 316 bool *r_dcache_miss_val; //[m_dcache_words] 317 data_t *r_dcache_miss_buf; //[m_dcache_words] 318 #endif 319 sc_signal<bool> r_icache_buf_unc_valid; 320 321 data_t *r_tgt_buf; //[m_cache_words] 322 be_t *r_tgt_be; //[m_cache_words] 323 #if CC_XCACHE_WRAPPER_CC_UPDATE_MULTI_CYCLE 307 sc_signal<uint32_t> r_vci_rsp_num_cache; 308 sc_signal<bool> * r_vci_rsp_ins_error; //[m_nb_icache] 309 sc_signal<bool> * r_vci_rsp_data_error; //[m_nb_dcache] 310 311 GenericFifo<data_t> r_vci_rsp_fifo_icache_data; 312 GenericFifo<uint32_t> r_vci_rsp_fifo_icache_num_cache; 313 GenericFifo<data_t> r_vci_rsp_fifo_dcache_data; 314 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache_num_cache; 315 316 data_t * r_tgt_buf; //[m_cache_words] 317 be_t * r_tgt_be; //[m_cache_words] 324 318 sc_signal<uint32_t> r_cache_word; 325 #endif326 319 327 320 sc_signal<int> r_vci_tgt_fsm; 328 sc_signal<addr_40> r_tgt_addr; 321 sc_signal<addr_40> r_tgt_iaddr; 322 sc_signal<addr_40> r_tgt_daddr; 329 323 sc_signal<size_t> r_tgt_word; 330 324 sc_signal<bool> r_tgt_update; … … 335 329 sc_signal<size_t> r_tgt_trdid; 336 330 //sc_signal<size_t> r_tgt_plen; 337 sc_signal<bool> r_tgt_icache_req; 338 sc_signal<bool> r_tgt_dcache_req; 339 sc_signal<bool> r_tgt_icache_rsp; 340 sc_signal<bool> r_tgt_dcache_rsp; 331 sc_signal<uint32_t> r_tgt_num_cache; 332 sc_signal<bool> * r_tgt_icache_req; //[m_nb_icache] 333 sc_signal<bool> * r_tgt_icache_rsp; //[m_nb_icache] 334 sc_signal<bool> * r_tgt_dcache_req; //[m_nb_dcache] 335 sc_signal<bool> * r_tgt_dcache_rsp; //[m_nb_dcache] 341 336 342 337 sc_signal<int> r_cleanup_fsm; // controls initiator port of the coherence network 343 344 MultiWriteBuffer<addr_40> r_wbuf; 345 GenericCache<vci_addr_t> r_icache; 346 GenericCache<vci_addr_t> r_dcache; 347 348 #if CC_XCACHE_WRAPPER_DEBUG_DCACHE_TRANSACTION 349 std::ofstream log_dcache_transaction_file; 338 sc_signal<uint32_t> r_cleanup_num_cache; 339 sc_signal<bool> r_cleanup_icache; 340 341 MultiWriteBuffer<addr_40>** r_wbuf; 342 GenericCache<vci_addr_t> ** r_icache; 343 GenericCache<vci_addr_t> ** r_dcache; 344 345 #if CC_XCACHE_WRAPPER_DEBUG_FILE_TRANSACTION 346 bool generate_log_transaction_file_icache; 347 bool generate_log_transaction_file_dcache; 348 bool generate_log_transaction_file_cmd; 349 bool generate_log_transaction_file_tgt; 350 bool generate_log_transaction_file_cleanup; 351 352 std::ofstream * log_transaction_file_icache; //[m_nb_cpu] 353 std::ofstream * log_transaction_file_dcache; //[m_nb_cpu] 354 std::ofstream log_transaction_file_cmd; 355 std::ofstream log_transaction_file_tgt; 356 std::ofstream log_transaction_file_cleanup; 357 #endif 358 359 #if MWBUF_VHDL_TESTBENCH 360 bool simulation_started; 361 bool generate_vhdl_testbench_mwbuf; 362 std::ofstream * vhdl_testbench_mwbuf; //[m_nb_dcache] 350 363 #endif 351 364 352 365 // Activity counters 353 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 354 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 355 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 356 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 357 358 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 359 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 360 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 361 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 362 363 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 364 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 365 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 366 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 367 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 368 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 369 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 370 371 uint32_t m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 372 uint32_t m_cpt_total_cycles; // total number of cycles 373 374 uint32_t m_cpt_data_read; // number of data read 375 uint32_t m_cpt_data_read_miss; // number of data read miss 376 uint32_t m_cpt_data_read_uncached; // number of data read uncached 377 uint32_t m_cpt_data_write; // number of data write 378 uint32_t m_cpt_data_write_miss; // number of data write miss 379 uint32_t m_cpt_data_write_uncached; // number of data write uncached 380 uint32_t m_cpt_ins_miss; // * number of instruction miss 381 382 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 383 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 384 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 385 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 386 387 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 388 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 389 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 390 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 391 392 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 393 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 394 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 395 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 396 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 366 uint32_t m_cpt_dcache_data_read; // * DCACHE DATA READ 367 uint32_t m_cpt_dcache_data_write; // * DCACHE DATA WRITE 368 uint32_t m_cpt_dcache_dir_read; // * DCACHE DIR READ 369 uint32_t m_cpt_dcache_dir_write; // * DCACHE DIR WRITE 370 371 uint32_t m_cpt_icache_data_read; // * ICACHE DATA READ 372 uint32_t m_cpt_icache_data_write; // * ICACHE DATA WRITE 373 uint32_t m_cpt_icache_dir_read; // * ICACHE DIR READ 374 uint32_t m_cpt_icache_dir_write; // * ICACHE DIR WRITE 375 376 uint32_t m_cpt_cc_update_icache; // number of coherence update packets (for icache) 377 uint32_t m_cpt_cc_update_dcache; // number of coherence update packets (for dcache) 378 uint32_t m_cpt_cc_inval_broadcast; // number of coherence inval packets 379 uint32_t m_cpt_cc_inval_icache; // number of coherence inval packets 380 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval packets 381 uint32_t m_cpt_cc_update_icache_word_useful; // number of valid word in coherence update packets 382 uint32_t m_cpt_cc_update_dcache_word_useful; // number of valid word in coherence update packets 383 384 uint32_t * m_cpt_frz_cycles; // * number of cycles where the cpu is frozen 385 uint32_t m_cpt_total_cycles; // total number of cycles 386 387 uint32_t m_cpt_data_read; // number of data read 388 uint32_t m_cpt_data_read_miss; // number of data read miss 389 uint32_t m_cpt_data_read_uncached; // number of data read uncached 390 uint32_t m_cpt_data_write; // number of data write 391 uint32_t m_cpt_data_write_miss; // number of data write miss 392 uint32_t m_cpt_data_write_uncached; // number of data write uncached 393 uint32_t m_cpt_ins_miss; // * number of instruction miss 394 395 uint32_t m_cost_write_frz; // * number of frozen cycles related to write buffer 396 uint32_t m_cost_data_miss_frz; // * number of frozen cycles related to data miss 397 uint32_t m_cost_unc_read_frz; // * number of frozen cycles related to uncached read 398 uint32_t m_cost_ins_miss_frz; // * number of frozen cycles related to ins miss 399 400 uint32_t m_cpt_imiss_transaction; // * number of VCI instruction miss transactions 401 uint32_t m_cpt_dmiss_transaction; // * number of VCI data miss transactions 402 uint32_t m_cpt_unc_transaction; // * number of VCI uncached read transactions 403 uint32_t m_cpt_data_write_transaction; // * number of VCI write transactions 404 405 uint32_t m_cost_imiss_transaction; // * cumulated duration for VCI IMISS transactions 406 uint32_t m_cost_dmiss_transaction; // * cumulated duration for VCI DMISS transactions 407 uint32_t m_cost_unc_transaction; // * cumulated duration for VCI UNC transactions 408 uint32_t m_cost_write_transaction; // * cumulated duration for VCI WRITE transactions 409 uint32_t m_length_write_transaction; // * cumulated length for VCI WRITE transactions 410 411 uint32_t * m_cpt_icache_access; //[m_nb_icache] 412 uint32_t * m_cpt_dcache_access; //[m_nb_dcache] 413 uint32_t * m_cpt_dcache_hit_after_miss_read; //[m_nb_dcache] 414 uint32_t * m_cpt_dcache_hit_after_miss_write; //[m_nb_dcache] 415 uint32_t * m_cpt_dcache_store_after_store; //[m_nb_dcache] 416 uint32_t * m_cpt_icache_miss_victim_wait; //[m_nb_icache] 417 uint32_t * m_cpt_dcache_miss_victim_wait; //[m_nb_dcache] 418 419 uint32_t ** m_cpt_fsm_dcache; //[m_nb_dcache] 420 uint32_t ** m_cpt_fsm_icache; //[m_nb_icache] 421 uint32_t * m_cpt_fsm_cmd; 422 uint32_t * m_cpt_fsm_rsp; 423 uint32_t * m_cpt_fsm_tgt; 424 uint32_t * m_cpt_fsm_cleanup; 425 426 // Non blocking multi-cache 427 typename iss_t::InstructionRequest * ireq ; //[m_nb_icache] 428 typename iss_t::InstructionResponse * irsp ; //[m_nb_icache] 429 bool * ireq_cached ; //[m_nb_icache] 430 uint32_t * ireq_num_cpu; //[m_nb_dcache] 431 typename iss_t::DataRequest * dreq ; //[m_nb_dcache] 432 typename iss_t::DataResponse * drsp ; //[m_nb_dcache] 433 bool * dreq_cached ; //[m_nb_dcache] 434 uint32_t * dreq_num_cpu; //[m_nb_dcache] 435 436 const uint32_t m_num_cache_LSB; 437 const uint32_t m_num_cache_MSB; 438 addr_40 m_num_cache_LSB_mask; 439 addr_40 m_num_cache_mask; 397 440 398 441 protected: … … 409 452 const soclib::common::IntTab &initiator_index_c, 410 453 const soclib::common::IntTab &target_index, 454 size_t nb_cpu, 455 size_t nb_dcache, 411 456 size_t icache_ways, 412 457 size_t icache_sets, … … 417 462 size_t wbuf_nwords, 418 463 size_t wbuf_nlines, 419 size_t wbuf_timeout 464 size_t wbuf_timeout, 465 write_policy_t write_policy=WRITE_THROUGH 420 466 ); 421 467 422 468 ~VciCcXCacheWrapperV4(); 423 469 424 void print_trace(size_t mode = 0); 425 void print_cpi(); 426 void print_stats(); 427 428 // #if CC_XCACHE_WRAPPER_STOP_SIMULATION 429 void stop_simulation (uint32_t); 430 // #endif // CC_XCACHE_WRAPPER_STOP_SIMULATION 470 void print_trace(size_t mode = 0); 471 void print_cpi(); 472 void print_stats(bool print_wbuf=true, bool print_fsm=true); 473 474 void stop_simulation (uint32_t); 475 void log_transaction ( bool generate_file_icache 476 ,bool generate_file_dcache 477 ,bool generate_file_cmd 478 ,bool generate_file_tgt 479 ,bool generate_file_cleanup); 480 481 void vhdl_testbench (bool generate_file_mwbuf); 431 482 432 483 private: … … 435 486 void genMoore(); 436 487 437 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 488 uint32_t get_num_cache (addr_40 & addr); 489 uint32_t get_num_cache_only(addr_40 addr); 490 void set_num_cache (addr_40 & addr, uint32_t num_cache); 491 addr_40 set_num_cache_only(addr_40 addr, uint32_t num_cache); 492 493 soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); 438 494 soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); 439 495 };
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