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arch.py @ 1050

Last change on this file since 1050 was 1050, checked in by alain, 7 years ago
Introduce the vci_master_nic component in the TSAR IOB architecture.
Property svn:executable set to ``*
File size: 20.4 KB

Rev	Line
[938]	1	#!/usr/bin/env python
[707]	2
[802]	3	from math import log, ceil
[707]	4	from mapping import *
	5
[938]	6	##################################################################################
[714]	7	# file : arch.py (for the tsar_generic_iob architecture)
[707]	8	# date : may 2014
	9	# author : Alain Greiner
[938]	10	##################################################################################
[802]	11	# This file contains a mapping generator for the "tsar_generic_iob" platform.
[707]	12	# This includes both the hardware architecture (clusters, processors, peripherals,
[938]	13	# physical space segmentation) and the mapping of all boot and kernel objects
	14	# (global vsegs).
[714]	15	#
[966]	16	# This platform includes 7 external peripherals, accessible through an IOB
[938]	17	# components located in cluster [0,0] or in cluster [x_size-1, y_size-1].
[966]	18	# Available peripherals are: TTY, IOC, FBF, ROM, NIC, CMA, PIC.
[938]	19	#
	20	# All clusters contain (nb_procs) processors, one L2 cache, one XCU, and
[972]	21	# one optional hardware coprocessor connected to a MWMR_DMA controller.
[938]	22	#
[966]	23	# The "constructor" parameters (defined in Makefile) are:
[714]	24	# - x_size : number of clusters in a row
	25	# - y_size : number of clusters in a column
	26	# - nb_procs : number of processors per cluster
[874]	27	# - nb_ttys : number of TTY channels
[817]	28	# - fbf_width : frame_buffer width = frame_buffer heigth
[1002]	29	# - ioc_type : can be 'BDV','HBA','SDC', 'SPI' but not 'RDK'
[1025]	30	# - mwr_type : coprocessor type / can be 'GCD','DCT','CPY','NONE'
[714]	31	#
[972]	32	# The other hardware parameters (defined in this script) are:
[714]	33	# - nb_nics : number of NIC channels
[938]	34	# - nb_cmas : number of CMA channels
[714]	35	# - x_io : cluster_io x coordinate
	36	# - y_io : cluster_io y coordinate
	37	# - x_width : number of bits for x coordinate
	38	# - y_width : number of bits for y coordinate
[1025]	39	# - p_width : number of bits for processor local index
[714]	40	# - paddr_width : number of bits for physical address
	41	# - irq_per_proc : number of input IRQs per processor
[1025]	42	# - peri_increment : address increment for replicated peripherals
[817]	43	#
[938]	44	# Regarding the boot and kernel vsegs mapping :
[1026]	45	# - We use one big physical page (2 Mbytes) for the preloader,
	46	# the 4 boot vsegs are packed in one BPP allocated in cluster[0,0].
	47	# - We use one BPP per cluster for the replicated kernel code vsegs.
	48	# - We use one BPP in cluster[0][0] for the kernel data vseg.
	49	# - We use two BPP per cluster for the distributed kernel heap vsegs.
	50	# - We use one BPP per cluster for the distributed ptab vsegs.
	51	# - We use two SPP per cluster for each schedulers.
	52	# - We use one PBB for each external peripheral in IO cluster,
	53	# - We use one SPP per cluster for each internal peripheral.
[938]	54	##################################################################################
[707]	55
[714]	56	########################
	57	def arch( x_size = 2,
	58	y_size = 2,
[817]	59	nb_procs = 2,
[874]	60	nb_ttys = 1,
[965]	61	fbf_width = 128,
[1025]	62	ioc_type = 'BDV',
	63	mwr_type = 'CPY' ):
[714]	64
	65	### define architecture constants
	66
[1050]	67	if ( x_size * y_size >= 4 ) : nb_nics = 4
	68	elif ( x_size * y_size == 2 ) : nb_nics = 2
	69	else : nb_nics = 1
	70
	71	nb_cmas = 1
[817]	72	x_io = 0
	73	y_io = 0
	74	x_width = 4
	75	y_width = 4
	76	p_width = 4
	77	paddr_width = 40
[972]	78	irq_per_proc = 4
[966]	79	peri_increment = 0x10000
[802]	80
[972]	81	### constructor parameters checking
[714]	82
[802]	83	assert( nb_procs <= (1 << p_width) )
[707]	84
[802]	85	assert( (x_size == 1) or (x_size == 2) or (x_size == 4)
[764]	86	or (x_size == 8) or (x_size == 16) )
[707]	87
[802]	88	assert( (y_size == 1) or (y_size == 2) or (y_size == 4)
[707]	89	or (y_size == 8) or (y_size == 16) )
	90
[1025]	91	assert( (nb_ttys >= 1) and (nb_ttys <= 16) )
[707]	92
	93	assert( ((x_io == 0) and (y_io == 0)) or
	94	((x_io == x_size-1) and (y_io == y_size-1)) )
	95
[1002]	96	assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' , 'SPI' ] )
[972]	97
[1025]	98	assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' ] )
[965]	99
	100	### define platform name
[802]	101
[965]	102	platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size , nb_procs )
[1025]	103	platform_name += '_%d_%d_%s_%s' % ( fbf_width , nb_ttys , ioc_type , mwr_type )
[707]	104
[938]	105	### define physical segments replicated in all clusters
	106
[707]	107	ram_base = 0x0000000000
[1018]	108	ram_size = 0x4000000 # 64 Mbytes
[707]	109
[802]	110	xcu_base = 0x00B0000000
	111	xcu_size = 0x1000 # 4 Kbytes
[707]	112
[972]	113	mwr_base = 0x00B1000000
	114	mwr_size = 0x1000 # 4 Kbytes
[707]	115
[802]	116	mmc_base = 0x00B2000000
[714]	117	mmc_size = 0x1000 # 4 Kbytes
[707]	118
[817]	119	### define physical segments for external peripherals
	120	## These segments are only defined in cluster_io
	121
[965]	122	ioc_base = 0x00B3000000
	123	ioc_size = 0x1000 # 4 Kbytes
[707]	124
[945]	125	tty_base = 0x00B4000000
[714]	126	tty_size = 0x4000 # 16 Kbytes
[707]	127
[945]	128	nic_base = 0x00B5000000
[1050]	129	nic_size = 0x1000 # 4 Kkbytes
[707]	130
[945]	131	cma_base = 0x00B6000000
[1018]	132	cma_size = 0x1000 * nb_cmas # 4 kbytes * nb_cmas
[707]	133
[945]	134	fbf_base = 0x00B7000000
[1018]	135	fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes
[707]	136
[945]	137	pic_base = 0x00B8000000
[714]	138	pic_size = 0x1000 # 4 Kbytes
[707]	139
[945]	140	iob_base = 0x00BE000000
[817]	141	iob_size = 0x1000 # 4 bytes
[707]	142
[945]	143	rom_base = 0x00BFC00000
[714]	144	rom_size = 0x4000 # 16 Kbytes
[707]	145
[754]	146	### define bootloader vsegs base addresses and sizes
[1031]	147	### We want to pack these 4 vsegs in 2 big pages
	148	### => boot cost two BIG pages in cluster[0][0]
[707]	149
[913]	150	boot_mapping_vbase = 0x00000000 # ident
[1031]	151	boot_mapping_size = 0x00100000 # 1 Mbytes
[707]	152
[1031]	153	boot_code_vbase = 0x00100000 # ident
	154	boot_code_size = 0x00080000 # 512 Kbytes
[802]	155
[1033]	156	boot_stack_vbase = 0x00180000 # ident
[1032]	157	boot_stack_size = 0x00080000 # 512 Kbytes
	158
[1033]	159	boot_data_vbase = 0x00200000 # ident
[1031]	160	boot_data_size = 0x00200000 # 2 Mbytes
[707]	161
[754]	162	### define kernel vsegs base addresses and sizes
[913]	163	### code, init, ptab, heap & sched vsegs are replicated in all clusters.
[817]	164	### data & uncdata vsegs are only mapped in cluster[0][0].
[707]	165
[802]	166	kernel_code_vbase = 0x80000000
[1026]	167	kernel_code_size = 0x00200000 # 2 Mbytes per cluster
[707]	168
[913]	169	kernel_data_vbase = 0x90000000
	170	kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0]
[707]	171
[817]	172	kernel_ptab_vbase = 0xE0000000
[913]	173	kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster
[707]	174
[913]	175	kernel_heap_vbase = 0xD0000000
[1050]	176	kernel_heap_size = 0x00200000 # 2 Mbytes per cluster
[707]	177
[817]	178	kernel_sched_vbase = 0xA0000000
	179	kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster
	180
[938]	181	#########################
[707]	182	### create mapping
[938]	183	#########################
[707]	184
[817]	185	mapping = Mapping( name = platform_name,
	186	x_size = x_size,
	187	y_size = y_size,
	188	nprocs = nb_procs,
	189	x_width = x_width,
	190	y_width = y_width,
[802]	191	p_width = p_width,
[817]	192	paddr_width = paddr_width,
	193	coherence = True,
	194	irq_per_proc = irq_per_proc,
[965]	195	use_ramdisk = (ioc_type == 'RDK'),
[817]	196	x_io = x_io,
[714]	197	y_io = y_io,
[802]	198	peri_increment = peri_increment,
	199	ram_base = ram_base,
	200	ram_size = ram_size )
[707]	201
	202
[938]	203	#############################
	204	### Hardware Components
	205	#############################
[707]	206
[938]	207	for x in xrange( x_size ):
	208	for y in xrange( y_size ):
	209	cluster_xy = (x << y_width) + y;
	210	offset = cluster_xy << (paddr_width - x_width - y_width)
[707]	211
[938]	212	### components replicated in all clusters
[972]	213	mapping.addRam( 'RAM', base = ram_base + offset,
[938]	214	size = ram_size )
[707]	215
[938]	216	xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset,
	217	size = xcu_size, ptype = 'XCU',
[955]	218	channels = nb_procs * irq_per_proc,
[959]	219	arg0 = 32, arg1 = 32, arg2 = 32 )
[707]	220
[979]	221	mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset,
	222	size = mmc_size, ptype = 'MMC' )
[707]	223
[972]	224	if ( mwr_type == 'GCD' ):
[975]	225	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
	226	size = mwr_size, ptype = 'MWR', subtype = 'GCD',
	227	arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 )
[972]	228
	229	if ( mwr_type == 'DCT' ):
[975]	230	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
	231	size = mwr_size, ptype = 'MWR', subtype = 'DCT',
	232	arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 )
[972]	233
	234	if ( mwr_type == 'CPY' ):
[975]	235	mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset,
	236	size = mwr_size, ptype = 'MWR', subtype = 'CPY',
	237	arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 )
[972]	238
[975]	239	mapping.addIrq( xcu, index = 0, src = mmc, isrtype = 'ISR_MMC' )
	240	mapping.addIrq( xcu, index = 1, src = mwr, isrtype = 'ISR_MWR' )
	241
[938]	242	for p in xrange ( nb_procs ):
[972]	243	mapping.addProc( x , y , p )
[707]	244
[938]	245	### external peripherals in cluster_io
	246	if ( (x==x_io) and (y==y_io) ):
[707]	247
[945]	248	iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size,
[938]	249	ptype = 'IOB' )
[707]	250
[965]	251	ioc = mapping.addPeriph( 'IOC', base = ioc_base + offset, size = ioc_size,
	252	ptype = 'IOC', subtype = ioc_type )
[707]	253
[945]	254	tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size,
[938]	255	ptype = 'TTY', channels = nb_ttys )
[710]	256
[945]	257	nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size,
[938]	258	ptype = 'NIC', channels = nb_nics )
[707]	259
[945]	260	cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size,
[938]	261	ptype = 'CMA', channels = nb_cmas )
[707]	262
[945]	263	fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size,
[955]	264	ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width )
[707]	265
[945]	266	rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size,
[938]	267	ptype = 'ROM' )
[707]	268
[945]	269	pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size,
[938]	270	ptype = 'PIC', channels = 32 )
[707]	271
[1050]	272	if ( ioc_type == 'BDV' ): isr_ioc = 'ISR_BDV'
	273	if ( ioc_type == 'HBA' ): isr_ioc = 'ISR_HBA'
	274	if ( ioc_type == 'SDC' ): isr_ioc = 'ISR_SDC'
	275	if ( ioc_type == 'SPI' ): isr_ioc = 'ISR_SPI'
	276
[975]	277	mapping.addIrq( pic, index = 0, src = nic,
	278	isrtype = 'ISR_NIC_RX', channel = 0 )
	279	mapping.addIrq( pic, index = 1, src = nic,
	280	isrtype = 'ISR_NIC_RX', channel = 1 )
[1050]	281	mapping.addIrq( pic, index = 2, src = nic,
	282	isrtype = 'ISR_NIC_RX', channel = 2 )
	283	mapping.addIrq( pic, index = 3, src = nic,
	284	isrtype = 'ISR_NIC_RX', channel = 3 )
[707]	285
[1050]	286	mapping.addIrq( pic, index = 4, src = nic,
[975]	287	isrtype = 'ISR_NIC_TX', channel = 0 )
[1050]	288	mapping.addIrq( pic, index = 5, src = nic,
[975]	289	isrtype = 'ISR_NIC_TX', channel = 1 )
[1050]	290	mapping.addIrq( pic, index = 6, src = nic,
	291	isrtype = 'ISR_NIC_TX', channel = 2 )
	292	mapping.addIrq( pic, index = 7, src = nic,
	293	isrtype = 'ISR_NIC_TX', channel = 3 )
[710]	294
[1050]	295	mapping.addIrq( pic, index = 8 , src = cma,
[975]	296	isrtype = 'ISR_CMA', channel = 0 )
[1050]	297	mapping.addIrq( pic, index = 9 , src = cma,
[975]	298	isrtype = 'ISR_CMA', channel = 1 )
[1050]	299	mapping.addIrq( pic, index = 10, src = cma,
[975]	300	isrtype = 'ISR_CMA', channel = 2 )
[1050]	301	mapping.addIrq( pic, index = 11, src = cma,
[975]	302	isrtype = 'ISR_CMA', channel = 3 )
[770]	303
[1050]	304	mapping.addIrq( pic, index = 12, src = ioc,
	305	isrtype = isr_ioc, channel = 0 )
[707]	306
[975]	307	mapping.addIrq( pic, index = 16, src = tty,
	308	isrtype = 'ISR_TTY_RX', channel = 0 )
	309	mapping.addIrq( pic, index = 17, src = tty,
	310	isrtype = 'ISR_TTY_RX', channel = 1 )
	311	mapping.addIrq( pic, index = 18, src = tty,
	312	isrtype = 'ISR_TTY_RX', channel = 2 )
	313	mapping.addIrq( pic, index = 19, src = tty,
	314	isrtype = 'ISR_TTY_RX', channel = 3 )
	315	mapping.addIrq( pic, index = 20, src = tty,
	316	isrtype = 'ISR_TTY_RX', channel = 4 )
	317	mapping.addIrq( pic, index = 21, src = tty,
	318	isrtype = 'ISR_TTY_RX', channel = 5 )
	319	mapping.addIrq( pic, index = 22, src = tty,
	320	isrtype = 'ISR_TTY_RX', channel = 6 )
	321	mapping.addIrq( pic, index = 23, src = tty,
	322	isrtype = 'ISR_TTY_RX', channel = 7 )
[965]	323
[938]	324
	325	####################################
	326	### Boot & Kernel vsegs mapping
	327	####################################
	328
[817]	329	### global vsegs for boot_loader
	330	### we want to pack those 4 vsegs in the same big page
	331	### => same flags CXW_ / identity mapping / non local / big page
[707]	332
[730]	333	mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size,
[817]	334	'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM',
	335	identity = True , local = False, big = True )
[707]	336
[730]	337	mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size,
	338	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
[817]	339	identity = True , local = False, big = True )
[707]	340
[730]	341	mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size,
[817]	342	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	343	identity = True , local = False, big = True )
[707]	344
[730]	345	mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size,
[817]	346	'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM',
	347	identity = True , local = False, big = True )
[707]	348
[943]	349	### global vseg kernel_data : big / non local
	350	### Only mapped in cluster[0][0]
	351	mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size,
	352	'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM',
[1005]	353	binpath = 'bin/kernel/kernel.elf',
[943]	354	local = False, big = True )
	355
[1026]	356	### global vsegs kernel_code : big / local
[965]	357	### replicated in all clusters with indexed name & same vbase
[874]	358	for x in xrange( x_size ):
	359	for y in xrange( y_size ):
[965]	360	mapping.addGlobal( 'seg_kernel_code_%d_%d' %(x,y),
	361	kernel_code_vbase, kernel_code_size,
[817]	362	'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM',
[1005]	363	binpath = 'bin/kernel/kernel.elf',
[817]	364	local = True, big = True )
[707]	365
[938]	366	### Global vsegs kernel_ptab_x_y : big / non local
	367	### one vseg per cluster: name indexed by (x,y)
	368	for x in xrange( x_size ):
	369	for y in xrange( y_size ):
	370	offset = ((x << y_width) + y) * kernel_ptab_size
	371	base = kernel_ptab_vbase + offset
	372	mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size,
	373	'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM',
	374	local = False , big = True )
	375
[913]	376	### global vsegs kernel_sched_x_y : small / non local
[874]	377	### one vseg per cluster with name indexed by (x,y)
[817]	378	for x in xrange( x_size ):
	379	for y in xrange( y_size ):
[913]	380	offset = ((x << y_width) + y) * kernel_sched_size
[938]	381	mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y),
	382	kernel_sched_vbase + offset , kernel_sched_size,
[817]	383	'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM',
	384	local = False, big = False )
[707]	385
[913]	386	### global vsegs kernel_heap_x_y : big / non local
	387	### one vseg per cluster with name indexed by (x,y)
	388	for x in xrange( x_size ):
	389	for y in xrange( y_size ):
	390	offset = ((x << y_width) + y) * kernel_heap_size
[938]	391	mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y),
	392	kernel_heap_vbase + offset , kernel_heap_size,
[913]	393	'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM',
	394	local = False, big = True )
	395
[817]	396	### global vsegs for external peripherals : non local / big page
[802]	397	mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_',
	398	vtype = 'PERI', x = 0, y = 0, pseg = 'IOB',
[817]	399	local = False, big = True )
[707]	400
[965]	401	mapping.addGlobal( 'seg_ioc', ioc_base, ioc_size, '__W_',
	402	vtype = 'PERI', x = 0, y = 0, pseg = 'IOC',
[817]	403	local = False, big = True )
[707]	404
[802]	405	mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_',
[730]	406	vtype = 'PERI', x = 0, y = 0, pseg = 'TTY',
[817]	407	local = False, big = True )
[707]	408
[802]	409	mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_',
[730]	410	vtype = 'PERI', x = 0, y = 0, pseg = 'NIC',
[817]	411	local = False, big = True )
[707]	412
[802]	413	mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_',
[730]	414	vtype = 'PERI', x = 0, y = 0, pseg = 'CMA',
[817]	415	local = False, big = True )
[707]	416
[802]	417	mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_',
[730]	418	vtype = 'PERI', x = 0, y = 0, pseg = 'FBF',
[817]	419	local = False, big = True )
[707]	420
[802]	421	mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_',
[730]	422	vtype = 'PERI', x = 0, y = 0, pseg = 'PIC',
[817]	423	local = False, big = True )
[707]	424
[802]	425	mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_',
[730]	426	vtype = 'PERI', x = 0, y = 0, pseg = 'ROM',
[817]	427	local = False, big = True )
[707]	428
[817]	429	### global vsegs for internal peripherals : non local / small pages
	430	### allocated in all clusters with name indexed by (x,y)
	431	### as vbase address is incremented by (cluster_xy * vseg_increment)
[714]	432	for x in xrange( x_size ):
	433	for y in xrange( y_size ):
[817]	434	offset = ((x << y_width) + y) * peri_increment
[707]	435
[714]	436	mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size,
[817]	437	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU',
	438	local = False, big = False )
[707]	439
[714]	440	mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size,
[817]	441	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC',
	442	local = False, big = False )
[707]	443
[972]	444	if ( mwr_type != 'NONE' ):
	445	mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size,
	446	'__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR',
	447	local = False, big = False )
	448
[707]	449	return mapping
	450
[938]	451	################################# platform test ####################################
[707]	452
	453	if __name__ == '__main__':
	454
[730]	455	mapping = arch( x_size = 2,
	456	y_size = 2,
	457	nb_procs = 2 )
[707]	458
	459	# print mapping.netbsd_dts()
	460
	461	print mapping.xml()
	462
	463	# print mapping.giet_vsegs()
	464
[802]	465
[707]	466	# Local Variables:
	467	# tab-width: 4;
	468	# c-basic-offset: 4;
	469	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	470	# indent-tabs-mode: nil;
	471	# End:
	472	#
	473	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	474

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source: trunk/platforms/tsar_generic_iob/arch.py @ 1050

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