[450] | 1 | /////////////////////////////////////////////////////////////////////////////// |
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[707] | 2 | // File: top.cpp (for tsar_generic_iob platform) |
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[718] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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[966] | 5 | // Date : august 2013 / updated march 2015 |
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[450] | 6 | // This program is released under the GNU public license |
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| 7 | /////////////////////////////////////////////////////////////////////////////// |
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[938] | 8 | // This file define a generic TSAR architecture with an external IO network |
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| 9 | // emulating a PCI or Hypertransport I/O bus to access 7 external peripherals: |
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[450] | 10 | // |
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[472] | 11 | // - BROM : boot ROM |
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| 12 | // - FBUF : Frame Buffer |
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[730] | 13 | // - MTTY : multi TTY (one channel) |
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[1050] | 14 | // - MNIC : Network controller (up to 4 channels) |
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[965] | 15 | // - DISK : Block device controler (BDV / HBA / SDC) |
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[707] | 16 | // - IOPI : HWI to SWI translator. |
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[450] | 17 | // |
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[938] | 18 | // This I/0 bus is connected to internal address space through two IOB bridges |
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[966] | 19 | // located in cluster[0][0] and cluster[X_SIZE-1][Y_SIZE-1]. |
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[938] | 20 | // |
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[707] | 21 | // The internal physical address space is 40 bits, and the cluster index |
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| 22 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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[938] | 23 | // Y is encoded on 4 bits, whatever the actual mesh size. |
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[707] | 24 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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[450] | 25 | // |
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[607] | 26 | // It contains 3 networks: |
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| 27 | // |
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[707] | 28 | // 1) the "INT" network supports Read/Write transactions |
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[718] | 29 | // between processors and L2 caches or peripherals. |
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[450] | 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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[718] | 32 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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[472] | 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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[450] | 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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[707] | 37 | // 7 external peripheral controllers. |
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[450] | 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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[718] | 39 | // |
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| 40 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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[707] | 41 | // external IOPIC component, that must be configured by the OS to route |
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[874] | 42 | // these WTI IRQS to one or several internal XICU components. |
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[1050] | 43 | // - IOPIC HWI[3:0] connected to IRQ_NIC_RX[3:0] |
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| 44 | // - IOPIC HWI[7:4] connected to IRQ_NIC_TX[3:0] |
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| 45 | // - IOPIC HWI[12] connected to IRQ_IOC |
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[874] | 46 | // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] |
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[450] | 47 | // |
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[972] | 48 | // Each cluster contains the following component: |
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| 49 | // - From 1 to 8 MIP32 processors |
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| 50 | // - One L2 cache controller |
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| 51 | // - One XICU component, |
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| 52 | // - One - optional - single channel DMA controler, |
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| 53 | // - One - optional - hardware coprocessor |
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| 54 | // The XICU component is mainly used to handle WTI IRQs, as at most |
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| 55 | // 2 HWI IRQs are connected to XICU in each cluster: |
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[959] | 56 | // - IRQ_IN[0] : MMC |
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[972] | 57 | // - IRQ_IN[1] : MWR |
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[718] | 58 | // |
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[450] | 59 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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[1050] | 60 | // contain an extra IO bridge component and two DSPIN local-xbar to multiplex |
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| 61 | // the MEMC and IOB access to RAM network. These IOB0 & IOB1 components are |
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[450] | 62 | // connected to the three networks (INT, RAM, IOX). |
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[718] | 63 | // |
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[450] | 64 | // - It uses two dspin_local_crossbar per cluster to implement the |
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[718] | 65 | // local interconnect correponding to the INT network. |
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| 66 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 67 | // local interconnect correponding to the coherence INT network. |
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[450] | 68 | // - It uses two virtual_dspin_router per cluster to implement |
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| 69 | // the INT network (routing both the direct and coherence trafic). |
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| 70 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 71 | // - It uses the vci_cc_vcache_wrapper. |
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| 72 | // - It uses the vci_mem_cache. |
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| 73 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 74 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 75 | // |
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| 76 | // The TsarIobCluster component is defined in files |
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| 77 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 78 | // |
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| 79 | // The main hardware parameters must be defined in the hard_config.h file : |
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[966] | 80 | // - X_WIDTH : number of bits for x cluster coordinate |
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| 81 | // - Y_WIDTH : number of bits for y cluster coordinate |
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| 82 | // - P_WIDTH : number of bits for local processor coordinate |
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[718] | 83 | // - X_SIZE : number of clusters in a row |
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[707] | 84 | // - Y_SIZE : number of clusters in a column |
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[959] | 85 | // - NB_PROCS_MAX : number of processors per cluster (up to 8) |
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| 86 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (>= NB_PROCS_MAX) |
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[1050] | 87 | // - NB_TXT_CHANNELS : number of TTY channels in I/O network (up to 16) |
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| 88 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 4) |
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[714] | 89 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 90 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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[1050] | 91 | // - ICU_NB_HWI : number of ICU HWIs (>= NB_PROCS_MAX + 1) |
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| 92 | // - ICU_NB_PTI : number of ICU PTIs (>= NB_PROCS_MAX) |
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| 93 | // - ICU_NB_WTI : number of ICU WTIs (>= 4*NB_PROCS_MAX) |
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| 94 | // - ICU_NB_OUT : number of ICU output IRQs (>= 4*NB_PROCS_MAX) |
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[966] | 95 | // - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC) |
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[718] | 96 | // |
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[966] | 97 | // Some other hardware parameters must be defined in this top.cpp file: |
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[718] | 98 | // - XRAM_LATENCY : external ram latency |
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[450] | 99 | // - MEMC_WAYS : L2 cache number of ways |
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| 100 | // - MEMC_SETS : L2 cache number of sets |
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[718] | 101 | // - L1_IWAYS |
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| 102 | // - L1_ISETS |
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| 103 | // - L1_DWAYS |
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| 104 | // - L1_DSETS |
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[965] | 105 | // - DISK_IMAGE_NAME : file pathname for block device |
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[450] | 106 | // |
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| 107 | // General policy for 40 bits physical address decoding: |
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| 108 | // All physical segments base addresses are multiple of 1 Mbytes |
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[718] | 109 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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[450] | 110 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 111 | // the cluster index, and the LADR bits define the local index: |
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[707] | 112 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 113 | // | 4 | 4 | 8 | 24 | |
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[450] | 114 | // |
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| 115 | // General policy for 14 bits SRCID decoding: |
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| 116 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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[707] | 117 | // |X_ID|Y_ID| L_ID | |
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| 118 | // | 4 | 4 | 6 | |
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[1050] | 119 | // |
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| 120 | // The NIC controler has one VCI target port, and one VCI initiator port, |
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| 121 | // but it uses two different LOCAL_SRCID values to distinguish TX and TX |
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| 122 | // transactions, because there is not enough bits in 4 bits TRDID field. |
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[450] | 123 | ///////////////////////////////////////////////////////////////////////// |
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| 124 | |
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| 125 | #include <systemc> |
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| 126 | #include <sys/time.h> |
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| 127 | #include <iostream> |
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| 128 | #include <sstream> |
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| 129 | #include <cstdlib> |
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| 130 | #include <cstdarg> |
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| 131 | #include <stdint.h> |
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| 132 | |
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| 133 | #include "gdbserver.h" |
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| 134 | #include "mapping_table.h" |
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| 135 | |
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| 136 | #include "tsar_iob_cluster.h" |
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| 137 | #include "vci_chbuf_dma.h" |
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| 138 | #include "vci_multi_tty.h" |
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[1050] | 139 | #include "vci_master_nic.h" |
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[450] | 140 | #include "vci_simple_rom.h" |
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[965] | 141 | #include "vci_multi_ahci.h" |
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[450] | 142 | #include "vci_block_device_tsar.h" |
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[1002] | 143 | #include "vci_ahci_sdc.h" |
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| 144 | #include "sd_card.h" |
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[450] | 145 | #include "vci_framebuffer.h" |
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| 146 | #include "vci_iox_network.h" |
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[707] | 147 | #include "vci_iopic.h" |
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[450] | 148 | |
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| 149 | #include "alloc_elems.h" |
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| 150 | |
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[972] | 151 | |
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| 152 | ////////////////////////////////////////////////////////////////// |
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| 153 | // Coprocessor type (must be replicated in tsar_iob_cluster) |
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| 154 | ////////////////////////////////////////////////////////////////// |
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| 155 | |
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| 156 | #define MWR_COPROC_CPY 0 |
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| 157 | #define MWR_COPROC_DCT 1 |
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| 158 | #define MWR_COPROC_GCD 2 |
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| 159 | |
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| 160 | ////////////////////////////////////////////////////////////////// |
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[1046] | 161 | // Virtual disk selection => OS selection |
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[972] | 162 | ////////////////////////////////////////////////////////////////// |
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| 163 | |
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[1046] | 164 | #define USE_ALMOS 1 |
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| 165 | #define USE_GIET 0 |
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[450] | 166 | |
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[1046] | 167 | #if ( USE_ALMOS + USE_GIET != 1 ) |
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| 168 | #error "OS UNDEFINED" |
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| 169 | #endif |
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[450] | 170 | |
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[1046] | 171 | #if USE_ALMOS |
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| 172 | #define DISK_IMAGE_NAME "almos_virt_hdd.dmg" |
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| 173 | #endif |
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| 174 | |
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| 175 | #if USE_GIET |
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| 176 | #define DISK_IMAGE_NAME "giet_virt_hdd.dmg" |
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| 177 | #endif |
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[972] | 178 | ////////////////////////////////////////////////////////////////// |
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| 179 | // Parallelisation |
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| 180 | ////////////////////////////////////////////////////////////////// |
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[450] | 181 | |
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[981] | 182 | #if USE_OPENMP |
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[450] | 183 | #include <omp.h> |
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| 184 | #endif |
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| 185 | |
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[972] | 186 | ////////////////////////////////////////////////////////////////// |
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[718] | 187 | // DSPIN parameters |
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[972] | 188 | ////////////////////////////////////////////////////////////////// |
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[450] | 189 | |
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| 190 | #define dspin_int_cmd_width 39 |
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| 191 | #define dspin_int_rsp_width 32 |
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| 192 | |
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| 193 | #define dspin_ram_cmd_width 64 |
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| 194 | #define dspin_ram_rsp_width 64 |
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| 195 | |
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[972] | 196 | ////////////////////////////////////////////////////////////////// |
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[718] | 197 | // VCI fields width for the 3 VCI networks |
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[972] | 198 | ////////////////////////////////////////////////////////////////// |
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[450] | 199 | |
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| 200 | #define vci_cell_width_int 4 |
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| 201 | #define vci_cell_width_ext 8 |
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| 202 | |
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| 203 | #define vci_plen_width 8 |
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| 204 | #define vci_address_width 40 |
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| 205 | #define vci_rerror_width 1 |
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| 206 | #define vci_clen_width 1 |
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| 207 | #define vci_rflag_width 1 |
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| 208 | #define vci_srcid_width 14 |
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| 209 | #define vci_pktid_width 4 |
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| 210 | #define vci_trdid_width 4 |
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| 211 | #define vci_wrplen_width 1 |
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| 212 | |
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| 213 | //////////////////////////////////////////////////////////// |
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[718] | 214 | // Main Hardware Parameters values |
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[450] | 215 | //////////////////////i///////////////////////////////////// |
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| 216 | |
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[802] | 217 | #include "hard_config.h" |
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[450] | 218 | |
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| 219 | //////////////////////////////////////////////////////////// |
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[718] | 220 | // Secondary Hardware Parameters values |
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[450] | 221 | //////////////////////i///////////////////////////////////// |
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| 222 | |
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[607] | 223 | #define XMAX X_SIZE |
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| 224 | #define YMAX Y_SIZE |
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[450] | 225 | |
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| 226 | #define XRAM_LATENCY 0 |
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| 227 | |
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| 228 | #define MEMC_WAYS 16 |
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| 229 | #define MEMC_SETS 256 |
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| 230 | |
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[1050] | 231 | #define MNIC_MAC_4 0x33445566 // 32 LSB bits |
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| 232 | #define MNIC_MAC_2 0X1122 // 16 MSB bits |
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| 233 | |
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[450] | 234 | #define L1_IWAYS 4 |
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| 235 | #define L1_ISETS 64 |
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| 236 | |
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| 237 | #define L1_DWAYS 4 |
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| 238 | #define L1_DSETS 64 |
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| 239 | |
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[938] | 240 | #define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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[450] | 241 | |
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| 242 | #define NORTH 0 |
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| 243 | #define SOUTH 1 |
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| 244 | #define EAST 2 |
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| 245 | #define WEST 3 |
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| 246 | |
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[693] | 247 | #define cluster(x,y) ((y) + ((x) << 4)) |
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[450] | 248 | |
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| 249 | //////////////////////////////////////////////////////////// |
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[718] | 250 | // DEBUG Parameters default values |
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[450] | 251 | //////////////////////i///////////////////////////////////// |
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| 252 | |
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[914] | 253 | #define MAX_FROZEN_CYCLES 1000000 |
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[450] | 254 | |
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| 255 | ///////////////////////////////////////////////////////// |
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| 256 | // Physical segments definition |
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| 257 | ///////////////////////////////////////////////////////// |
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| 258 | |
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[734] | 259 | // All physical segments base addresses and sizes are defined |
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| 260 | // in the hard_config.h file. For replicated segments, the |
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| 261 | // base address is incremented by a cluster offset: |
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| 262 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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[450] | 263 | |
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| 264 | //////////////////////////////////////////////////////////////////////// |
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| 265 | // SRCID definition |
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| 266 | //////////////////////////////////////////////////////////////////////// |
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| 267 | // All initiators are in the same indexing space (14 bits). |
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| 268 | // The SRCID is structured in two fields: |
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[1050] | 269 | // - The 8 MSB bits define the cluster index. |
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[764] | 270 | // - The 6 LSB bits define the local index. |
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[718] | 271 | // Two different initiators cannot have the same SRCID, but a given |
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| 272 | // initiator can have two alias SRCIDs: |
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[972] | 273 | // - Internal initiators (procs, mwmr) are replicated in all clusters, |
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[450] | 274 | // and each initiator has one single SRCID. |
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[965] | 275 | // - External initiators (disk, cdma) are not replicated, but can be |
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[718] | 276 | // accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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[450] | 277 | // They have the same local index, but two different cluster indexes. |
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[707] | 278 | // |
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[450] | 279 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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[718] | 280 | // and external initiators, they must have different local indexes. |
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[450] | 281 | // Consequence: For a local interconnect, the INI_ID port index |
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| 282 | // is NOT equal to the SRCID local index, and the local interconnect |
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[718] | 283 | // must make a translation: SRCID => INI_ID |
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[450] | 284 | //////////////////////////////////////////////////////////////////////// |
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| 285 | |
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[550] | 286 | #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 |
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[972] | 287 | #define MWMR_LOCAL_SRCID 0x8 |
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[550] | 288 | #define IOBX_LOCAL_SRCID 0x9 |
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| 289 | #define MEMC_LOCAL_SRCID 0xA |
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[965] | 290 | #define DISK_LOCAL_SRCID 0xC |
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[707] | 291 | #define IOPI_LOCAL_SRCID 0xD |
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[1050] | 292 | #define MNRX_LOCAL_SRCID 0xE // NIC_RX transactions |
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| 293 | #define MNTX_LOCAL_SRCID 0xF // NIC_TX transactions |
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[450] | 294 | |
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[550] | 295 | /////////////////////////////////////////////////////////////////////// |
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[450] | 296 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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[550] | 297 | /////////////////////////////////////////////////////////////////////// |
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[450] | 298 | |
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| 299 | #define INT_MEMC_TGT_ID 0 |
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| 300 | #define INT_XICU_TGT_ID 1 |
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[972] | 301 | #define INT_MWMR_TGT_ID 2 |
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[450] | 302 | #define INT_IOBX_TGT_ID 3 |
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| 303 | |
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| 304 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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[972] | 305 | #define INT_MWMR_INI_ID (NB_PROCS_MAX) |
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[450] | 306 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 307 | |
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[550] | 308 | /////////////////////////////////////////////////////////////////////// |
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[450] | 309 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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[550] | 310 | /////////////////////////////////////////////////////////////////////// |
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[450] | 311 | |
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| 312 | #define RAM_XRAM_TGT_ID 0 |
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| 313 | |
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| 314 | #define RAM_MEMC_INI_ID 0 |
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| 315 | #define RAM_IOBX_INI_ID 1 |
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| 316 | |
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[550] | 317 | /////////////////////////////////////////////////////////////////////// |
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[450] | 318 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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[550] | 319 | /////////////////////////////////////////////////////////////////////// |
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[450] | 320 | |
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[718] | 321 | #define IOX_FBUF_TGT_ID 0 |
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[965] | 322 | #define IOX_DISK_TGT_ID 1 |
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[718] | 323 | #define IOX_MNIC_TGT_ID 2 |
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[1050] | 324 | #define IOX_BROM_TGT_ID 3 |
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| 325 | #define IOX_MTTY_TGT_ID 4 |
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| 326 | #define IOX_IOPI_TGT_ID 5 |
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| 327 | #define IOX_IOB0_TGT_ID 6 |
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| 328 | #define IOX_IOB1_TGT_ID 7 |
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[450] | 329 | |
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[965] | 330 | #define IOX_DISK_INI_ID 0 |
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[1050] | 331 | #define IOX_IOPI_INI_ID 1 |
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| 332 | #define IOX_MNIC_INI_ID 2 |
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[718] | 333 | #define IOX_IOB0_INI_ID 3 |
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| 334 | #define IOX_IOB1_INI_ID 4 |
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[450] | 335 | |
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[550] | 336 | //////////////////////////////////////////////////////////////////////// |
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[450] | 337 | int _main(int argc, char *argv[]) |
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[550] | 338 | //////////////////////////////////////////////////////////////////////// |
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[450] | 339 | { |
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| 340 | using namespace sc_core; |
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| 341 | using namespace soclib::caba; |
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| 342 | using namespace soclib::common; |
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| 343 | |
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[938] | 344 | char soft_name[256] = ROM_SOFT_NAME; // pathname: binary code |
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| 345 | size_t ncycles = 4000000000; // simulated cycles |
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[965] | 346 | char disk_name[256] = DISK_IMAGE_NAME; // pathname: disk image |
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[966] | 347 | ssize_t threads = 1; // simulator's threads number |
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[938] | 348 | bool debug_ok = false; // trace activated |
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[1030] | 349 | uint32_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 350 | uint32_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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[938] | 351 | bool debug_iob = false; // trace iob0 & iob1 when true |
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| 352 | uint32_t debug_from = 0; // trace start cycle |
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| 353 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 354 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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| 355 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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| 356 | size_t x_width = X_WIDTH; // # of bits for x |
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| 357 | size_t y_width = Y_WIDTH; // # of bits for y |
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| 358 | size_t p_width = P_WIDTH; // # of bits for lpid |
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[450] | 359 | |
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[981] | 360 | #if USE_OPENMP |
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[762] | 361 | size_t simul_period = 1000000; |
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| 362 | #else |
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| 363 | size_t simul_period = 1; |
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| 364 | #endif |
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| 365 | |
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[607] | 366 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 367 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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[718] | 368 | |
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[818] | 369 | assert( P_WIDTH <= 4 and |
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| 370 | "ERROR: we must have P_WIDTH <= 4"); |
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[802] | 371 | |
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[450] | 372 | ////////////// command line arguments ////////////////////// |
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| 373 | if (argc > 1) |
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| 374 | { |
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| 375 | for (int n = 1; n < argc; n = n + 2) |
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| 376 | { |
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| 377 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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| 378 | { |
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| 379 | ncycles = atoi(argv[n+1]); |
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| 380 | } |
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| 381 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 382 | { |
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| 383 | debug_ok = true; |
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| 384 | debug_from = atoi(argv[n+1]); |
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| 385 | } |
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| 386 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 387 | { |
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| 388 | strcpy(disk_name, argv[n+1]); |
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| 389 | } |
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| 390 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
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| 391 | { |
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| 392 | debug_memc_id = atoi(argv[n+1]); |
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[607] | 393 | size_t x = debug_memc_id >> 4; |
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| 394 | size_t y = debug_memc_id & 0xF; |
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| 395 | if( (x>=XMAX) || (y>=YMAX) ) |
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| 396 | { |
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[966] | 397 | std::cout << "MEMCID parameter doesn't fit XMAX/YMAX" << std::endl; |
---|
[914] | 398 | std::cout << " - MEMCID = " << std::hex << debug_memc_id << std::endl; |
---|
| 399 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
---|
| 400 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
---|
[607] | 401 | exit(0); |
---|
| 402 | } |
---|
[450] | 403 | } |
---|
| 404 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
---|
| 405 | { |
---|
| 406 | debug_iob = atoi(argv[n+1]); |
---|
| 407 | } |
---|
| 408 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
---|
| 409 | { |
---|
[607] | 410 | debug_proc_id = atoi(argv[n+1]); |
---|
[802] | 411 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
---|
[607] | 412 | size_t x = cluster_xy >> 4; |
---|
| 413 | size_t y = cluster_xy & 0xF; |
---|
| 414 | if( (x>=XMAX) || (y>=YMAX) ) |
---|
| 415 | { |
---|
| 416 | std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; |
---|
[914] | 417 | std::cout << " - PROCID = " << std::hex << debug_proc_id << std::endl; |
---|
| 418 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
---|
| 419 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
---|
[607] | 420 | exit(0); |
---|
| 421 | } |
---|
[450] | 422 | } |
---|
| 423 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
---|
| 424 | { |
---|
[966] | 425 | threads = atoi(argv[n+1]); |
---|
| 426 | threads = (threads < 1) ? 1 : threads; |
---|
[450] | 427 | } |
---|
| 428 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
---|
| 429 | { |
---|
| 430 | frozen_cycles = atoi(argv[n+1]); |
---|
| 431 | } |
---|
| 432 | else |
---|
| 433 | { |
---|
| 434 | std::cout << " Arguments are (key,value) couples." << std::endl; |
---|
| 435 | std::cout << " The order is not important." << std::endl; |
---|
| 436 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
---|
[938] | 437 | std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; |
---|
| 438 | std::cout << " - DEBUG debug_start_cycle" << std::endl; |
---|
| 439 | std::cout << " - THREADS simulator's threads number" << std::endl; |
---|
[1030] | 440 | std::cout << " - FROZEN max_number_of_cycles" << std::endl; |
---|
[938] | 441 | std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; |
---|
| 442 | std::cout << " - PROCID index_proc_to_be_traced" << std::endl; |
---|
| 443 | std::cout << " - IOB non_zero_value" << std::endl; |
---|
[450] | 444 | exit(0); |
---|
| 445 | } |
---|
| 446 | } |
---|
| 447 | } |
---|
| 448 | |
---|
| 449 | // checking hardware parameters |
---|
[607] | 450 | assert( (XMAX <= 16) and |
---|
[972] | 451 | "Error in tsar_generic_iob : XMAX parameter cannot be larger than 16" ); |
---|
[450] | 452 | |
---|
[607] | 453 | assert( (YMAX <= 16) and |
---|
[972] | 454 | "Error in tsar_generic_iob : YMAX parameter cannot be larger than 16" ); |
---|
[450] | 455 | |
---|
[959] | 456 | assert( (NB_PROCS_MAX <= 8) and |
---|
[972] | 457 | "Error in tsar_generic_iob : NB_PROCS_MAX parameter cannot be larger than 8" ); |
---|
[450] | 458 | |
---|
[1050] | 459 | assert( (ICU_NB_HWI > NB_PROCS_MAX) and |
---|
| 460 | "Error in tsar_generic_iob : ICU_NB_HWI cannot be smaller than NB_PROCS_MAX" ); |
---|
[959] | 461 | |
---|
[1050] | 462 | assert( (ICU_NB_PTI >= NB_PROCS_MAX) and |
---|
| 463 | "Error in tsar_generic_iob : ICU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); |
---|
[959] | 464 | |
---|
[1050] | 465 | assert( (ICU_NB_WTI >= 4*NB_PROCS_MAX) and |
---|
| 466 | "Error in tsar_generic_iob : ICU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
[959] | 467 | |
---|
[1050] | 468 | assert( (ICU_NB_OUT >= 4*NB_PROCS_MAX) and |
---|
| 469 | "Error in tsar_generic_iob : ICU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); |
---|
[959] | 470 | |
---|
[1050] | 471 | assert( (NB_TXT_CHANNELS >= 1) and (NB_TXT_CHANNELS <= 16) and |
---|
| 472 | "Error in tsar_generic_iob : NB_TXT_CHANNELS parameter cannot be larger than 16" ); |
---|
[450] | 473 | |
---|
[1050] | 474 | assert( (NB_NIC_CHANNELS <= 4) and |
---|
| 475 | "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 4" ); |
---|
[450] | 476 | |
---|
[966] | 477 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
---|
[972] | 478 | "Error in tsar_generic_iob : You must have X_WIDTH == Y_WIDTH == 4"); |
---|
[966] | 479 | |
---|
[972] | 480 | assert( ((USE_MWR_CPY + USE_MWR_GCD + USE_MWR_DCT) == 1) and |
---|
| 481 | "Error in tsar_generic_iob : No MWR coprocessor found in hard_config.h"); |
---|
| 482 | |
---|
| 483 | assert( ((USE_IOC_HBA + USE_IOC_BDV + USE_IOC_SDC) == 1) and |
---|
| 484 | "Error in tsar_generic_iob : NoIOC controller found in hard_config.h"); |
---|
| 485 | |
---|
[707] | 486 | std::cout << std::endl << std::dec |
---|
| 487 | << " - XMAX = " << XMAX << std::endl |
---|
| 488 | << " - YMAX = " << YMAX << std::endl |
---|
[802] | 489 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
---|
[1050] | 490 | << " - NB_TXT_CHANNELS = " << NB_TXT_CHANNELS << std::endl |
---|
[707] | 491 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
---|
| 492 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
---|
| 493 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
---|
| 494 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
---|
| 495 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
---|
[914] | 496 | << " - NCYCLES = " << ncycles << std::endl |
---|
[966] | 497 | << " - SOFT_FILENAME = " << soft_name << std::endl |
---|
| 498 | << " - DISK_IMAGENAME = " << disk_name << std::endl |
---|
| 499 | << " - OPENMP THREADS = " << threads << std::endl |
---|
[707] | 500 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
---|
[1030] | 501 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl; |
---|
[450] | 502 | |
---|
| 503 | std::cout << std::endl; |
---|
| 504 | |
---|
[981] | 505 | #if USE_OPENMP |
---|
[450] | 506 | omp_set_dynamic(false); |
---|
[966] | 507 | omp_set_num_threads(threads); |
---|
[450] | 508 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 509 | #endif |
---|
| 510 | |
---|
| 511 | // Define VciParams objects |
---|
| 512 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 513 | vci_plen_width, |
---|
| 514 | vci_address_width, |
---|
| 515 | vci_rerror_width, |
---|
| 516 | vci_clen_width, |
---|
| 517 | vci_rflag_width, |
---|
| 518 | vci_srcid_width, |
---|
| 519 | vci_pktid_width, |
---|
| 520 | vci_trdid_width, |
---|
| 521 | vci_wrplen_width> vci_param_int; |
---|
| 522 | |
---|
| 523 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 524 | vci_plen_width, |
---|
| 525 | vci_address_width, |
---|
[718] | 526 | vci_rerror_width, |
---|
[450] | 527 | vci_clen_width, |
---|
| 528 | vci_rflag_width, |
---|
| 529 | vci_srcid_width, |
---|
| 530 | vci_pktid_width, |
---|
| 531 | vci_trdid_width, |
---|
| 532 | vci_wrplen_width> vci_param_ext; |
---|
| 533 | |
---|
| 534 | ///////////////////////////////////////////////////////////////////// |
---|
| 535 | // INT network mapping table |
---|
| 536 | // - two levels address decoding for commands |
---|
| 537 | // - two levels srcid decoding for responses |
---|
[972] | 538 | // - NB_PROCS_MAX + 2 (MWMR, IOBX) local initiators per cluster |
---|
| 539 | // - 4 local targets (MEMC, XICU, MWMR, IOBX) per cluster |
---|
[450] | 540 | ///////////////////////////////////////////////////////////////////// |
---|
[718] | 541 | MappingTable maptab_int( vci_address_width, |
---|
| 542 | IntTab(x_width + y_width, 16 - x_width - y_width), |
---|
| 543 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
---|
[450] | 544 | 0x00FF000000); |
---|
| 545 | |
---|
| 546 | for (size_t x = 0; x < XMAX; x++) |
---|
| 547 | { |
---|
| 548 | for (size_t y = 0; y < YMAX; y++) |
---|
| 549 | { |
---|
[718] | 550 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
[450] | 551 | << (vci_address_width-x_width-y_width); |
---|
[550] | 552 | bool config = true; |
---|
| 553 | bool cacheable = true; |
---|
[450] | 554 | |
---|
| 555 | // the four following segments are defined in all clusters |
---|
| 556 | |
---|
| 557 | std::ostringstream smemc_conf; |
---|
| 558 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
---|
[718] | 559 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
---|
| 560 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); |
---|
[450] | 561 | |
---|
| 562 | std::ostringstream smemc_xram; |
---|
| 563 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
---|
[718] | 564 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
---|
| 565 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); |
---|
[450] | 566 | |
---|
| 567 | std::ostringstream sxicu; |
---|
| 568 | sxicu << "int_seg_xicu_" << x << "_" << y; |
---|
[1050] | 569 | maptab_int.add(Segment(sxicu.str(), SEG_ICU_BASE+offset, SEG_ICU_SIZE, |
---|
[718] | 570 | IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); |
---|
[450] | 571 | |
---|
[972] | 572 | std::ostringstream smwmr; |
---|
| 573 | smwmr << "int_seg_mwmr_" << x << "_" << y; |
---|
| 574 | maptab_int.add(Segment(smwmr.str(), SEG_MWR_BASE+offset, SEG_MWR_SIZE, |
---|
| 575 | IntTab(cluster(x,y), INT_MWMR_TGT_ID), not cacheable)); |
---|
[450] | 576 | |
---|
| 577 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
---|
| 578 | |
---|
[718] | 579 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
---|
[450] | 580 | { |
---|
| 581 | std::ostringstream siobx; |
---|
| 582 | siobx << "int_seg_iobx_" << x << "_" << y; |
---|
[718] | 583 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
---|
[550] | 584 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); |
---|
[450] | 585 | |
---|
| 586 | std::ostringstream stty; |
---|
| 587 | stty << "int_seg_mtty_" << x << "_" << y; |
---|
[1050] | 588 | maptab_int.add(Segment(stty.str(), SEG_TXT_BASE+offset, SEG_TXT_SIZE, |
---|
[550] | 589 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 590 | |
---|
| 591 | std::ostringstream sfbf; |
---|
| 592 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
---|
[718] | 593 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
---|
[550] | 594 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 595 | |
---|
[965] | 596 | std::ostringstream sdsk; |
---|
| 597 | sdsk << "int_seg_disk_" << x << "_" << y; |
---|
| 598 | maptab_int.add(Segment(sdsk.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
---|
[550] | 599 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 600 | |
---|
| 601 | std::ostringstream snic; |
---|
| 602 | snic << "int_seg_mnic_" << x << "_" << y; |
---|
[718] | 603 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
---|
[550] | 604 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 605 | |
---|
| 606 | std::ostringstream srom; |
---|
| 607 | srom << "int_seg_brom_" << x << "_" << y; |
---|
[718] | 608 | maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
---|
[550] | 609 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); |
---|
[450] | 610 | |
---|
[707] | 611 | std::ostringstream spic; |
---|
| 612 | spic << "int_seg_iopi_" << x << "_" << y; |
---|
[718] | 613 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
---|
[707] | 614 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
---|
[450] | 615 | } |
---|
| 616 | |
---|
| 617 | // This define the mapping between the SRCIDs |
---|
| 618 | // and the port index on the local interconnect. |
---|
| 619 | |
---|
[972] | 620 | maptab_int.srcid_map( IntTab( cluster(x,y), MWMR_LOCAL_SRCID ), |
---|
| 621 | IntTab( cluster(x,y), INT_MWMR_INI_ID ) ); |
---|
[450] | 622 | |
---|
[550] | 623 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), |
---|
| 624 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
[450] | 625 | |
---|
[707] | 626 | maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), |
---|
| 627 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
---|
| 628 | |
---|
[802] | 629 | for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) |
---|
[718] | 630 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), |
---|
[550] | 631 | IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); |
---|
[450] | 632 | } |
---|
| 633 | } |
---|
| 634 | std::cout << "INT network " << maptab_int << std::endl; |
---|
| 635 | |
---|
| 636 | ///////////////////////////////////////////////////////////////////////// |
---|
[718] | 637 | // RAM network mapping table |
---|
[450] | 638 | // - two levels address decoding for commands |
---|
| 639 | // - two levels srcid decoding for responses |
---|
[718] | 640 | // - 2 local initiators (MEMC, IOBX) per cluster |
---|
[450] | 641 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
---|
| 642 | // - 1 local target (XRAM) per cluster |
---|
| 643 | //////////////////////////////////////////////////////////////////////// |
---|
| 644 | MappingTable maptab_ram( vci_address_width, |
---|
[718] | 645 | IntTab(x_width+y_width, 0), |
---|
| 646 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
---|
[450] | 647 | 0x00FF000000); |
---|
| 648 | |
---|
| 649 | for (size_t x = 0; x < XMAX; x++) |
---|
| 650 | { |
---|
| 651 | for (size_t y = 0; y < YMAX ; y++) |
---|
[718] | 652 | { |
---|
| 653 | uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
[450] | 654 | << (vci_address_width-x_width-y_width); |
---|
| 655 | |
---|
| 656 | std::ostringstream sxram; |
---|
| 657 | sxram << "ext_seg_xram_" << x << "_" << y; |
---|
[718] | 658 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
---|
| 659 | SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
---|
[450] | 660 | } |
---|
| 661 | } |
---|
| 662 | |
---|
[550] | 663 | // This define the mapping between the initiators SRCID |
---|
| 664 | // and the port index on the RAM local interconnect. |
---|
[1050] | 665 | // This routing table is used to route the response to the |
---|
| 666 | // relevant initiator: external peripherals transactions |
---|
| 667 | // use IOBX port, while MEMC transactions use MEMC port. |
---|
[450] | 668 | |
---|
[965] | 669 | maptab_ram.srcid_map( IntTab( cluster_iob0, DISK_LOCAL_SRCID ), |
---|
[550] | 670 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
[450] | 671 | |
---|
[965] | 672 | maptab_ram.srcid_map( IntTab( cluster_iob1, DISK_LOCAL_SRCID ), |
---|
[550] | 673 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 674 | |
---|
[718] | 675 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
---|
| 676 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 677 | |
---|
| 678 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
---|
| 679 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 680 | |
---|
[1050] | 681 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNRX_LOCAL_SRCID ), |
---|
| 682 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 683 | |
---|
| 684 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNRX_LOCAL_SRCID ), |
---|
| 685 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 686 | |
---|
| 687 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNTX_LOCAL_SRCID ), |
---|
| 688 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
---|
| 689 | |
---|
| 690 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNTX_LOCAL_SRCID ), |
---|
| 691 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
---|
| 692 | |
---|
[718] | 693 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
---|
| 694 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
---|
| 695 | |
---|
| 696 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
---|
[550] | 697 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
---|
| 698 | |
---|
[450] | 699 | std::cout << "RAM network " << maptab_ram << std::endl; |
---|
| 700 | |
---|
| 701 | /////////////////////////////////////////////////////////////////////// |
---|
[718] | 702 | // IOX network mapping table |
---|
[1050] | 703 | // - two levels address decoding for commands |
---|
[450] | 704 | // - two levels srcid decoding for responses |
---|
[1050] | 705 | // - 5 initiators (IOB0, IOB1, DISK, MNIC, IOPI) |
---|
| 706 | // - 8 targets (IOB0, IOB1, DISK, MTTY, FBUF, BROM, MNIC, IOPI) |
---|
[718] | 707 | // |
---|
| 708 | // Address bit 32 is used to determine if a command must be routed to |
---|
| 709 | // IOB0 or IOB1. |
---|
[450] | 710 | /////////////////////////////////////////////////////////////////////// |
---|
[718] | 711 | MappingTable maptab_iox( |
---|
| 712 | vci_address_width, |
---|
| 713 | IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), |
---|
| 714 | IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), |
---|
| 715 | 0x00FF000000); |
---|
[450] | 716 | |
---|
[707] | 717 | // External peripherals segments |
---|
[718] | 718 | // When there is more than one cluster, external peripherals can be accessed |
---|
[707] | 719 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
---|
[718] | 720 | |
---|
| 721 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
---|
| 722 | << (vci_address_width - x_width - y_width); |
---|
| 723 | |
---|
[1050] | 724 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TXT_BASE + iob0_base, SEG_TXT_SIZE, |
---|
[718] | 725 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 726 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
---|
| 727 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[965] | 728 | maptab_iox.add(Segment("iox_seg_disk_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
---|
| 729 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
[718] | 730 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
---|
| 731 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 732 | maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, |
---|
| 733 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
| 734 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
---|
| 735 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
| 736 | |
---|
[707] | 737 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 738 | { |
---|
[718] | 739 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
---|
| 740 | << (vci_address_width - x_width - y_width); |
---|
| 741 | |
---|
[1050] | 742 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TXT_BASE + iob1_base, SEG_TXT_SIZE, |
---|
[718] | 743 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
---|
| 744 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
---|
| 745 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
---|
[965] | 746 | maptab_iox.add(Segment("iox_seg_disk_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
---|
| 747 | IntTab(0, IOX_DISK_TGT_ID), false)); |
---|
[718] | 748 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
---|
| 749 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
---|
| 750 | maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, |
---|
| 751 | IntTab(0, IOX_BROM_TGT_ID), false)); |
---|
| 752 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
---|
| 753 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
---|
[707] | 754 | } |
---|
[450] | 755 | |
---|
[718] | 756 | // If there is more than one cluster, external peripherals |
---|
[707] | 757 | // can access RAM through two segments (IOB0 / IOB1). |
---|
| 758 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
---|
[718] | 759 | // and the choice depends on address bit A[32]. |
---|
[450] | 760 | for (size_t x = 0; x < XMAX; x++) |
---|
| 761 | { |
---|
| 762 | for (size_t y = 0; y < YMAX ; y++) |
---|
[718] | 763 | { |
---|
| 764 | const bool wti = true; |
---|
| 765 | const bool cacheable = true; |
---|
[450] | 766 | |
---|
[718] | 767 | const uint64_t offset = ((uint64_t)cluster(x,y)) |
---|
| 768 | << (vci_address_width-x_width-y_width); |
---|
| 769 | |
---|
[1050] | 770 | const uint64_t xicu_base = SEG_ICU_BASE + offset; |
---|
[718] | 771 | |
---|
| 772 | if ( (y & 0x1) == 0 ) // use IOB0 |
---|
[450] | 773 | { |
---|
[718] | 774 | std::ostringstream sxcu0; |
---|
| 775 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
---|
[1050] | 776 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_ICU_SIZE, |
---|
[718] | 777 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
---|
| 778 | |
---|
| 779 | std::ostringstream siob0; |
---|
| 780 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
---|
[1050] | 781 | maptab_iox.add(Segment(siob0.str(), offset, SEG_ICU_BASE, |
---|
[718] | 782 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
---|
[707] | 783 | } |
---|
[718] | 784 | else // USE IOB1 |
---|
[707] | 785 | { |
---|
[718] | 786 | std::ostringstream sxcu1; |
---|
| 787 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
---|
[1050] | 788 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_ICU_SIZE, |
---|
[718] | 789 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
---|
| 790 | |
---|
| 791 | std::ostringstream siob1; |
---|
| 792 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
---|
[1050] | 793 | maptab_iox.add(Segment(siob1.str(), offset, SEG_ICU_BASE, |
---|
[718] | 794 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
---|
[450] | 795 | } |
---|
| 796 | } |
---|
| 797 | } |
---|
| 798 | |
---|
[707] | 799 | // This define the mapping between the external initiators (SRCID) |
---|
[1050] | 800 | // and the initiator port index on the IOX local interconnect. |
---|
[550] | 801 | |
---|
[965] | 802 | maptab_iox.srcid_map( IntTab( 0, DISK_LOCAL_SRCID ) , |
---|
| 803 | IntTab( 0, IOX_DISK_INI_ID ) ); |
---|
[1050] | 804 | |
---|
[718] | 805 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
---|
| 806 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
---|
[1050] | 807 | |
---|
[718] | 808 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
---|
| 809 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
---|
| 810 | |
---|
[1050] | 811 | maptab_iox.srcid_map( IntTab( 0, MNRX_LOCAL_SRCID ) , |
---|
| 812 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
---|
| 813 | |
---|
| 814 | maptab_iox.srcid_map( IntTab( 0, MNTX_LOCAL_SRCID ) , |
---|
| 815 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
---|
| 816 | |
---|
[707] | 817 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 818 | { |
---|
[718] | 819 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
---|
| 820 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
---|
[707] | 821 | } |
---|
[550] | 822 | |
---|
[450] | 823 | std::cout << "IOX network " << maptab_iox << std::endl; |
---|
| 824 | |
---|
| 825 | //////////////////// |
---|
| 826 | // Signals |
---|
| 827 | /////////////////// |
---|
| 828 | |
---|
[550] | 829 | sc_clock signal_clk("clk"); |
---|
| 830 | sc_signal<bool> signal_resetn("resetn"); |
---|
[450] | 831 | |
---|
[584] | 832 | sc_signal<bool> signal_irq_false; |
---|
[965] | 833 | sc_signal<bool> signal_irq_disk; |
---|
[1050] | 834 | sc_signal<bool> signal_irq_mtty_rx[NB_TXT_CHANNELS]; |
---|
[550] | 835 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 836 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
[450] | 837 | |
---|
| 838 | // VCI signals for IOX network |
---|
[550] | 839 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
---|
| 840 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
---|
[965] | 841 | VciSignals<vci_param_ext> signal_vci_ini_disk("signal_vci_ini_disk"); |
---|
[707] | 842 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
[1050] | 843 | VciSignals<vci_param_ext> signal_vci_ini_mnic("signal_vci_ini_mnic"); |
---|
[450] | 844 | |
---|
[550] | 845 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
---|
| 846 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
---|
| 847 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 848 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 849 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 850 | VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); |
---|
[965] | 851 | VciSignals<vci_param_ext> signal_vci_tgt_disk("signal_vci_tgt_disk"); |
---|
[953] | 852 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); |
---|
[450] | 853 | |
---|
[1002] | 854 | // Horizontal inter-clusters INT_CMD DSPIN |
---|
| 855 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_inc = |
---|
| 856 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX); |
---|
| 857 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_dec = |
---|
| 858 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX); |
---|
[450] | 859 | |
---|
[1002] | 860 | // Horizontal inter-clusters INT_RSP DSPIN |
---|
| 861 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_inc = |
---|
| 862 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX); |
---|
| 863 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_dec = |
---|
| 864 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX); |
---|
[450] | 865 | |
---|
[1002] | 866 | // Horizontal inter-clusters INT_M2P DSPIN |
---|
| 867 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_inc = |
---|
| 868 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_inc", XMAX-1, YMAX); |
---|
| 869 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_dec = |
---|
| 870 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_dec", XMAX-1, YMAX); |
---|
[450] | 871 | |
---|
[1002] | 872 | // Horizontal inter-clusters INT_P2M DSPIN |
---|
| 873 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_inc = |
---|
| 874 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_inc", XMAX-1, YMAX); |
---|
| 875 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_dec = |
---|
| 876 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_dec", XMAX-1, YMAX); |
---|
[450] | 877 | |
---|
[1002] | 878 | // Horizontal inter-clusters INT_CLA DSPIN |
---|
| 879 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_inc = |
---|
| 880 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_inc", XMAX-1, YMAX); |
---|
| 881 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_dec = |
---|
| 882 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_dec", XMAX-1, YMAX); |
---|
| 883 | |
---|
| 884 | |
---|
| 885 | // Vertical inter-clusters INT_CMD DSPIN |
---|
| 886 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_inc = |
---|
| 887 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1); |
---|
| 888 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_dec = |
---|
| 889 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1); |
---|
| 890 | |
---|
| 891 | // Vertical inter-clusters INT_RSP DSPIN |
---|
| 892 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_inc = |
---|
| 893 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1); |
---|
| 894 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_dec = |
---|
| 895 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1); |
---|
| 896 | |
---|
| 897 | // Vertical inter-clusters INT_M2P DSPIN |
---|
| 898 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_inc = |
---|
| 899 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_inc", XMAX, YMAX-1); |
---|
| 900 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_dec = |
---|
| 901 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_dec", XMAX, YMAX-1); |
---|
| 902 | |
---|
| 903 | // Vertical inter-clusters INT_P2M DSPIN |
---|
| 904 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_inc = |
---|
| 905 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_inc", XMAX, YMAX-1); |
---|
| 906 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_dec = |
---|
| 907 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_dec", XMAX, YMAX-1); |
---|
| 908 | |
---|
| 909 | // Vertical inter-clusters INT_CLA DSPIN |
---|
| 910 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_inc = |
---|
| 911 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_inc", XMAX, YMAX-1); |
---|
| 912 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_dec = |
---|
| 913 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_dec", XMAX, YMAX-1); |
---|
| 914 | |
---|
| 915 | |
---|
| 916 | // Mesh boundaries INT_CMD DSPIN |
---|
| 917 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_in = |
---|
| 918 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4); |
---|
| 919 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_out = |
---|
| 920 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4); |
---|
| 921 | |
---|
| 922 | // Mesh boundaries INT_RSP DSPIN |
---|
| 923 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_in = |
---|
| 924 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4); |
---|
| 925 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_out = |
---|
| 926 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4); |
---|
| 927 | |
---|
| 928 | // Mesh boundaries INT_M2P DSPIN |
---|
| 929 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_in = |
---|
| 930 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2p_in", XMAX, YMAX, 4); |
---|
| 931 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_out = |
---|
| 932 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2P_out", XMAX, YMAX, 4); |
---|
| 933 | |
---|
| 934 | // Mesh boundaries INT_P2M DSPIN |
---|
| 935 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_in = |
---|
| 936 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_in", XMAX, YMAX, 4); |
---|
| 937 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_out = |
---|
| 938 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_out", XMAX, YMAX, 4); |
---|
| 939 | |
---|
| 940 | // Mesh boundaries INT_CLA DSPIN |
---|
| 941 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_in = |
---|
| 942 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_in", XMAX, YMAX, 4); |
---|
| 943 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_out = |
---|
| 944 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_out", XMAX, YMAX, 4); |
---|
| 945 | |
---|
| 946 | |
---|
| 947 | // Horizontal inter-clusters RAM_CMD DSPIN |
---|
[450] | 948 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
---|
| 949 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
---|
| 950 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
---|
| 951 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
---|
[1002] | 952 | |
---|
| 953 | // Horizontal inter-clusters RAM_RSP DSPIN |
---|
[450] | 954 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
---|
| 955 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
---|
| 956 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
---|
| 957 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
---|
| 958 | |
---|
[1002] | 959 | // Vertical inter-clusters RAM_CMD DSPIN |
---|
[450] | 960 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
---|
| 961 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
---|
| 962 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
---|
| 963 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
---|
[1002] | 964 | |
---|
| 965 | // Vertical inter-clusters RAM_RSP DSPIN |
---|
[450] | 966 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
---|
| 967 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
---|
| 968 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
---|
| 969 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
---|
| 970 | |
---|
[1002] | 971 | // Mesh boundaries RAM_CMD DSPIN |
---|
[450] | 972 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
---|
| 973 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
---|
| 974 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
---|
| 975 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
---|
[1002] | 976 | |
---|
| 977 | // Mesh boundaries RAM_RSP DSPIN |
---|
[450] | 978 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
---|
| 979 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
---|
| 980 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
---|
| 981 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
---|
| 982 | |
---|
[1002] | 983 | // SD card signals |
---|
| 984 | sc_signal<bool> signal_sdc_clk; |
---|
| 985 | sc_signal<bool> signal_sdc_cmd_enable_to_card; |
---|
| 986 | sc_signal<bool> signal_sdc_cmd_value_to_card; |
---|
| 987 | sc_signal<bool> signal_sdc_dat_enable_to_card; |
---|
| 988 | sc_signal<bool> signal_sdc_dat_value_to_card[4]; |
---|
| 989 | sc_signal<bool> signal_sdc_cmd_enable_from_card; |
---|
| 990 | sc_signal<bool> signal_sdc_cmd_value_from_card; |
---|
| 991 | sc_signal<bool> signal_sdc_dat_enable_from_card; |
---|
| 992 | sc_signal<bool> signal_sdc_dat_value_from_card[4]; |
---|
| 993 | |
---|
[1046] | 994 | //////////////////////////////////////////////// |
---|
| 995 | // Load the preloader code in the ROM |
---|
| 996 | //////////////////////////////////////////////// |
---|
[450] | 997 | |
---|
[965] | 998 | soclib::common::Loader loader(soft_name); |
---|
[450] | 999 | |
---|
[965] | 1000 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 1001 | proc_iss::set_loader(loader); |
---|
[450] | 1002 | |
---|
[965] | 1003 | //////////////////////////////////////// |
---|
| 1004 | // Instanciated Hardware Components |
---|
| 1005 | //////////////////////////////////////// |
---|
[450] | 1006 | |
---|
[965] | 1007 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
---|
[450] | 1008 | |
---|
[965] | 1009 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
---|
[1050] | 1010 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; |
---|
[718] | 1011 | |
---|
[965] | 1012 | // IOX network |
---|
| 1013 | VciIoxNetwork<vci_param_ext>* iox_network; |
---|
| 1014 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
---|
| 1015 | maptab_iox, |
---|
| 1016 | nb_iox_targets, |
---|
| 1017 | nb_iox_initiators ); |
---|
| 1018 | // boot ROM |
---|
| 1019 | VciSimpleRom<vci_param_ext>* brom; |
---|
| 1020 | brom = new VciSimpleRom<vci_param_ext>( "brom", |
---|
| 1021 | IntTab(0, IOX_BROM_TGT_ID), |
---|
| 1022 | maptab_iox, |
---|
| 1023 | loader ); |
---|
[1050] | 1024 | // Ethernet Controller |
---|
| 1025 | VciMasterNic<vci_param_ext>* mnic; |
---|
| 1026 | mnic = new VciMasterNic<vci_param_ext>( "mnic", |
---|
| 1027 | maptab_iox, |
---|
| 1028 | IntTab(0, MNRX_LOCAL_SRCID), |
---|
| 1029 | IntTab(0, MNTX_LOCAL_SRCID), |
---|
| 1030 | IntTab(0, IOX_MNIC_TGT_ID), |
---|
| 1031 | NB_NIC_CHANNELS, |
---|
| 1032 | 64, // burst length |
---|
| 1033 | MNIC_MAC_4, // default MAC address (LSB) |
---|
| 1034 | MNIC_MAC_2, // default MAC address (MSB) |
---|
| 1035 | 1, // NIC_MODE_SYNTHESIS |
---|
| 1036 | 12); // INTER_FRAME_GAP |
---|
[450] | 1037 | |
---|
[965] | 1038 | // Frame Buffer |
---|
| 1039 | VciFrameBuffer<vci_param_ext>* fbuf; |
---|
| 1040 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
---|
| 1041 | IntTab(0, IOX_FBUF_TGT_ID), |
---|
| 1042 | maptab_iox, |
---|
| 1043 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[450] | 1044 | |
---|
[965] | 1045 | // Disk |
---|
| 1046 | std::vector<std::string> filenames; |
---|
| 1047 | filenames.push_back(disk_name); // one single disk |
---|
| 1048 | |
---|
| 1049 | #if ( USE_IOC_HBA ) |
---|
[966] | 1050 | |
---|
[965] | 1051 | VciMultiAhci<vci_param_ext>* disk; |
---|
| 1052 | disk = new VciMultiAhci<vci_param_ext>( "disk", |
---|
| 1053 | maptab_iox, |
---|
| 1054 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 1055 | IntTab(0, IOX_DISK_TGT_ID), |
---|
| 1056 | filenames, |
---|
| 1057 | 512, // block size |
---|
| 1058 | 64, // burst size (bytes) |
---|
| 1059 | 0 ); // disk latency |
---|
[1002] | 1060 | #elif ( USE_IOC_BDV ) |
---|
[966] | 1061 | |
---|
[965] | 1062 | VciBlockDeviceTsar<vci_param_ext>* disk; |
---|
| 1063 | disk = new VciBlockDeviceTsar<vci_param_ext>( "disk", |
---|
[550] | 1064 | maptab_iox, |
---|
[965] | 1065 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 1066 | IntTab(0, IOX_DISK_TGT_ID), |
---|
[550] | 1067 | disk_name, |
---|
[714] | 1068 | 512, // block size |
---|
[718] | 1069 | 64, // burst size (bytes) |
---|
| 1070 | 0 ); // disk latency |
---|
[1002] | 1071 | #elif ( USE_IOC_SDC ) |
---|
| 1072 | |
---|
| 1073 | VciAhciSdc<vci_param_ext>* disk; |
---|
| 1074 | disk = new VciAhciSdc<vci_param_ext>( "disk", |
---|
| 1075 | maptab_iox, |
---|
| 1076 | IntTab(0, DISK_LOCAL_SRCID), |
---|
| 1077 | IntTab(0, IOX_DISK_TGT_ID), |
---|
| 1078 | 64 ); // burst size (bytes) |
---|
| 1079 | SdCard* card; |
---|
| 1080 | card = new SdCard( "card", |
---|
| 1081 | disk_name, |
---|
| 1082 | 10, // RX one block latency |
---|
| 1083 | 10 ); // TX one block latency |
---|
[965] | 1084 | #endif |
---|
[450] | 1085 | |
---|
[965] | 1086 | // Multi-TTY controller |
---|
| 1087 | std::vector<std::string> vect_names; |
---|
[1050] | 1088 | for( size_t tid = 0 ; tid < NB_TXT_CHANNELS ; tid++ ) |
---|
[965] | 1089 | { |
---|
| 1090 | std::ostringstream term_name; |
---|
| 1091 | term_name << "term" << tid; |
---|
| 1092 | |
---|
[707] | 1093 | vect_names.push_back(term_name.str().c_str()); |
---|
| 1094 | } |
---|
| 1095 | VciMultiTty<vci_param_ext>* mtty; |
---|
| 1096 | mtty = new VciMultiTty<vci_param_ext>( "mtty", |
---|
| 1097 | IntTab(0, IOX_MTTY_TGT_ID), |
---|
[718] | 1098 | maptab_iox, |
---|
[707] | 1099 | vect_names); |
---|
| 1100 | |
---|
[965] | 1101 | // IOPIC |
---|
| 1102 | VciIopic<vci_param_ext>* iopi; |
---|
| 1103 | iopi = new VciIopic<vci_param_ext>( "iopi", |
---|
| 1104 | maptab_iox, |
---|
| 1105 | IntTab(0, IOPI_LOCAL_SRCID), |
---|
| 1106 | IntTab(0, IOX_IOPI_TGT_ID), |
---|
| 1107 | 32 ); // number of input HWI |
---|
| 1108 | // Clusters |
---|
| 1109 | TsarIobCluster<vci_param_int, |
---|
| 1110 | vci_param_ext, |
---|
| 1111 | dspin_int_cmd_width, |
---|
| 1112 | dspin_int_rsp_width, |
---|
| 1113 | dspin_ram_cmd_width, |
---|
| 1114 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
---|
[450] | 1115 | |
---|
[972] | 1116 | unsigned int coproc_type; |
---|
| 1117 | if ( USE_MWR_CPY ) coproc_type = MWR_COPROC_CPY; |
---|
| 1118 | if ( USE_MWR_DCT ) coproc_type = MWR_COPROC_DCT; |
---|
| 1119 | if ( USE_MWR_GCD ) coproc_type = MWR_COPROC_GCD; |
---|
| 1120 | |
---|
[981] | 1121 | #if USE_OPENMP |
---|
[450] | 1122 | #pragma omp parallel |
---|
| 1123 | { |
---|
| 1124 | #pragma omp for |
---|
| 1125 | #endif |
---|
| 1126 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
---|
| 1127 | { |
---|
| 1128 | size_t x = i / YMAX; |
---|
| 1129 | size_t y = i % YMAX; |
---|
| 1130 | |
---|
[981] | 1131 | #if USE_OPENMP |
---|
[450] | 1132 | #pragma omp critical |
---|
| 1133 | { |
---|
| 1134 | #endif |
---|
| 1135 | std::cout << std::endl; |
---|
| 1136 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
---|
| 1137 | std::cout << std::endl; |
---|
| 1138 | |
---|
[718] | 1139 | const bool is_iob0 = (cluster(x,y) == cluster_iob0); |
---|
| 1140 | const bool is_iob1 = (cluster(x,y) == cluster_iob1); |
---|
| 1141 | const bool is_io_cluster = is_iob0 || is_iob1; |
---|
| 1142 | |
---|
| 1143 | const int iox_iob_ini_id = is_iob0 ? |
---|
| 1144 | IOX_IOB0_INI_ID : |
---|
| 1145 | IOX_IOB1_INI_ID ; |
---|
| 1146 | const int iox_iob_tgt_id = is_iob0 ? |
---|
| 1147 | IOX_IOB0_TGT_ID : |
---|
| 1148 | IOX_IOB1_TGT_ID ; |
---|
| 1149 | |
---|
[972] | 1150 | |
---|
[450] | 1151 | std::ostringstream sc; |
---|
| 1152 | sc << "cluster_" << x << "_" << y; |
---|
| 1153 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
---|
| 1154 | vci_param_ext, |
---|
| 1155 | dspin_int_cmd_width, |
---|
| 1156 | dspin_int_rsp_width, |
---|
| 1157 | dspin_ram_cmd_width, |
---|
| 1158 | dspin_ram_rsp_width> |
---|
| 1159 | ( |
---|
| 1160 | sc.str().c_str(), |
---|
| 1161 | NB_PROCS_MAX, |
---|
| 1162 | x, |
---|
| 1163 | y, |
---|
| 1164 | XMAX, |
---|
| 1165 | YMAX, |
---|
| 1166 | |
---|
| 1167 | maptab_int, |
---|
| 1168 | maptab_ram, |
---|
| 1169 | maptab_iox, |
---|
| 1170 | |
---|
| 1171 | x_width, |
---|
| 1172 | y_width, |
---|
| 1173 | vci_srcid_width - x_width - y_width, // l_id width, |
---|
[802] | 1174 | p_width, |
---|
[450] | 1175 | |
---|
| 1176 | INT_MEMC_TGT_ID, |
---|
| 1177 | INT_XICU_TGT_ID, |
---|
[972] | 1178 | INT_MWMR_TGT_ID, |
---|
[450] | 1179 | INT_IOBX_TGT_ID, |
---|
| 1180 | |
---|
| 1181 | INT_PROC_INI_ID, |
---|
[972] | 1182 | INT_MWMR_INI_ID, |
---|
[450] | 1183 | INT_IOBX_INI_ID, |
---|
| 1184 | |
---|
| 1185 | RAM_XRAM_TGT_ID, |
---|
| 1186 | |
---|
| 1187 | RAM_MEMC_INI_ID, |
---|
[550] | 1188 | RAM_IOBX_INI_ID, |
---|
[450] | 1189 | |
---|
[718] | 1190 | is_io_cluster, |
---|
| 1191 | iox_iob_tgt_id, |
---|
| 1192 | iox_iob_ini_id, |
---|
| 1193 | |
---|
[450] | 1194 | MEMC_WAYS, |
---|
| 1195 | MEMC_SETS, |
---|
| 1196 | L1_IWAYS, |
---|
| 1197 | L1_ISETS, |
---|
| 1198 | L1_DWAYS, |
---|
| 1199 | L1_DSETS, |
---|
| 1200 | XRAM_LATENCY, |
---|
[1050] | 1201 | ICU_NB_HWI, |
---|
| 1202 | ICU_NB_PTI, |
---|
| 1203 | ICU_NB_WTI, |
---|
| 1204 | ICU_NB_OUT, |
---|
[450] | 1205 | |
---|
[972] | 1206 | coproc_type, |
---|
| 1207 | |
---|
[450] | 1208 | loader, |
---|
| 1209 | |
---|
| 1210 | frozen_cycles, |
---|
[1030] | 1211 | debug_ok, |
---|
[450] | 1212 | debug_from, |
---|
[1030] | 1213 | debug_proc_id, |
---|
| 1214 | debug_memc_id, |
---|
| 1215 | debug_iob |
---|
[450] | 1216 | ); |
---|
| 1217 | |
---|
[981] | 1218 | #if USE_OPENMP |
---|
[450] | 1219 | } // end critical |
---|
| 1220 | #endif |
---|
| 1221 | } // end for |
---|
[981] | 1222 | #if USE_OPENMP |
---|
[450] | 1223 | } |
---|
| 1224 | #endif |
---|
| 1225 | |
---|
| 1226 | std::cout << std::endl; |
---|
| 1227 | |
---|
| 1228 | /////////////////////////////////////////////////////////////////////////////// |
---|
[718] | 1229 | // Net-list |
---|
[450] | 1230 | /////////////////////////////////////////////////////////////////////////////// |
---|
| 1231 | |
---|
| 1232 | // IOX network connexion |
---|
[584] | 1233 | iox_network->p_clk (signal_clk); |
---|
| 1234 | iox_network->p_resetn (signal_resetn); |
---|
| 1235 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
---|
[965] | 1236 | iox_network->p_to_ini[IOX_DISK_INI_ID] (signal_vci_ini_disk); |
---|
[707] | 1237 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
---|
[1050] | 1238 | iox_network->p_to_ini[IOX_MNIC_INI_ID] (signal_vci_ini_mnic); |
---|
[707] | 1239 | |
---|
[584] | 1240 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
---|
| 1241 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
---|
| 1242 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
---|
| 1243 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
---|
| 1244 | iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); |
---|
[965] | 1245 | iox_network->p_to_tgt[IOX_DISK_TGT_ID] (signal_vci_tgt_disk); |
---|
[707] | 1246 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
---|
[450] | 1247 | |
---|
[718] | 1248 | if (cluster_iob0 != cluster_iob1) |
---|
| 1249 | { |
---|
| 1250 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
---|
| 1251 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
---|
| 1252 | } |
---|
| 1253 | |
---|
[965] | 1254 | // DISK connexion |
---|
[1002] | 1255 | |
---|
| 1256 | #if ( USE_IOC_HBA ) |
---|
| 1257 | |
---|
[965] | 1258 | disk->p_clk (signal_clk); |
---|
| 1259 | disk->p_resetn (signal_resetn); |
---|
| 1260 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1261 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
| 1262 | disk->p_channel_irq[0] (signal_irq_disk); |
---|
[1002] | 1263 | |
---|
| 1264 | #elif ( USE_IOC_BDV ) |
---|
| 1265 | |
---|
| 1266 | disk->p_clk (signal_clk); |
---|
| 1267 | disk->p_resetn (signal_resetn); |
---|
| 1268 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1269 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
[965] | 1270 | disk->p_irq (signal_irq_disk); |
---|
[1002] | 1271 | |
---|
| 1272 | #elif ( USE_IOC_SDC ) |
---|
| 1273 | |
---|
| 1274 | disk->p_clk (signal_clk); |
---|
| 1275 | disk->p_resetn (signal_resetn); |
---|
| 1276 | disk->p_vci_target (signal_vci_tgt_disk); |
---|
| 1277 | disk->p_vci_initiator (signal_vci_ini_disk); |
---|
| 1278 | disk->p_irq (signal_irq_disk); |
---|
| 1279 | |
---|
| 1280 | disk->p_sdc_clk (signal_sdc_clk); |
---|
| 1281 | disk->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_to_card); |
---|
| 1282 | disk->p_sdc_cmd_value_out (signal_sdc_cmd_value_to_card); |
---|
| 1283 | disk->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_from_card); |
---|
| 1284 | disk->p_sdc_cmd_value_in (signal_sdc_cmd_value_from_card); |
---|
| 1285 | disk->p_sdc_dat_enable_out (signal_sdc_dat_enable_to_card); |
---|
| 1286 | disk->p_sdc_dat_value_out[0] (signal_sdc_dat_value_to_card[0]); |
---|
| 1287 | disk->p_sdc_dat_value_out[1] (signal_sdc_dat_value_to_card[1]); |
---|
| 1288 | disk->p_sdc_dat_value_out[2] (signal_sdc_dat_value_to_card[2]); |
---|
| 1289 | disk->p_sdc_dat_value_out[3] (signal_sdc_dat_value_to_card[3]); |
---|
| 1290 | disk->p_sdc_dat_enable_in (signal_sdc_dat_enable_from_card); |
---|
| 1291 | disk->p_sdc_dat_value_in[0] (signal_sdc_dat_value_from_card[0]); |
---|
| 1292 | disk->p_sdc_dat_value_in[1] (signal_sdc_dat_value_from_card[1]); |
---|
| 1293 | disk->p_sdc_dat_value_in[2] (signal_sdc_dat_value_from_card[2]); |
---|
| 1294 | disk->p_sdc_dat_value_in[3] (signal_sdc_dat_value_from_card[3]); |
---|
| 1295 | |
---|
| 1296 | card->p_clk (signal_clk); |
---|
| 1297 | card->p_resetn (signal_resetn); |
---|
| 1298 | |
---|
| 1299 | card->p_sdc_clk (signal_sdc_clk); |
---|
| 1300 | card->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_from_card); |
---|
| 1301 | card->p_sdc_cmd_value_out (signal_sdc_cmd_value_from_card); |
---|
| 1302 | card->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_to_card); |
---|
| 1303 | card->p_sdc_cmd_value_in (signal_sdc_cmd_value_to_card); |
---|
| 1304 | card->p_sdc_dat_enable_out (signal_sdc_dat_enable_from_card); |
---|
| 1305 | card->p_sdc_dat_value_out[0] (signal_sdc_dat_value_from_card[0]); |
---|
| 1306 | card->p_sdc_dat_value_out[1] (signal_sdc_dat_value_from_card[1]); |
---|
| 1307 | card->p_sdc_dat_value_out[2] (signal_sdc_dat_value_from_card[2]); |
---|
| 1308 | card->p_sdc_dat_value_out[3] (signal_sdc_dat_value_from_card[3]); |
---|
| 1309 | card->p_sdc_dat_enable_in (signal_sdc_dat_enable_to_card); |
---|
| 1310 | card->p_sdc_dat_value_in[0] (signal_sdc_dat_value_to_card[0]); |
---|
| 1311 | card->p_sdc_dat_value_in[1] (signal_sdc_dat_value_to_card[1]); |
---|
| 1312 | card->p_sdc_dat_value_in[2] (signal_sdc_dat_value_to_card[2]); |
---|
| 1313 | card->p_sdc_dat_value_in[3] (signal_sdc_dat_value_to_card[3]); |
---|
| 1314 | |
---|
[965] | 1315 | #endif |
---|
[450] | 1316 | |
---|
[965] | 1317 | std::cout << " - DISK connected" << std::endl; |
---|
[450] | 1318 | |
---|
| 1319 | // FBUF connexion |
---|
[550] | 1320 | fbuf->p_clk (signal_clk); |
---|
| 1321 | fbuf->p_resetn (signal_resetn); |
---|
| 1322 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
[450] | 1323 | |
---|
| 1324 | std::cout << " - FBUF connected" << std::endl; |
---|
| 1325 | |
---|
| 1326 | // MNIC connexion |
---|
[550] | 1327 | mnic->p_clk (signal_clk); |
---|
| 1328 | mnic->p_resetn (signal_resetn); |
---|
[1050] | 1329 | mnic->p_vci_tgt (signal_vci_tgt_mnic); |
---|
| 1330 | mnic->p_vci_ini (signal_vci_ini_mnic); |
---|
[450] | 1331 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 1332 | { |
---|
[550] | 1333 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 1334 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
[450] | 1335 | } |
---|
| 1336 | |
---|
| 1337 | std::cout << " - MNIC connected" << std::endl; |
---|
| 1338 | |
---|
| 1339 | // BROM connexion |
---|
[550] | 1340 | brom->p_clk (signal_clk); |
---|
| 1341 | brom->p_resetn (signal_resetn); |
---|
| 1342 | brom->p_vci (signal_vci_tgt_brom); |
---|
[450] | 1343 | |
---|
| 1344 | std::cout << " - BROM connected" << std::endl; |
---|
| 1345 | |
---|
| 1346 | // MTTY connexion |
---|
[550] | 1347 | mtty->p_clk (signal_clk); |
---|
| 1348 | mtty->p_resetn (signal_resetn); |
---|
| 1349 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
[1050] | 1350 | for ( size_t i=0 ; i<NB_TXT_CHANNELS ; i++ ) |
---|
[874] | 1351 | { |
---|
| 1352 | mtty->p_irq[i] (signal_irq_mtty_rx[i]); |
---|
| 1353 | } |
---|
[450] | 1354 | std::cout << " - MTTY connected" << std::endl; |
---|
| 1355 | |
---|
[707] | 1356 | // IOPI connexion |
---|
[718] | 1357 | iopi->p_clk (signal_clk); |
---|
| 1358 | iopi->p_resetn (signal_resetn); |
---|
| 1359 | iopi->p_vci_target (signal_vci_tgt_iopi); |
---|
| 1360 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
---|
[707] | 1361 | for ( size_t i=0 ; i<32 ; i++) |
---|
[450] | 1362 | { |
---|
[707] | 1363 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 1364 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
---|
[1050] | 1365 | else if(i < 4+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-4]); |
---|
| 1366 | else if(i < 12) iopi->p_hwi[i] (signal_irq_false); |
---|
| 1367 | else if(i < 13) iopi->p_hwi[i] (signal_irq_disk); |
---|
[874] | 1368 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
---|
[1050] | 1369 | else if(i < 16+NB_TXT_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
---|
[707] | 1370 | else iopi->p_hwi[i] (signal_irq_false); |
---|
| 1371 | } |
---|
[584] | 1372 | |
---|
[707] | 1373 | std::cout << " - IOPIC connected" << std::endl; |
---|
[584] | 1374 | |
---|
[718] | 1375 | |
---|
[707] | 1376 | // IOB0 cluster connexion to IOX network |
---|
[718] | 1377 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
---|
| 1378 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
---|
[584] | 1379 | |
---|
[718] | 1380 | // IOB1 cluster connexion to IOX network |
---|
[707] | 1381 | // (only when there is more than 1 cluster) |
---|
| 1382 | if ( cluster_iob0 != cluster_iob1 ) |
---|
| 1383 | { |
---|
| 1384 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
---|
| 1385 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
---|
[450] | 1386 | } |
---|
| 1387 | |
---|
| 1388 | // All clusters Clock & RESET connexions |
---|
| 1389 | for ( size_t x = 0; x < (XMAX); x++ ) |
---|
| 1390 | { |
---|
| 1391 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1392 | { |
---|
| 1393 | clusters[x][y]->p_clk (signal_clk); |
---|
| 1394 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 1395 | } |
---|
| 1396 | } |
---|
| 1397 | |
---|
| 1398 | // Inter Clusters horizontal connections |
---|
| 1399 | if (XMAX > 1) |
---|
| 1400 | { |
---|
| 1401 | for (size_t x = 0; x < (XMAX-1); x++) |
---|
| 1402 | { |
---|
| 1403 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1404 | { |
---|
[1002] | 1405 | clusters[x][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_int_cmd_h_inc[x][y]); |
---|
| 1406 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_int_cmd_h_inc[x][y]); |
---|
| 1407 | clusters[x][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_int_cmd_h_dec[x][y]); |
---|
| 1408 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_int_cmd_h_dec[x][y]); |
---|
[468] | 1409 | |
---|
[1002] | 1410 | clusters[x][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_int_rsp_h_inc[x][y]); |
---|
| 1411 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_int_rsp_h_inc[x][y]); |
---|
| 1412 | clusters[x][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_int_rsp_h_dec[x][y]); |
---|
| 1413 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_int_rsp_h_dec[x][y]); |
---|
[450] | 1414 | |
---|
[1002] | 1415 | clusters[x][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_int_m2p_h_inc[x][y]); |
---|
| 1416 | clusters[x+1][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_int_m2p_h_inc[x][y]); |
---|
| 1417 | clusters[x][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_int_m2p_h_dec[x][y]); |
---|
| 1418 | clusters[x+1][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_int_m2p_h_dec[x][y]); |
---|
| 1419 | |
---|
| 1420 | clusters[x][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_int_p2m_h_inc[x][y]); |
---|
| 1421 | clusters[x+1][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_int_p2m_h_inc[x][y]); |
---|
| 1422 | clusters[x][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_int_p2m_h_dec[x][y]); |
---|
| 1423 | clusters[x+1][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_int_p2m_h_dec[x][y]); |
---|
| 1424 | |
---|
| 1425 | clusters[x][y]->p_dspin_int_cla_out[EAST] (signal_dspin_int_cla_h_inc[x][y]); |
---|
| 1426 | clusters[x+1][y]->p_dspin_int_cla_in[WEST] (signal_dspin_int_cla_h_inc[x][y]); |
---|
| 1427 | clusters[x][y]->p_dspin_int_cla_in[EAST] (signal_dspin_int_cla_h_dec[x][y]); |
---|
| 1428 | clusters[x+1][y]->p_dspin_int_cla_out[WEST] (signal_dspin_int_cla_h_dec[x][y]); |
---|
| 1429 | |
---|
[450] | 1430 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1431 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
---|
| 1432 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
| 1433 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
---|
[1002] | 1434 | |
---|
[450] | 1435 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1436 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
---|
| 1437 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1438 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
---|
| 1439 | } |
---|
| 1440 | } |
---|
| 1441 | } |
---|
| 1442 | |
---|
[718] | 1443 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
---|
[450] | 1444 | |
---|
| 1445 | // Inter Clusters vertical connections |
---|
[718] | 1446 | if (YMAX > 1) |
---|
[450] | 1447 | { |
---|
| 1448 | for (size_t y = 0; y < (YMAX-1); y++) |
---|
| 1449 | { |
---|
| 1450 | for (size_t x = 0; x < XMAX; x++) |
---|
| 1451 | { |
---|
[1002] | 1452 | clusters[x][y]->p_dspin_int_cmd_out[NORTH] (signal_dspin_int_cmd_v_inc[x][y]); |
---|
| 1453 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_int_cmd_v_inc[x][y]); |
---|
| 1454 | clusters[x][y]->p_dspin_int_cmd_in[NORTH] (signal_dspin_int_cmd_v_dec[x][y]); |
---|
| 1455 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_int_cmd_v_dec[x][y]); |
---|
[468] | 1456 | |
---|
[1002] | 1457 | clusters[x][y]->p_dspin_int_rsp_out[NORTH] (signal_dspin_int_rsp_v_inc[x][y]); |
---|
| 1458 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_int_rsp_v_inc[x][y]); |
---|
| 1459 | clusters[x][y]->p_dspin_int_rsp_in[NORTH] (signal_dspin_int_rsp_v_dec[x][y]); |
---|
| 1460 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_int_rsp_v_dec[x][y]); |
---|
[450] | 1461 | |
---|
[1002] | 1462 | clusters[x][y]->p_dspin_int_m2p_out[NORTH] (signal_dspin_int_m2p_v_inc[x][y]); |
---|
| 1463 | clusters[x][y+1]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_int_m2p_v_inc[x][y]); |
---|
| 1464 | clusters[x][y]->p_dspin_int_m2p_in[NORTH] (signal_dspin_int_m2p_v_dec[x][y]); |
---|
| 1465 | clusters[x][y+1]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_int_m2p_v_dec[x][y]); |
---|
| 1466 | |
---|
| 1467 | clusters[x][y]->p_dspin_int_p2m_out[NORTH] (signal_dspin_int_p2m_v_inc[x][y]); |
---|
| 1468 | clusters[x][y+1]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_int_p2m_v_inc[x][y]); |
---|
| 1469 | clusters[x][y]->p_dspin_int_p2m_in[NORTH] (signal_dspin_int_p2m_v_dec[x][y]); |
---|
| 1470 | clusters[x][y+1]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_int_p2m_v_dec[x][y]); |
---|
| 1471 | |
---|
| 1472 | clusters[x][y]->p_dspin_int_cla_out[NORTH] (signal_dspin_int_cla_v_inc[x][y]); |
---|
| 1473 | clusters[x][y+1]->p_dspin_int_cla_in[SOUTH] (signal_dspin_int_cla_v_inc[x][y]); |
---|
| 1474 | clusters[x][y]->p_dspin_int_cla_in[NORTH] (signal_dspin_int_cla_v_dec[x][y]); |
---|
| 1475 | clusters[x][y+1]->p_dspin_int_cla_out[SOUTH] (signal_dspin_int_cla_v_dec[x][y]); |
---|
| 1476 | |
---|
[450] | 1477 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1478 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
---|
| 1479 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
| 1480 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
---|
[1002] | 1481 | |
---|
[450] | 1482 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1483 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
---|
| 1484 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1485 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
---|
| 1486 | } |
---|
| 1487 | } |
---|
| 1488 | } |
---|
| 1489 | |
---|
| 1490 | std::cout << "Vertical connections established" << std::endl; |
---|
| 1491 | |
---|
| 1492 | // East & West boundary cluster connections |
---|
| 1493 | for (size_t y = 0; y < YMAX; y++) |
---|
| 1494 | { |
---|
[1002] | 1495 | clusters[0][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_false_int_cmd_in[0][y][WEST]); |
---|
| 1496 | clusters[0][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_false_int_cmd_out[0][y][WEST]); |
---|
| 1497 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST]); |
---|
| 1498 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST]); |
---|
[468] | 1499 | |
---|
[1002] | 1500 | clusters[0][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_false_int_rsp_in[0][y][WEST]); |
---|
| 1501 | clusters[0][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_false_int_rsp_out[0][y][WEST]); |
---|
| 1502 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST]); |
---|
| 1503 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST]); |
---|
[450] | 1504 | |
---|
[1002] | 1505 | clusters[0][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_false_int_m2p_in[0][y][WEST]); |
---|
| 1506 | clusters[0][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_false_int_m2p_out[0][y][WEST]); |
---|
| 1507 | clusters[XMAX-1][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_false_int_m2p_in[XMAX-1][y][EAST]); |
---|
| 1508 | clusters[XMAX-1][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_false_int_m2p_out[XMAX-1][y][EAST]); |
---|
[450] | 1509 | |
---|
[1002] | 1510 | clusters[0][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_false_int_p2m_in[0][y][WEST]); |
---|
| 1511 | clusters[0][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_false_int_p2m_out[0][y][WEST]); |
---|
| 1512 | clusters[XMAX-1][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_false_int_p2m_in[XMAX-1][y][EAST]); |
---|
| 1513 | clusters[XMAX-1][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_false_int_p2m_out[XMAX-1][y][EAST]); |
---|
| 1514 | |
---|
| 1515 | clusters[0][y]->p_dspin_int_cla_in[WEST] (signal_dspin_false_int_cla_in[0][y][WEST]); |
---|
| 1516 | clusters[0][y]->p_dspin_int_cla_out[WEST] (signal_dspin_false_int_cla_out[0][y][WEST]); |
---|
| 1517 | clusters[XMAX-1][y]->p_dspin_int_cla_in[EAST] (signal_dspin_false_int_cla_in[XMAX-1][y][EAST]); |
---|
| 1518 | clusters[XMAX-1][y]->p_dspin_int_cla_out[EAST] (signal_dspin_false_int_cla_out[XMAX-1][y][EAST]); |
---|
| 1519 | |
---|
| 1520 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
---|
| 1521 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
---|
| 1522 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
---|
| 1523 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
---|
| 1524 | |
---|
| 1525 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
---|
| 1526 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
---|
| 1527 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
---|
| 1528 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
---|
[450] | 1529 | } |
---|
| 1530 | |
---|
| 1531 | std::cout << "East & West boundaries established" << std::endl; |
---|
| 1532 | |
---|
| 1533 | // North & South boundary clusters connections |
---|
| 1534 | for (size_t x = 0; x < XMAX; x++) |
---|
| 1535 | { |
---|
[1002] | 1536 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_false_int_cmd_in[x][0][SOUTH]); |
---|
| 1537 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_false_int_cmd_out[x][0][SOUTH]); |
---|
| 1538 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH]); |
---|
| 1539 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH]); |
---|
[468] | 1540 | |
---|
[1002] | 1541 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_false_int_rsp_in[x][0][SOUTH]); |
---|
| 1542 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_false_int_rsp_out[x][0][SOUTH]); |
---|
| 1543 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH]); |
---|
| 1544 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH]); |
---|
[450] | 1545 | |
---|
[1002] | 1546 | clusters[x][0]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_false_int_m2p_in[x][0][SOUTH]); |
---|
| 1547 | clusters[x][0]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_false_int_m2p_out[x][0][SOUTH]); |
---|
| 1548 | clusters[x][YMAX-1]->p_dspin_int_m2p_in[NORTH] (signal_dspin_false_int_m2p_in[x][YMAX-1][NORTH]); |
---|
| 1549 | clusters[x][YMAX-1]->p_dspin_int_m2p_out[NORTH] (signal_dspin_false_int_m2p_out[x][YMAX-1][NORTH]); |
---|
[450] | 1550 | |
---|
[1002] | 1551 | clusters[x][0]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_false_int_p2m_in[x][0][SOUTH]); |
---|
| 1552 | clusters[x][0]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_false_int_p2m_out[x][0][SOUTH]); |
---|
| 1553 | clusters[x][YMAX-1]->p_dspin_int_p2m_in[NORTH] (signal_dspin_false_int_p2m_in[x][YMAX-1][NORTH]); |
---|
| 1554 | clusters[x][YMAX-1]->p_dspin_int_p2m_out[NORTH] (signal_dspin_false_int_p2m_out[x][YMAX-1][NORTH]); |
---|
| 1555 | |
---|
| 1556 | clusters[x][0]->p_dspin_int_cla_in[SOUTH] (signal_dspin_false_int_cla_in[x][0][SOUTH]); |
---|
| 1557 | clusters[x][0]->p_dspin_int_cla_out[SOUTH] (signal_dspin_false_int_cla_out[x][0][SOUTH]); |
---|
| 1558 | clusters[x][YMAX-1]->p_dspin_int_cla_in[NORTH] (signal_dspin_false_int_cla_in[x][YMAX-1][NORTH]); |
---|
| 1559 | clusters[x][YMAX-1]->p_dspin_int_cla_out[NORTH] (signal_dspin_false_int_cla_out[x][YMAX-1][NORTH]); |
---|
| 1560 | |
---|
| 1561 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
---|
| 1562 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
---|
| 1563 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
---|
| 1564 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
---|
| 1565 | |
---|
| 1566 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
---|
| 1567 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
---|
| 1568 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
---|
| 1569 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
---|
[450] | 1570 | } |
---|
| 1571 | |
---|
[550] | 1572 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
---|
[450] | 1573 | |
---|
| 1574 | //////////////////////////////////////////////////////// |
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| 1575 | // Simulation |
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| 1576 | /////////////////////////////////////////////////////// |
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| 1577 | |
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| 1578 | sc_start(sc_core::sc_time(0, SC_NS)); |
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[584] | 1579 | |
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[450] | 1580 | signal_resetn = false; |
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[584] | 1581 | signal_irq_false = false; |
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| 1582 | |
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[450] | 1583 | // network boundaries signals |
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| 1584 | for (size_t x = 0; x < XMAX ; x++) |
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| 1585 | { |
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| 1586 | for (size_t y = 0; y < YMAX ; y++) |
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| 1587 | { |
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| 1588 | for (size_t a = 0; a < 4; a++) |
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| 1589 | { |
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[1002] | 1590 | signal_dspin_false_int_cmd_in[x][y][a].write = false; |
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| 1591 | signal_dspin_false_int_cmd_in[x][y][a].read = true; |
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| 1592 | signal_dspin_false_int_cmd_out[x][y][a].write = false; |
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| 1593 | signal_dspin_false_int_cmd_out[x][y][a].read = true; |
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[468] | 1594 | |
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[1002] | 1595 | signal_dspin_false_int_rsp_in[x][y][a].write = false; |
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| 1596 | signal_dspin_false_int_rsp_in[x][y][a].read = true; |
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| 1597 | signal_dspin_false_int_rsp_out[x][y][a].write = false; |
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| 1598 | signal_dspin_false_int_rsp_out[x][y][a].read = true; |
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[450] | 1599 | |
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[1002] | 1600 | signal_dspin_false_int_m2p_in[x][y][a].write = false; |
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| 1601 | signal_dspin_false_int_m2p_in[x][y][a].read = true; |
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| 1602 | signal_dspin_false_int_m2p_out[x][y][a].write = false; |
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| 1603 | signal_dspin_false_int_m2p_out[x][y][a].read = true; |
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| 1604 | |
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| 1605 | signal_dspin_false_int_p2m_in[x][y][a].write = false; |
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| 1606 | signal_dspin_false_int_p2m_in[x][y][a].read = true; |
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| 1607 | signal_dspin_false_int_p2m_out[x][y][a].write = false; |
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| 1608 | signal_dspin_false_int_p2m_out[x][y][a].read = true; |
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| 1609 | |
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| 1610 | signal_dspin_false_int_cla_in[x][y][a].write = false; |
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| 1611 | signal_dspin_false_int_cla_in[x][y][a].read = true; |
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| 1612 | signal_dspin_false_int_cla_out[x][y][a].write = false; |
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| 1613 | signal_dspin_false_int_cla_out[x][y][a].read = true; |
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| 1614 | |
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[450] | 1615 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
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| 1616 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
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| 1617 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
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| 1618 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
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| 1619 | |
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| 1620 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
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| 1621 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
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| 1622 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
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| 1623 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
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| 1624 | } |
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| 1625 | } |
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| 1626 | } |
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| 1627 | |
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[550] | 1628 | sc_start(sc_core::sc_time(1, SC_NS)); |
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| 1629 | signal_resetn = true; |
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[450] | 1630 | |
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[707] | 1631 | |
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| 1632 | // simulation loop |
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[693] | 1633 | struct timeval t1,t2; |
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| 1634 | gettimeofday(&t1, NULL); |
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[707] | 1635 | |
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[762] | 1636 | |
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| 1637 | for ( size_t n = 0; n < ncycles ; n += simul_period ) |
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[550] | 1638 | { |
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[693] | 1639 | // stats display |
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[714] | 1640 | if( (n % 1000000) == 0) |
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[693] | 1641 | { |
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| 1642 | gettimeofday(&t2, NULL); |
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| 1643 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
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| 1644 | (uint64_t) t1.tv_usec / 1000; |
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| 1645 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
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| 1646 | (uint64_t) t2.tv_usec / 1000; |
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[817] | 1647 | std::cerr << "### cycle = " << std::dec << n |
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[718] | 1648 | << " / frequency = " |
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| 1649 | << (double) 1000000 / (double) (ms2 - ms1) << "Khz" |
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[693] | 1650 | << std::endl; |
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| 1651 | |
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| 1652 | gettimeofday(&t1, NULL); |
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[1044] | 1653 | |
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| 1654 | // loop on all processors to display FROZEN stats |
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| 1655 | for ( size_t x = 0 ; x < XMAX ; x++ ) |
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| 1656 | { |
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| 1657 | for ( size_t y = 0 ; y < YMAX ; y++ ) |
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| 1658 | { |
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| 1659 | for ( size_t l = 0 ; l < NB_PROCS_MAX ; l++ ) |
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| 1660 | { |
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| 1661 | clusters[x][y]->proc[l]->print_frozen_stats(); |
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| 1662 | } |
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| 1663 | } |
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| 1664 | } |
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[693] | 1665 | } |
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| 1666 | |
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[607] | 1667 | // Monitor a specific address for one L1 cache |
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[959] | 1668 | // clusters[0][0]->proc[0]->cache_monitor(0x800080ULL); |
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[450] | 1669 | |
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[1002] | 1670 | // Monitor a specific address for one L2 cache (single word if second argument true) |
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[1050] | 1671 | // clusters[0][0]->memc->cache_monitor( 0x00007000ULL, false ); |
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[607] | 1672 | |
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| 1673 | // Monitor a specific address for one XRAM |
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[1050] | 1674 | // clusters[0][0]->xram->start_monitor( 0x00007000ULL , 64); |
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[607] | 1675 | |
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[764] | 1676 | if ( debug_ok and (n > debug_from) ) |
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[450] | 1677 | { |
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[550] | 1678 | std::cout << "****************** cycle " << std::dec << n ; |
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| 1679 | std::cout << " ************************************************" << std::endl; |
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[450] | 1680 | |
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[718] | 1681 | // trace proc[debug_proc_id] |
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[607] | 1682 | if ( debug_proc_id != 0xFFFFFFFF ) |
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[550] | 1683 | { |
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[802] | 1684 | size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; |
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| 1685 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
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[607] | 1686 | size_t x = cluster_xy >> 4; |
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| 1687 | size_t y = cluster_xy & 0xF; |
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[764] | 1688 | |
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| 1689 | clusters[x][y]->proc[l]->print_trace(0x1); |
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[550] | 1690 | std::ostringstream proc_signame; |
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| 1691 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
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| 1692 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
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[450] | 1693 | |
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[959] | 1694 | clusters[x][y]->xicu->print_trace(1); |
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| 1695 | std::ostringstream xicu_signame; |
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| 1696 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
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| 1697 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
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[584] | 1698 | |
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[972] | 1699 | // coprocessor in cluster(x,y) |
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[1050] | 1700 | // clusters[x][y]->mwmr->print_trace(); |
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| 1701 | // std::ostringstream mwmr_tgt_signame; |
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| 1702 | // mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; |
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| 1703 | // clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); |
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| 1704 | // std::ostringstream mwmr_ini_signame; |
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| 1705 | // mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; |
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| 1706 | // clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); |
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| 1707 | // if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); |
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| 1708 | // if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); |
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| 1709 | // if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); |
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[714] | 1710 | |
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[739] | 1711 | // local interrupts in cluster(x,y) |
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| 1712 | if( clusters[x][y]->signal_irq_memc.read() ) |
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[802] | 1713 | std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y |
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[739] | 1714 | << " ACTIVE" << std::endl; |
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| 1715 | |
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[972] | 1716 | if( clusters[x][y]->signal_irq_mwmr.read() ) |
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| 1717 | std::cout << "### IRQ_MWR_" << std::dec << x << "_" << y |
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| 1718 | << " ACTIVE" << std::endl; |
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[802] | 1719 | |
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[739] | 1720 | for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) |
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| 1721 | { |
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[1008] | 1722 | if( clusters[x][y]->signal_proc_it[c<<2].read() ) |
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[802] | 1723 | std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c |
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[739] | 1724 | << " ACTIVE" << std::endl; |
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| 1725 | } |
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[718] | 1726 | } |
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[450] | 1727 | |
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[718] | 1728 | // trace memc[debug_memc_id] |
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[607] | 1729 | if ( debug_memc_id != 0xFFFFFFFF ) |
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[550] | 1730 | { |
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[607] | 1731 | size_t x = debug_memc_id >> 4; |
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| 1732 | size_t y = debug_memc_id & 0xF; |
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[718] | 1733 | |
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[550] | 1734 | clusters[x][y]->memc->print_trace(0); |
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| 1735 | std::ostringstream smemc_tgt; |
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| 1736 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
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| 1737 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
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| 1738 | std::ostringstream smemc_ini; |
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| 1739 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
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| 1740 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
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[707] | 1741 | |
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[550] | 1742 | clusters[x][y]->xram->print_trace(); |
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| 1743 | std::ostringstream sxram_tgt; |
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| 1744 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
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| 1745 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
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[450] | 1746 | |
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[1030] | 1747 | // clusters[x][y]->ram_router_cmd->print_trace(); |
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| 1748 | // clusters[x][y]->ram_router_rsp->print_trace(); |
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[1050] | 1749 | |
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| 1750 | // clusters[x][y]->ram_xbar_cmd->print_trace(); |
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| 1751 | // clusters[x][y]->ram_xbar_rsp->print_trace(); |
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[707] | 1752 | } |
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[718] | 1753 | |
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| 1754 | // trace iob, iox and external peripherals |
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[550] | 1755 | if ( debug_iob ) |
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| 1756 | { |
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[914] | 1757 | // clusters[0][0]->iob->print_trace(); |
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[718] | 1758 | // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
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| 1759 | // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
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| 1760 | // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
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[730] | 1761 | // signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
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| 1762 | // signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
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[450] | 1763 | |
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[710] | 1764 | // brom->print_trace(); |
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[914] | 1765 | // signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); |
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[450] | 1766 | |
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[550] | 1767 | // mtty->print_trace(); |
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[914] | 1768 | // signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); |
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[450] | 1769 | |
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[1018] | 1770 | // disk->print_trace(); |
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| 1771 | // signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); |
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| 1772 | // signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); |
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[450] | 1773 | |
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[1002] | 1774 | #if ( USE_IOC_SDC ) |
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[1018] | 1775 | // card->print_trace(); |
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[1002] | 1776 | #endif |
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[714] | 1777 | |
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[1050] | 1778 | mnic->print_trace( 0 ); |
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| 1779 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
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| 1780 | signal_vci_ini_mnic.print_trace("[SIG]MNIC_INI"); |
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[1002] | 1781 | |
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[1050] | 1782 | // fbuf->print_trace(); |
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| 1783 | // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); |
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[498] | 1784 | |
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[874] | 1785 | // iopi->print_trace(); |
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| 1786 | // signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
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| 1787 | // signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
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[965] | 1788 | |
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[874] | 1789 | // iox_network->print_trace(); |
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[450] | 1790 | |
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[550] | 1791 | // interrupts |
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[1002] | 1792 | if ( signal_irq_disk.read() ) |
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| 1793 | std::cout << "### IRQ_DISK ACTIVE" << std::endl; |
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| 1794 | |
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| 1795 | if ( signal_irq_mtty_rx[0].read() ) |
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| 1796 | std::cout << "### IRQ_MTTY_RX[0] ACTIVE" << std::endl; |
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| 1797 | |
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| 1798 | if ( signal_irq_mnic_rx[0].read() ) |
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| 1799 | std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; |
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| 1800 | |
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| 1801 | if ( signal_irq_mnic_tx[0].read() ) |
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| 1802 | std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; |
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[550] | 1803 | } |
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| 1804 | } |
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[450] | 1805 | |
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[762] | 1806 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
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[550] | 1807 | } |
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| 1808 | return EXIT_SUCCESS; |
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[450] | 1809 | } |
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| 1810 | |
---|
| 1811 | int sc_main (int argc, char *argv[]) |
---|
| 1812 | { |
---|
| 1813 | try { |
---|
| 1814 | return _main(argc, argv); |
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| 1815 | } catch (std::exception &e) { |
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| 1816 | std::cout << e.what() << std::endl; |
---|
| 1817 | } catch (...) { |
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| 1818 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1819 | throw; |
---|
| 1820 | } |
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| 1821 | return 1; |
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| 1822 | } |
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| 1823 | |
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| 1824 | |
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| 1825 | // Local Variables: |
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| 1826 | // tab-width: 3 |
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| 1827 | // c-basic-offset: 3 |
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| 1828 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 1829 | // indent-tabs-mode: nil |
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| 1830 | // End: |
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| 1831 | |
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| 1832 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 1833 | |
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| 1834 | |
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| 1835 | |
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