Context Navigation

source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 714

Last change on this file since 714 was 714, checked in by alain, 10 years ago
changing genmap_py to arch.py
File size: 31.2 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	namespace soclib { namespace caba {
18
19	//////////////////////////////////////////////////////////////////////////
20	// Constructor
21	//////////////////////////////////////////////////////////////////////////
22	template<typename vci_param_int,
23	typename vci_param_ext,
24	size_t dspin_int_cmd_width,
25	size_t dspin_int_rsp_width,
26	size_t dspin_ram_cmd_width,
27	size_t dspin_ram_rsp_width>
28	TsarIobCluster<vci_param_int,
29	vci_param_ext,
30	dspin_int_cmd_width,
31	dspin_int_rsp_width,
32	dspin_ram_cmd_width,
33	dspin_ram_rsp_width>::TsarIobCluster(
34	//////////////////////////////////////////////////////////////////////////
35	sc_module_name insname,
36	size_t nb_procs,
37	size_t nb_dmas,
38	size_t x_id,
39	size_t y_id,
40	size_t xmax,
41	size_t ymax,
42
43	const soclib::common::MappingTable &mt_int,
44	const soclib::common::MappingTable &mt_ram,
45	const soclib::common::MappingTable &mt_iox,
46
47	size_t x_width,
48	size_t y_width,
49	size_t l_width,
50
51	size_t memc_int_tgtid, // local index
52	size_t xicu_int_tgtid, // local index
53	size_t mdma_int_tgtid, // local index
54	size_t iobx_int_tgtid, // local index
55
56	size_t proc_int_srcid, // local index
57	size_t mdma_int_srcid, // local index
58	size_t iobx_int_srcid, // local index
59
60	size_t xram_ram_tgtid, // local index
61
62	size_t memc_ram_srcid, // local index
63	size_t iobx_ram_srcid, // local index
64
65	size_t memc_ways,
66	size_t memc_sets,
67	size_t l1_i_ways,
68	size_t l1_i_sets,
69	size_t l1_d_ways,
70	size_t l1_d_sets,
71	size_t xram_latency,
72	size_t xcu_nb_inputs,
73
74	const Loader &loader,
75
76	uint32_t frozen_cycles,
77	uint32_t debug_start_cycle,
78	bool memc_debug_ok,
79	bool proc_debug_ok,
80	bool iob_debug_ok )
81	: soclib::caba::BaseModule(insname),
82	p_clk("clk"),
83	p_resetn("resetn")
84	{
85	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
86
87	size_t cluster_id = (x_id<<4) + y_id;
88
89	size_t cluster_iob0 = 0; // South-West cluster
90	size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster
91
92	// Vectors of DSPIN ports for inter-cluster communications
93	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
94	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
95	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
96	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
97
98	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
99	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
100	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
101	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
102
103	// ports in cluster_iob0 and cluster_iob1 only
104	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
105	{
106	// VCI ports from IOB to IOX network
107	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
108	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
109
110	// DSPIN ports from IOB to RAM network
111	p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
112	p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
113	}
114
115	/////////////////////////////////////////////////////////////////////////////
116	// Hardware components
117	/////////////////////////////////////////////////////////////////////////////
118
119	//////////// PROCS
120	for (size_t p = 0; p < nb_procs; p++)
121	{
122	std::ostringstream s_proc;
123	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
124	proc[p] = new VciCcVCacheWrapper<vci_param_int,
125	dspin_int_cmd_width,
126	dspin_int_rsp_width,
127	GdbServer<Mips32ElIss> >(
128	s_proc.str().c_str(),
129	cluster_id*nb_procs + p, // GLOBAL PROC_ID
130	mt_int, // Mapping Table INT network
131	IntTab(cluster_id,p), // SRCID
132	(cluster_id << l_width) + p, // CC_GLOBAL_ID
133	8, // ITLB ways
134	8, // ITLB sets
135	8, // DTLB ways
136	8, // DTLB sets
137	l1_i_ways,l1_i_sets,16, // ICACHE size
138	l1_d_ways,l1_d_sets,16, // DCACHE size
139	4, // WBUF nlines
140	4, // WBUF nwords
141	x_width,
142	y_width,
143	frozen_cycles, // max frozen cycles
144	debug_start_cycle,
145	proc_debug_ok);
146	}
147
148	/////////// MEMC
149	std::ostringstream s_memc;
150	s_memc << "memc_" << x_id << "_" << y_id;
151	memc = new VciMemCache<vci_param_int,
152	vci_param_ext,
153	dspin_int_rsp_width,
154	dspin_int_cmd_width>(
155	s_memc.str().c_str(),
156	mt_int, // Mapping Table INT network
157	mt_ram, // Mapping Table RAM network
158	IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network
159	IntTab(cluster_id, memc_int_tgtid), // TGTID INT network
160	x_width, // number of bits for x coordinate
161	y_width, // number of bits for y coordinate
162	memc_ways, memc_sets, 16, // CACHE SIZE
163	3, // MAX NUMBER OF COPIES
164	4096, // HEAP SIZE
165	8, // TRANSACTION TABLE DEPTH
166	8, // UPDATE TABLE DEPTH
167	8, // INVALIDATE TABLE DEPTH
168	debug_start_cycle,
169	memc_debug_ok );
170
171	std::ostringstream s_wi_memc;
172	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
173	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
174	dspin_ram_cmd_width,
175	dspin_ram_rsp_width>(
176	s_wi_memc.str().c_str(),
177	x_width + y_width + l_width);
178
179	/////////// XICU
180	std::ostringstream s_xicu;
181	s_xicu << "xicu_" << x_id << "_" << y_id;
182	xicu = new VciXicu<vci_param_int>(
183	s_xicu.str().c_str(),
184	mt_int, // mapping table INT network
185	IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space
186	xcu_nb_inputs, // number of timer IRQs
187	xcu_nb_inputs, // number of hard IRQs
188	xcu_nb_inputs, // number of soft IRQs
189	16); // number of output IRQs
190
191	//////////// MDMA
192	std::ostringstream s_mdma;
193	s_mdma << "mdma_" << x_id << "_" << y_id;
194	mdma = new VciMultiDma<vci_param_int>(
195	s_mdma.str().c_str(),
196	mt_int,
197	IntTab(cluster_id, nb_procs), // SRCID
198	IntTab(cluster_id, mdma_int_tgtid), // TGTID
199	64, // burst size
200	nb_dmas); // number of IRQs
201
202	/////////// Direct LOCAL_XBAR(S)
203	size_t nb_direct_initiators = nb_procs + 1;
204	size_t nb_direct_targets = 3;
205	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
206	{
207	nb_direct_initiators = nb_procs + 2;
208	nb_direct_targets = 4;
209	}
210
211	std::ostringstream s_int_xbar_d;
212	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
213	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
214	s_int_xbar_d.str().c_str(),
215	mt_int, // mapping table
216	cluster_id, // cluster id
217	nb_direct_initiators, // number of local initiators
218	nb_direct_targets, // number of local targets
219	0 ); // default target
220
221	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
222	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
223	<< x_id << "_" << y_id;
224	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
225	dspin_int_cmd_width,
226	dspin_int_rsp_width>(
227	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
228	x_width + y_width + l_width);
229
230	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
231	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
232	<< x_id << "_" << y_id;
233	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
234	dspin_int_cmd_width,
235	dspin_int_rsp_width>(
236	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
237	x_width + y_width + l_width);
238
239	//////////// Coherence LOCAL_XBAR(S)
240	std::ostringstream s_int_xbar_m2p_c;
241	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
242	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
243	s_int_xbar_m2p_c.str().c_str(),
244	mt_int, // mapping table
245	x_id, y_id, // cluster coordinates
246	x_width, y_width, l_width, // several dests
247	1, // number of local sources
248	nb_procs, // number of local dests
249	2, 2, // fifo depths
250	true, // pseudo CMD
251	false, // no routing table
252	true ); // broacast
253
254	std::ostringstream s_int_xbar_p2m_c;
255	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
256	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
257	s_int_xbar_p2m_c.str().c_str(),
258	mt_int, // mapping table
259	x_id, y_id, // cluster coordinates
260	x_width, y_width, 0, // only one dest
261	nb_procs, // number of local sources
262	1, // number of local dests
263	2, 2, // fifo depths
264	false, // pseudo RSP
265	false, // no routing table
266	false ); // no broacast
267
268	std::ostringstream s_int_xbar_clack_c;
269	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
270	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
271	s_int_xbar_clack_c.str().c_str(),
272	mt_int, // mapping table
273	x_id, y_id, // cluster coordinates
274	x_width, y_width, l_width,
275	1, // number of local sources
276	nb_procs, // number of local targets
277	1, 1, // fifo depths
278	true, // CMD
279	false, // no routing table
280	false); // broadcast
281
282	////////////// INT ROUTER(S)
283	std::ostringstream s_int_router_cmd;
284	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
285	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
286	s_int_router_cmd.str().c_str(),
287	x_id,y_id, // coordinate in the mesh
288	x_width, y_width, // x & y fields width
289	3, // nb virtual channels
290	4,4); // input & output fifo depths
291
292	std::ostringstream s_int_router_rsp;
293	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
294	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
295	s_int_router_rsp.str().c_str(),
296	x_id,y_id, // router coordinates in mesh
297	x_width, y_width, // x & y fields width
298	2, // nb virtual channels
299	4,4); // input & output fifo depths
300
301	////////////// XRAM
302	std::ostringstream s_xram;
303	s_xram << "xram_" << x_id << "_" << y_id;
304	xram = new VciSimpleRam<vci_param_ext>(
305	s_xram.str().c_str(),
306	IntTab(cluster_id, xram_ram_tgtid ),
307	mt_ram,
308	loader,
309	xram_latency);
310
311	std::ostringstream s_wt_xram;
312	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
313	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
314	dspin_ram_cmd_width,
315	dspin_ram_rsp_width>(
316	s_wt_xram.str().c_str(),
317	x_width + y_width + l_width);
318
319	///////////// RAM ROUTER(S)
320	std::ostringstream s_ram_router_cmd;
321	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
322	size_t is_iob0 = (x_id == 0) and (y_id == 0);
323	size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1));
324	ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
325	s_ram_router_cmd.str().c_str(),
326	x_id, y_id, // router coordinates in mesh
327	x_width, // x field width in first flit
328	y_width, // y field width in first flit
329	4, 4, // input & output fifo depths
330	is_iob0, // cluster contains IOB0
331	is_iob1, // cluster contains IOB1
332	false, // not a response router
333	l_width); // local field width in first flit
334
335	std::ostringstream s_ram_router_rsp;
336	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
337	ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>(
338	s_ram_router_rsp.str().c_str(),
339	x_id, y_id, // coordinates in mesh
340	x_width, // x field width in first flit
341	y_width, // y field width in first flit
342	4, 4, // input & output fifo depths
343	is_iob0, // cluster contains IOB0
344	is_iob1, // cluster contains IOB1
345	true, // response router
346	l_width); // local field width in first flit
347
348
349	////////////////////// I/O CLUSTER ONLY ///////////////////////
350	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
351	{
352	/////////// IO_BRIDGE
353	size_t iox_local_id;
354	size_t global_id;
355	if ( cluster_id == cluster_iob0 )
356	{
357	iox_local_id = 0;
358	global_id = cluster_iob0;
359	}
360	else
361	{
362	iox_local_id = 1;
363	global_id = cluster_iob1;
364	}
365
366	std::ostringstream s_iob;
367	s_iob << "iob_" << x_id << "_" << y_id;
368	iob = new VciIoBridge<vci_param_int,
369	vci_param_ext>(
370	s_iob.str().c_str(),
371	mt_ram, // EXT network maptab
372	mt_int, // INT network maptab
373	mt_iox, // IOX network maptab
374	IntTab( global_id, iobx_int_tgtid ), // INT TGTID
375	IntTab( global_id, iobx_int_srcid ), // INT SRCID
376	IntTab( global_id, iox_local_id ), // IOX TGTID
377	16, // cache line words
378	8, // IOTLB ways
379	8, // IOTLB sets
380	debug_start_cycle,
381	iob_debug_ok );
382
383	std::ostringstream s_iob_ram_wi;
384	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
385	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
386	dspin_ram_cmd_width,
387	dspin_ram_rsp_width>(
388	s_iob_ram_wi.str().c_str(),
389	x_width + y_width + l_width);
390	} // end if IO
391
392	////////////////////////////////////
393	// Connections are defined here
394	////////////////////////////////////
395
396	// on coherence network : local srcid[proc] in [0...nb_procs-1]
397	// : local srcid[memc] = nb_procs
398	// In cluster_iob0, 32 HWI interrupts from external peripherals
399	// are connected to the XICU ports p_hwi[0:31]
400	// In other clusters, no HWI interrupts are connected to XICU
401
402	//////////////////////// internal CMD & RSP routers
403	int_router_cmd->p_clk (this->p_clk);
404	int_router_cmd->p_resetn (this->p_resetn);
405	int_router_rsp->p_clk (this->p_clk);
406	int_router_rsp->p_resetn (this->p_resetn);
407
408	for (int i = 0; i < 4; i++)
409	{
410	for(int k = 0; k < 3; k++)
411	{
412	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
413	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
414	}
415
416	for(int k = 0; k < 2; k++)
417	{
418	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
419	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
420	}
421	}
422
423	// local ports
424	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
425	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
426	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
427	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
428	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
429	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
430
431	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
432	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
433	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
434	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
435
436	///////////////////// CMD DSPIN local crossbar direct
437	int_xbar_d->p_clk (this->p_clk);
438	int_xbar_d->p_resetn (this->p_resetn);
439	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
440	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
441
442	int_xbar_d->p_to_target[memc_int_tgtid] (signal_int_vci_tgt_memc);
443	int_xbar_d->p_to_target[xicu_int_tgtid] (signal_int_vci_tgt_xicu);
444	int_xbar_d->p_to_target[mdma_int_tgtid] (signal_int_vci_tgt_mdma);
445	int_xbar_d->p_to_initiator[mdma_int_srcid] (signal_int_vci_ini_mdma);
446	for (size_t p = 0; p < nb_procs; p++)
447	int_xbar_d->p_to_initiator[proc_int_srcid + p] (signal_int_vci_ini_proc[p]);
448
449	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
450	{
451	int_xbar_d->p_to_target[iobx_int_tgtid] (signal_int_vci_tgt_iobx);
452	int_xbar_d->p_to_initiator[iobx_int_srcid] (signal_int_vci_ini_iobx);
453	}
454
455	int_wi_gate_d->p_clk (this->p_clk);
456	int_wi_gate_d->p_resetn (this->p_resetn);
457	int_wi_gate_d->p_vci (signal_int_vci_l2g);
458	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
459	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
460
461	int_wt_gate_d->p_clk (this->p_clk);
462	int_wt_gate_d->p_resetn (this->p_resetn);
463	int_wt_gate_d->p_vci (signal_int_vci_g2l);
464	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
465	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
466
467	////////////////////// M2P DSPIN local crossbar coherence
468	int_xbar_m2p_c->p_clk (this->p_clk);
469	int_xbar_m2p_c->p_resetn (this->p_resetn);
470	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
471	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
472	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
473	for (size_t p = 0; p < nb_procs; p++)
474	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
475
476	////////////////////////// P2M DSPIN local crossbar coherence
477	int_xbar_p2m_c->p_clk (this->p_clk);
478	int_xbar_p2m_c->p_resetn (this->p_resetn);
479	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
480	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
481	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
482	for (size_t p = 0; p < nb_procs; p++)
483	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
484
485	////////////////////// CLACK DSPIN local crossbar coherence
486	int_xbar_clack_c->p_clk (this->p_clk);
487	int_xbar_clack_c->p_resetn (this->p_resetn);
488	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
489	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
490	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
491	for (size_t p = 0; p < nb_procs; p++)
492	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
493
494	//////////////////////////////////// Processors
495	for (size_t p = 0; p < nb_procs; p++)
496	{
497	proc[p]->p_clk (this->p_clk);
498	proc[p]->p_resetn (this->p_resetn);
499	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
500	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
501	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
502	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
503
504	for ( size_t j = 0 ; j < 6 ; j++)
505	{
506	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
507	else proc[p]->p_irq[j] (signal_false);
508	}
509	}
510
511	///////////////////////////////////// XICU
512	xicu->p_clk (this->p_clk);
513	xicu->p_resetn (this->p_resetn);
514	xicu->p_vci (signal_int_vci_tgt_xicu);
515	for ( size_t i=0 ; i < 16 ; i++)
516	{
517	xicu->p_irq[i] (signal_proc_it[i]);
518	}
519	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
520	{
521	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
522	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
523	else xicu->p_hwi[i] (signal_false);
524	}
525
526	///////////////////////////////////// MEMC
527	memc->p_clk (this->p_clk);
528	memc->p_resetn (this->p_resetn);
529	memc->p_vci_ixr (signal_ram_vci_ini_memc);
530	memc->p_vci_tgt (signal_int_vci_tgt_memc);
531	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
532	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
533	memc->p_dspin_clack (signal_int_dspin_clack_memc);
534	memc->p_irq (signal_irq_memc);
535
536	// wrapper to RAM network
537	memc_ram_wi->p_clk (this->p_clk);
538	memc_ram_wi->p_resetn (this->p_resetn);
539	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
540	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
541	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
542
543	//////////////////////////////////// XRAM
544	xram->p_clk (this->p_clk);
545	xram->p_resetn (this->p_resetn);
546	xram->p_vci (signal_ram_vci_tgt_xram);
547
548	// wrapper to RAM network
549	xram_ram_wt->p_clk (this->p_clk);
550	xram_ram_wt->p_resetn (this->p_resetn);
551	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
552	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
553	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
554
555	/////////////////////////////////// MDMA
556	mdma->p_clk (this->p_clk);
557	mdma->p_resetn (this->p_resetn);
558	mdma->p_vci_target (signal_int_vci_tgt_mdma);
559	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
560	for (size_t i=0 ; i<nb_dmas ; i++)
561	mdma->p_irq[i] (signal_irq_mdma[i]);
562
563	//////////////////////////// RAM network CMD & RSP routers
564	ram_router_cmd->p_clk (this->p_clk);
565	ram_router_cmd->p_resetn (this->p_resetn);
566	ram_router_rsp->p_clk (this->p_clk);
567	ram_router_rsp->p_resetn (this->p_resetn);
568	for( size_t n=0 ; n<4 ; n++)
569	{
570	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
571	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
572	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
573	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
574	}
575	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
576	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
577	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
578	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
579
580	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
581	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
582	{
583	// IO bridge
584	iob->p_clk (this->p_clk);
585	iob->p_resetn (this->p_resetn);
586	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
587	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
588	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
589	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
590	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
591
592	// initiator wrapper to RAM network
593	iob_ram_wi->p_clk (this->p_clk);
594	iob_ram_wi->p_resetn (this->p_resetn);
595	iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out));
596	iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in));
597	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
598	}
599
600	} // end constructor
601
602	}}
603
604
605	// Local Variables:
606	// tab-width: 3
607	// c-basic-offset: 3
608	// c-file-offsets:((innamespace . 0)(inline-open . 0))
609	// indent-tabs-mode: nil
610	// End:
611
612	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
613
614
615

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0