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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 707

Last change on this file since 707 was 707, checked in by alain, 10 years ago
Bug Fix: in the special case of one single cluster there is only one IOB component toa access IOX network (IOB1 does not exist).
File size: 31.2 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	namespace soclib { namespace caba {
18
19	//////////////////////////////////////////////////////////////////////////
20	// Constructor
21	//////////////////////////////////////////////////////////////////////////
22	template<typename vci_param_int,
23	typename vci_param_ext,
24	size_t dspin_int_cmd_width,
25	size_t dspin_int_rsp_width,
26	size_t dspin_ram_cmd_width,
27	size_t dspin_ram_rsp_width>
28	TsarIobCluster<vci_param_int,
29	vci_param_ext,
30	dspin_int_cmd_width,
31	dspin_int_rsp_width,
32	dspin_ram_cmd_width,
33	dspin_ram_rsp_width>::TsarIobCluster(
34	//////////////////////////////////////////////////////////////////////////
35	sc_module_name insname,
36	size_t nb_procs,
37	size_t nb_dmas,
38	size_t x_id,
39	size_t y_id,
40	size_t xmax,
41	size_t ymax,
42
43	const soclib::common::MappingTable &mt_int,
44	const soclib::common::MappingTable &mt_ram,
45	const soclib::common::MappingTable &mt_iox,
46
47	size_t x_width,
48	size_t y_width,
49	size_t l_width,
50
51	size_t memc_int_tgtid, // local index
52	size_t xicu_int_tgtid, // local index
53	size_t mdma_int_tgtid, // local index
54	size_t iobx_int_tgtid, // local index
55
56	size_t proc_int_srcid, // local index
57	size_t mdma_int_srcid, // local index
58	size_t iobx_int_srcid, // local index
59
60	size_t xram_ram_tgtid, // local index
61
62	size_t memc_ram_srcid, // local index
63	size_t iobx_ram_srcid, // local index
64
65	size_t memc_ways,
66	size_t memc_sets,
67	size_t l1_i_ways,
68	size_t l1_i_sets,
69	size_t l1_d_ways,
70	size_t l1_d_sets,
71	size_t xram_latency,
72
73	const Loader &loader,
74
75	uint32_t frozen_cycles,
76	uint32_t debug_start_cycle,
77	bool memc_debug_ok,
78	bool proc_debug_ok,
79	bool iob_debug_ok )
80	: soclib::caba::BaseModule(insname),
81	p_clk("clk"),
82	p_resetn("resetn")
83	{
84	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
85
86	size_t cluster_id = (x_id<<4) + y_id;
87
88	size_t cluster_iob0 = 0; // South-West cluster
89	size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster
90
91	// Vectors of DSPIN ports for inter-cluster communications
92	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
93	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
94	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
95	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
96
97	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
98	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
99	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
100	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
101
102	// ports in cluster_iob0 and cluster_iob1 only
103	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
104	{
105	// VCI ports from IOB to IOX network
106	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
107	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
108
109	// DSPIN ports from IOB to RAM network
110	p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
111	p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
112	}
113
114	/////////////////////////////////////////////////////////////////////////////
115	// Hardware components
116	/////////////////////////////////////////////////////////////////////////////
117
118	//////////// PROCS
119	for (size_t p = 0; p < nb_procs; p++)
120	{
121	std::ostringstream s_proc;
122	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
123	proc[p] = new VciCcVCacheWrapper<vci_param_int,
124	dspin_int_cmd_width,
125	dspin_int_rsp_width,
126	GdbServer<Mips32ElIss> >(
127	s_proc.str().c_str(),
128	cluster_id*nb_procs + p, // GLOBAL PROC_ID
129	mt_int, // Mapping Table INT network
130	IntTab(cluster_id,p), // SRCID
131	(cluster_id << l_width) + p, // CC_GLOBAL_ID
132	8, // ITLB ways
133	8, // ITLB sets
134	8, // DTLB ways
135	8, // DTLB sets
136	l1_i_ways,l1_i_sets,16, // ICACHE size
137	l1_d_ways,l1_d_sets,16, // DCACHE size
138	4, // WBUF nlines
139	4, // WBUF nwords
140	x_width,
141	y_width,
142	frozen_cycles, // max frozen cycles
143	debug_start_cycle,
144	proc_debug_ok);
145	}
146
147	/////////// MEMC
148	std::ostringstream s_memc;
149	s_memc << "memc_" << x_id << "_" << y_id;
150	memc = new VciMemCache<vci_param_int,
151	vci_param_ext,
152	dspin_int_rsp_width,
153	dspin_int_cmd_width>(
154	s_memc.str().c_str(),
155	mt_int, // Mapping Table INT network
156	mt_ram, // Mapping Table RAM network
157	IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network
158	IntTab(cluster_id, memc_int_tgtid), // TGTID INT network
159	x_width, // number of bits for x coordinate
160	y_width, // number of bits for y coordinate
161	memc_ways, memc_sets, 16, // CACHE SIZE
162	3, // MAX NUMBER OF COPIES
163	4096, // HEAP SIZE
164	8, // TRANSACTION TABLE DEPTH
165	8, // UPDATE TABLE DEPTH
166	8, // INVALIDATE TABLE DEPTH
167	debug_start_cycle,
168	memc_debug_ok );
169
170	std::ostringstream s_wi_memc;
171	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
172	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
173	dspin_ram_cmd_width,
174	dspin_ram_rsp_width>(
175	s_wi_memc.str().c_str(),
176	x_width + y_width + l_width);
177
178	/////////// XICU
179	std::ostringstream s_xicu;
180	s_xicu << "xicu_" << x_id << "_" << y_id;
181	xicu = new VciXicu<vci_param_int>(
182	s_xicu.str().c_str(),
183	mt_int, // mapping table INT network
184	IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space
185	32, // number of timer IRQs
186	32, // number of hard IRQs
187	32, // number of soft IRQs
188	32); // number of output IRQs
189
190	//////////// MDMA
191	std::ostringstream s_mdma;
192	s_mdma << "mdma_" << x_id << "_" << y_id;
193	mdma = new VciMultiDma<vci_param_int>(
194	s_mdma.str().c_str(),
195	mt_int,
196	IntTab(cluster_id, nb_procs), // SRCID
197	IntTab(cluster_id, mdma_int_tgtid), // TGTID
198	64, // burst size
199	nb_dmas); // number of IRQs
200
201	/////////// Direct LOCAL_XBAR(S)
202	size_t nb_direct_initiators = nb_procs + 1;
203	size_t nb_direct_targets = 3;
204	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
205	{
206	nb_direct_initiators = nb_procs + 2;
207	nb_direct_targets = 4;
208	}
209
210	std::ostringstream s_int_xbar_d;
211	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
212	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
213	s_int_xbar_d.str().c_str(),
214	mt_int, // mapping table
215	cluster_id, // cluster id
216	nb_direct_initiators, // number of local initiators
217	nb_direct_targets, // number of local targets
218	0 ); // default target
219
220	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
221	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
222	<< x_id << "_" << y_id;
223	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
224	dspin_int_cmd_width,
225	dspin_int_rsp_width>(
226	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
227	x_width + y_width + l_width);
228
229	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
230	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
231	<< x_id << "_" << y_id;
232	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
233	dspin_int_cmd_width,
234	dspin_int_rsp_width>(
235	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
236	x_width + y_width + l_width);
237
238	//////////// Coherence LOCAL_XBAR(S)
239	std::ostringstream s_int_xbar_m2p_c;
240	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
241	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
242	s_int_xbar_m2p_c.str().c_str(),
243	mt_int, // mapping table
244	x_id, y_id, // cluster coordinates
245	x_width, y_width, l_width, // several dests
246	1, // number of local sources
247	nb_procs, // number of local dests
248	2, 2, // fifo depths
249	true, // pseudo CMD
250	false, // no routing table
251	true ); // broacast
252
253	std::ostringstream s_int_xbar_p2m_c;
254	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
255	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
256	s_int_xbar_p2m_c.str().c_str(),
257	mt_int, // mapping table
258	x_id, y_id, // cluster coordinates
259	x_width, y_width, 0, // only one dest
260	nb_procs, // number of local sources
261	1, // number of local dests
262	2, 2, // fifo depths
263	false, // pseudo RSP
264	false, // no routing table
265	false ); // no broacast
266
267	std::ostringstream s_int_xbar_clack_c;
268	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
269	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
270	s_int_xbar_clack_c.str().c_str(),
271	mt_int, // mapping table
272	x_id, y_id, // cluster coordinates
273	x_width, y_width, l_width,
274	1, // number of local sources
275	nb_procs, // number of local targets
276	1, 1, // fifo depths
277	true, // CMD
278	false, // no routing table
279	false); // broadcast
280
281	////////////// INT ROUTER(S)
282	std::ostringstream s_int_router_cmd;
283	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
284	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
285	s_int_router_cmd.str().c_str(),
286	x_id,y_id, // coordinate in the mesh
287	x_width, y_width, // x & y fields width
288	3, // nb virtual channels
289	4,4); // input & output fifo depths
290
291	std::ostringstream s_int_router_rsp;
292	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
293	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
294	s_int_router_rsp.str().c_str(),
295	x_id,y_id, // router coordinates in mesh
296	x_width, y_width, // x & y fields width
297	2, // nb virtual channels
298	4,4); // input & output fifo depths
299
300	////////////// XRAM
301	std::ostringstream s_xram;
302	s_xram << "xram_" << x_id << "_" << y_id;
303	xram = new VciSimpleRam<vci_param_ext>(
304	s_xram.str().c_str(),
305	IntTab(cluster_id, xram_ram_tgtid ),
306	mt_ram,
307	loader,
308	xram_latency);
309
310	std::ostringstream s_wt_xram;
311	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
312	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
313	dspin_ram_cmd_width,
314	dspin_ram_rsp_width>(
315	s_wt_xram.str().c_str(),
316	x_width + y_width + l_width);
317
318	///////////// RAM ROUTER(S)
319	std::ostringstream s_ram_router_cmd;
320	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
321	size_t is_iob0 = (x_id == 0) and (y_id == 0);
322	size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1));
323	ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
324	s_ram_router_cmd.str().c_str(),
325	x_id, y_id, // router coordinates in mesh
326	x_width, // x field width in first flit
327	y_width, // y field width in first flit
328	4, 4, // input & output fifo depths
329	is_iob0, // cluster contains IOB0
330	is_iob1, // cluster contains IOB1
331	false, // not a response router
332	l_width); // local field width in first flit
333
334	std::ostringstream s_ram_router_rsp;
335	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
336	ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>(
337	s_ram_router_rsp.str().c_str(),
338	x_id, y_id, // coordinates in mesh
339	x_width, // x field width in first flit
340	y_width, // y field width in first flit
341	4, 4, // input & output fifo depths
342	is_iob0, // cluster contains IOB0
343	is_iob1, // cluster contains IOB1
344	true, // response router
345	l_width); // local field width in first flit
346
347
348	////////////////////// I/O CLUSTER ONLY ///////////////////////
349	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
350	{
351	/////////// IO_BRIDGE
352	size_t iox_local_id;
353	size_t global_id;
354	if ( cluster_id == cluster_iob0 )
355	{
356	iox_local_id = 0;
357	global_id = cluster_iob0;
358	}
359	else
360	{
361	iox_local_id = 1;
362	global_id = cluster_iob1;
363	}
364
365	std::ostringstream s_iob;
366	s_iob << "iob_" << x_id << "_" << y_id;
367	iob = new VciIoBridge<vci_param_int,
368	vci_param_ext>(
369	s_iob.str().c_str(),
370	mt_ram, // EXT network maptab
371	mt_int, // INT network maptab
372	mt_iox, // IOX network maptab
373	IntTab( global_id, iobx_int_tgtid ), // INT TGTID
374	IntTab( global_id, iobx_int_srcid ), // INT SRCID
375	IntTab( global_id, iox_local_id ), // IOX TGTID
376	16, // cache line words
377	8, // IOTLB ways
378	8, // IOTLB sets
379	debug_start_cycle,
380	iob_debug_ok );
381
382	std::ostringstream s_iob_ram_wi;
383	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
384	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
385	dspin_ram_cmd_width,
386	dspin_ram_rsp_width>(
387	s_iob_ram_wi.str().c_str(),
388	x_width + y_width + l_width);
389	} // end if IO
390
391	////////////////////////////////////
392	// Connections are defined here
393	////////////////////////////////////
394
395	// on coherence network : local srcid[proc] in [0...nb_procs-1]
396	// : local srcid[memc] = nb_procs
397	// In cluster_iob0, 32 HWI interrupts from external peripherals
398	// are connected to the XICU ports p_hwi[0:31]
399	// In other clusters, no HWI interrupts are connected to XICU
400
401	//////////////////////// internal CMD & RSP routers
402	int_router_cmd->p_clk (this->p_clk);
403	int_router_cmd->p_resetn (this->p_resetn);
404	int_router_rsp->p_clk (this->p_clk);
405	int_router_rsp->p_resetn (this->p_resetn);
406
407	for (int i = 0; i < 4; i++)
408	{
409	for(int k = 0; k < 3; k++)
410	{
411	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
412	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
413	}
414
415	for(int k = 0; k < 2; k++)
416	{
417	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
418	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
419	}
420	}
421
422	// local ports
423	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
424	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
425	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
426	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
427	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
428	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
429
430	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
431	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
432	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
433	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
434
435	///////////////////// CMD DSPIN local crossbar direct
436	int_xbar_d->p_clk (this->p_clk);
437	int_xbar_d->p_resetn (this->p_resetn);
438	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
439	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
440
441	int_xbar_d->p_to_target[memc_int_tgtid] (signal_int_vci_tgt_memc);
442	int_xbar_d->p_to_target[xicu_int_tgtid] (signal_int_vci_tgt_xicu);
443	int_xbar_d->p_to_target[mdma_int_tgtid] (signal_int_vci_tgt_mdma);
444	int_xbar_d->p_to_initiator[mdma_int_srcid] (signal_int_vci_ini_mdma);
445	for (size_t p = 0; p < nb_procs; p++)
446	int_xbar_d->p_to_initiator[proc_int_srcid + p] (signal_int_vci_ini_proc[p]);
447
448	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
449	{
450	int_xbar_d->p_to_target[iobx_int_tgtid] (signal_int_vci_tgt_iobx);
451	int_xbar_d->p_to_initiator[iobx_int_srcid] (signal_int_vci_ini_iobx);
452	}
453
454	int_wi_gate_d->p_clk (this->p_clk);
455	int_wi_gate_d->p_resetn (this->p_resetn);
456	int_wi_gate_d->p_vci (signal_int_vci_l2g);
457	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
458	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
459
460	int_wt_gate_d->p_clk (this->p_clk);
461	int_wt_gate_d->p_resetn (this->p_resetn);
462	int_wt_gate_d->p_vci (signal_int_vci_g2l);
463	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
464	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
465
466	////////////////////// M2P DSPIN local crossbar coherence
467	int_xbar_m2p_c->p_clk (this->p_clk);
468	int_xbar_m2p_c->p_resetn (this->p_resetn);
469	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
470	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
471	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
472	for (size_t p = 0; p < nb_procs; p++)
473	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
474
475	////////////////////////// P2M DSPIN local crossbar coherence
476	int_xbar_p2m_c->p_clk (this->p_clk);
477	int_xbar_p2m_c->p_resetn (this->p_resetn);
478	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
479	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
480	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
481	for (size_t p = 0; p < nb_procs; p++)
482	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
483
484	////////////////////// CLACK DSPIN local crossbar coherence
485	int_xbar_clack_c->p_clk (this->p_clk);
486	int_xbar_clack_c->p_resetn (this->p_resetn);
487	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
488	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
489	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
490	for (size_t p = 0; p < nb_procs; p++)
491	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
492
493	//////////////////////////////////// Processors
494	for (size_t p = 0; p < nb_procs; p++)
495	{
496	proc[p]->p_clk (this->p_clk);
497	proc[p]->p_resetn (this->p_resetn);
498	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
499	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
500	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
501	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
502
503	for ( size_t j = 0 ; j < 6 ; j++)
504	{
505	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
506	else proc[p]->p_irq[j] (signal_false);
507	}
508	}
509
510	///////////////////////////////////// XICU
511	xicu->p_clk (this->p_clk);
512	xicu->p_resetn (this->p_resetn);
513	xicu->p_vci (signal_int_vci_tgt_xicu);
514	for ( size_t p=0 ; p < 32 ; p++)
515	{
516	xicu->p_irq[p] (signal_proc_it[p]);
517	}
518	for ( size_t i=0 ; i<32 ; i++)
519	{
520	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
521	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
522	else xicu->p_hwi[i] (signal_false);
523	}
524
525	///////////////////////////////////// MEMC
526	memc->p_clk (this->p_clk);
527	memc->p_resetn (this->p_resetn);
528	memc->p_vci_ixr (signal_ram_vci_ini_memc);
529	memc->p_vci_tgt (signal_int_vci_tgt_memc);
530	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
531	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
532	memc->p_dspin_clack (signal_int_dspin_clack_memc);
533	memc->p_irq (signal_irq_memc);
534
535	// wrapper to RAM network
536	memc_ram_wi->p_clk (this->p_clk);
537	memc_ram_wi->p_resetn (this->p_resetn);
538	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
539	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
540	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
541
542	//////////////////////////////////// XRAM
543	xram->p_clk (this->p_clk);
544	xram->p_resetn (this->p_resetn);
545	xram->p_vci (signal_ram_vci_tgt_xram);
546
547	// wrapper to RAM network
548	xram_ram_wt->p_clk (this->p_clk);
549	xram_ram_wt->p_resetn (this->p_resetn);
550	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
551	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
552	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
553
554	/////////////////////////////////// MDMA
555	mdma->p_clk (this->p_clk);
556	mdma->p_resetn (this->p_resetn);
557	mdma->p_vci_target (signal_int_vci_tgt_mdma);
558	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
559	for (size_t i=0 ; i<nb_dmas ; i++)
560	mdma->p_irq[i] (signal_irq_mdma[i]);
561
562	//////////////////////////// RAM network CMD & RSP routers
563	ram_router_cmd->p_clk (this->p_clk);
564	ram_router_cmd->p_resetn (this->p_resetn);
565	ram_router_rsp->p_clk (this->p_clk);
566	ram_router_rsp->p_resetn (this->p_resetn);
567	for( size_t n=0 ; n<4 ; n++)
568	{
569	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
570	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
571	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
572	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
573	}
574	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
575	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
576	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
577	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
578
579	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
580	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
581	{
582	// IO bridge
583	iob->p_clk (this->p_clk);
584	iob->p_resetn (this->p_resetn);
585	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
586	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
587	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
588	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
589	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
590
591	// initiator wrapper to RAM network
592	iob_ram_wi->p_clk (this->p_clk);
593	iob_ram_wi->p_resetn (this->p_resetn);
594	iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out));
595	iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in));
596	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
597	}
598
599	} // end constructor
600
601	}}
602
603
604	// Local Variables:
605	// tab-width: 3
606	// c-basic-offset: 3
607	// c-file-offsets:((innamespace . 0)(inline-open . 0))
608	// indent-tabs-mode: nil
609	// End:
610
611	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
612
613
614

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Project-Id-Version: Trac 0.12
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PO-Revision-Date: 2010-07-19 23:05+0200
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