Context Navigation

top.cpp @ 1048

Last change on this file since 1048 was 1048, checked in by meunier, 7 years ago
Update of tsar_xbar_cluster (scripts and openmp support)
File size: 48.8 KB

Rev	Line
[344]	1	/////////////////////////////////////////////////////////////////////////
	2	// File: top.cpp
	3	// Author: Alain Greiner
	4	// Copyright: UPMC/LIP6
[396]	5	// Date : may 2013
[344]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
[396]	8	// This file define a generic TSAR architecture.
	9	// The physical address space is 40 bits.
	10	//
[344]	11	// The number of clusters cannot be larger than 256.
	12	// The number of processors per cluster cannot be larger than 8.
	13	//
	14	// - It uses four dspin_local_crossbar per cluster as local interconnect
	15	// - It uses two virtual_dspin routers per cluster as global interconnect
	16	// - It uses the vci_cc_vcache_wrapper
	17	// - It uses the vci_mem_cache
[396]	18	// - It contains one vci_xicu per cluster.
	19	// - It contains one vci_multi_dma per cluster.
	20	// - It contains one vci_simple_ram per cluster to model the L3 cache.
[344]	21	//
[396]	22	// The communication between the MemCache and the Xram is 64 bits.
	23	//
	24	// All clusters are identical, but the cluster 0 (called io_cluster),
[493]	25	// contains 6 extra components:
[344]	26	// - the boot rom (BROM)
	27	// - the disk controller (BDEV)
	28	// - the multi-channel network controller (MNIC)
[493]	29	// - the multi-channel chained buffer dma controller (CDMA)
[344]	30	// - the multi-channel tty controller (MTTY)
	31	// - the frame buffer controller (FBUF)
	32	//
[396]	33	// It is build with one single component implementing a cluster,
	34	// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd)
[344]	35	//
	36	// The IRQs are connected to XICUs as follow:
	37	// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
	38	// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
	39	// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
	40	// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
	41	//
[396]	42	// Some hardware parameters are used when compiling the OS, and are used
	43	// by this top.cpp file. They must be defined in the hard_config.h file :
[344]	44	// - CLUSTER_X : number of clusters in a row (power of 2)
	45	// - CLUSTER_Y : number of clusters in a column (power of 2)
	46	// - CLUSTER_SIZE : size of the segment allocated to a cluster
	47	// - NB_PROCS_MAX : number of processors per cluster (power of 2)
[438]	48	// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9)
	49	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16)
	50	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9)
[344]	51	//
[396]	52	// Some other hardware parameters are not used when compiling the OS,
	53	// and can be directly defined in this top.cpp file:
[344]	54	// - XRAM_LATENCY : external ram latency
	55	// - MEMC_WAYS : L2 cache number of ways
	56	// - MEMC_SETS : L2 cache number of sets
	57	// - L1_IWAYS
	58	// - L1_ISETS
	59	// - L1_DWAYS
	60	// - L1_DSETS
	61	// - FBUF_X_SIZE : width of frame buffer (pixels)
	62	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
	63	// - BDEV_SECTOR_SIZE : block size for block drvice
	64	// - BDEV_IMAGE_NAME : file pathname for block device
	65	// - NIC_RX_NAME : file pathname for NIC received packets
	66	// - NIC_TX_NAME : file pathname for NIC transmited packets
	67	// - NIC_TIMEOUT : max number of cycles before closing a container
[396]	68	/////////////////////////////////////////////////////////////////////////
	69	// General policy for 40 bits physical address decoding:
	70	// All physical segments base addresses are multiple of 1 Mbytes
	71	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
[344]	72	// The (x_width + y_width) MSB bits (left aligned) define
[396]	73	// the cluster index, and the LADR bits define the local index:
[344]	74	// \| X_ID \| Y_ID \|---\| LADR \| OFFSET \|
[396]	75	// \|x_width\|y_width\|---\| 8 \| 24 \|
[344]	76	/////////////////////////////////////////////////////////////////////////
[396]	77	// General policy for 14 bits SRCID decoding:
	78	// Each component is identified by (x_id, y_id, l_id) tuple.
	79	// \| X_ID \| Y_ID \|---\| L_ID \|
	80	// \|x_width\|y_width\|---\| 6 \|
	81	/////////////////////////////////////////////////////////////////////////
[344]	82
	83	#include <systemc>
	84	#include <sys/time.h>
	85	#include <iostream>
	86	#include <sstream>
	87	#include <cstdlib>
	88	#include <cstdarg>
	89	#include <stdint.h>
	90
	91	#include "gdbserver.h"
	92	#include "mapping_table.h"
[663]	93	#include "alloc_elems.h"
[378]	94	#include "tsar_xbar_cluster.h"
[344]	95
[663]	96	#define USE_ALMOS 1
[344]	97
[464]	98
[663]	99	#ifdef USE_ALMOS
	100	#define PREFIX_OS "almos/"
	101	#include "almos/hard_config.h"
	102	#endif
	103
[344]	104	///////////////////////////////////////////////////
	105	// Parallelisation
	106	///////////////////////////////////////////////////
[663]	107
[344]	108
[1048]	109	#ifdef USE_OPENMP
	110	#include <omp.h>
[344]	111	#endif
	112
[1012]	113	// nluster index (computed from x,y coordinates)
[619]	114	#ifdef USE_ALMOS
[663]	115	#define cluster(x,y) (y + x * Y_SIZE)
[619]	116	#else
[663]	117	#define cluster(x,y) (y + (x << Y_WIDTH))
[619]	118	#endif
[344]	119
[619]	120
[547]	121	#define min(x, y) (x < y ? x : y)
	122
[344]	123	///////////////////////////////////////////////////////////
	124	// DSPIN parameters
	125	///////////////////////////////////////////////////////////
	126
[404]	127	#define dspin_cmd_width 39
	128	#define dspin_rsp_width 32
[344]	129
[396]	130	///////////////////////////////////////////////////////////
	131	// VCI parameters
	132	///////////////////////////////////////////////////////////
	133
[438]	134	#define vci_cell_width_int 4
	135	#define vci_cell_width_ext 8
[396]	136
[504]	137	#ifdef USE_ALMOS
	138	#define vci_address_width 32
	139	#endif
[438]	140	#define vci_plen_width 8
	141	#define vci_rerror_width 1
	142	#define vci_clen_width 1
	143	#define vci_rflag_width 1
	144	#define vci_srcid_width 14
	145	#define vci_pktid_width 4
	146	#define vci_trdid_width 4
	147	#define vci_wrplen_width 1
[493]	148
[344]	149	////////////////////////////////////////////////////////////
[396]	150	// Secondary Hardware Parameters
[344]	151	//////////////////////i/////////////////////////////////////
	152
[438]	153
[344]	154	#define XRAM_LATENCY 0
	155
	156	#define MEMC_WAYS 16
	157	#define MEMC_SETS 256
	158
	159	#define L1_IWAYS 4
	160	#define L1_ISETS 64
	161
	162	#define L1_DWAYS 4
	163	#define L1_DSETS 64
	164
[464]	165	#ifdef USE_ALMOS
[663]	166	#define FBUF_X_SIZE 1024
	167	#define FBUF_Y_SIZE 1024
[464]	168	#endif
[344]	169
[464]	170	#ifdef USE_ALMOS
	171	#define BDEV_SECTOR_SIZE 4096
	172	#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin"
	173	#endif
[344]	174
[464]	175	#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt"
	176	#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt"
[344]	177	#define NIC_TIMEOUT 10000
	178
[438]	179	#define NORTH 0
	180	#define SOUTH 1
	181	#define EAST 2
	182	#define WEST 3
	183
[344]	184	////////////////////////////////////////////////////////////
	185	// Software to be loaded in ROM & RAM
	186	//////////////////////i/////////////////////////////////////
	187
[464]	188	#ifdef USE_ALMOS
[1012]	189	#define soft_name PREFIX_OS"preloader.elf"
[464]	190	#endif
[344]	191
	192	////////////////////////////////////////////////////////////
	193	// DEBUG Parameters default values
	194	//////////////////////i/////////////////////////////////////
	195
[663]	196	#define MAX_FROZEN_CYCLES 100000000
[344]	197
[572]	198
	199	////////////////////////////////////////////////////////////////////
	200	// TGTID definition in direct space
	201	// For all components: global TGTID = global SRCID = cluster_index
	202	////////////////////////////////////////////////////////////////////
	203
	204
[344]	205	/////////////////////////////////////////////////////////
	206	// Physical segments definition
	207	/////////////////////////////////////////////////////////
	208	// There is 3 segments replicated in all clusters
	209	// and 5 specific segments in the "IO" cluster
	210	// (containing address 0xBF000000)
	211	/////////////////////////////////////////////////////////
	212
[547]	213	#ifdef USE_GIET
[1012]	214	#error "This platform is no more supported for the GIET"
[504]	215	#endif
[344]	216
[504]	217	bool stop_called = false;
	218
[1048]	219	using namespace sc_core;
	220	using namespace soclib::caba;
	221	using namespace soclib::common;
	222
[344]	223	/////////////////////////////////
	224	int _main(int argc, char *argv[])
	225	{
	226
[1048]	227	const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call
	228	int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles
	229	char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image
	230	char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file
	231	char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file
	232	ssize_t threads_nr = 1; // simulator's threads number
	233	bool debug_ok = false; // trace activated
	234	size_t debug_period = 1; // trace period
	235	size_t debug_memc_id = 0; // index of memc to be traced
	236	size_t debug_proc_id = 0; // index of proc to be traced
	237	int64_t debug_from = 0; // trace start cycle
	238	int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor
	239	int64_t reset_counters = -1;
	240	int64_t dump_counters = -1;
	241	bool do_reset_counters = false;
	242	bool do_dump_counters = false;
	243	struct timeval t1, t2;
	244	uint64_t ms1, ms2;
[344]	245
[1048]	246	////////////// command line arguments //////////////////////
	247	if (argc > 1) {
	248	for (int n = 1; n < argc; n = n + 2) {
	249	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) {
	250	ncycles = (int64_t) strtol(argv[n + 1], NULL, 0);
	251	}
	252	else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) {
[464]	253	#ifdef USE_ALMOS
[1048]	254	assert( 0 && "Can't define almos soft name" );
[464]	255	#endif
[1048]	256	}
	257	else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) {
	258	strcpy(disk_name, argv[n + 1]);
	259	}
	260	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) {
	261	debug_ok = true;
	262	debug_from = (int64_t) strtol(argv[n + 1], NULL, 0);
	263	}
	264	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) {
	265	debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
[619]	266	#ifdef USE_ALMOS
[1048]	267	assert((debug_memc_id < (X_SIZE * Y_SIZE)) &&
	268	"debug_memc_id larger than X_SIZE * Y_SIZE" );
[619]	269	#else
[1048]	270	size_t x = debug_memc_id >> Y_WIDTH;
	271	size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1);
[619]	272
[1048]	273	assert( (x <= X_SIZE) and (y <= Y_SIZE) &&
	274	"MEMCID parameter refers a not valid memory cache");
[619]	275	#endif
[1048]	276	}
	277	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) {
	278	debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
[619]	279	#ifdef USE_ALMOS
[1048]	280	assert((debug_proc_id < (X_SIZE * Y_SIZE * NB_PROCS_MAX)) &&
	281	"debug_proc_id larger than X_SIZE * Y_SIZE * NB_PROCS");
[619]	282	#else
[1048]	283	size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ;
	284	size_t x = cluster_xy >> Y_WIDTH;
	285	size_t y = cluster_xy & ((1 << Y_WIDTH) - 1);
[619]	286
[1048]	287	assert( (x <= X_SIZE) and (y <= Y_SIZE) &&
	288	"PROCID parameter refers a not valid processor");
[619]	289	#endif
[1048]	290	}
	291	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) {
	292	threads_nr = (ssize_t) strtol(argv[n + 1], NULL, 0);
	293	threads_nr = (threads_nr < 1) ? 1 : threads_nr;
	294	}
	295	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) {
	296	frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0);
	297	}
	298	else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) {
	299	debug_period = (size_t) strtol(argv[n + 1], NULL, 0);
	300	}
	301	else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) {
	302	reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0);
	303	do_reset_counters = true;
	304	}
	305	else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) {
	306	dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0);
	307	do_dump_counters = true;
	308	}
	309	else {
	310	std::cout << " Arguments are (key,value) couples." << std::endl;
	311	std::cout << " The order is not important." << std::endl;
	312	std::cout << " Accepted arguments are :" << std::endl << std::endl;
	313	std::cout << " -SOFT pathname_for_embedded_soft" << std::endl;
	314	std::cout << " -DISK pathname_for_disk_image" << std::endl;
	315	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
	316	std::cout << " -DEBUG debug_start_cycle" << std::endl;
	317	std::cout << " -THREADS simulator's threads number" << std::endl;
	318	std::cout << " -FROZEN max_number_of_lines" << std::endl;
	319	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
	320	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
	321	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
	322	exit(0);
	323	}
	324	}
	325	}
[344]	326
[396]	327	// checking hardware parameters
[663]	328	assert( ( (X_SIZE == 1) or (X_SIZE == 2) or (X_SIZE == 4) or
	329	(X_SIZE == 8) or (X_SIZE == 16) ) and
	330	"The X_SIZE parameter must be 1, 2, 4, 8 or 16" );
[344]	331
[663]	332	assert( ( (Y_SIZE == 1) or (Y_SIZE == 2) or (Y_SIZE == 4) or
	333	(Y_SIZE == 8) or (Y_SIZE == 16) ) and
	334	"The Y_SIZE parameter must be 1, 2, 4, 8 or 16" );
[344]	335
[396]	336	assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
	337	(NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
	338	"The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
[344]	339
[396]	340	assert( (NB_DMA_CHANNELS < 9) and
	341	"The NB_DMA_CHANNELS parameter must be smaller than 9" );
[344]	342
[396]	343	assert( (NB_TTY_CHANNELS < 15) and
	344	"The NB_TTY_CHANNELS parameter must be smaller than 15" );
[344]	345
[396]	346	assert( (NB_NIC_CHANNELS < 9) and
	347	"The NB_NIC_CHANNELS parameter must be smaller than 9" );
[344]	348
[504]	349	#ifdef USE_ALMOS
	350	assert( (vci_address_width == 32) and
	351	"VCI address width with ALMOS must be 32 bits" );
	352	#endif
	353
	354
[396]	355	std::cout << std::endl;
[663]	356	std::cout << " - X_SIZE = " << X_SIZE << std::endl;
	357	std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
[438]	358	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
[396]	359	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
[438]	360	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
	361	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
	362	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
	363	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
	364	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
	365	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
[396]	366
	367	std::cout << std::endl;
	368	// Internal and External VCI parameters definition
[438]	369	typedef soclib::caba::VciParams<vci_cell_width_int,
	370	vci_plen_width,
	371	vci_address_width,
	372	vci_rerror_width,
	373	vci_clen_width,
	374	vci_rflag_width,
	375	vci_srcid_width,
	376	vci_pktid_width,
	377	vci_trdid_width,
	378	vci_wrplen_width> vci_param_int;
[396]	379
[438]	380	typedef soclib::caba::VciParams<vci_cell_width_ext,
	381	vci_plen_width,
	382	vci_address_width,
	383	vci_rerror_width,
	384	vci_clen_width,
	385	vci_rflag_width,
	386	vci_srcid_width,
	387	vci_pktid_width,
	388	vci_trdid_width,
	389	vci_wrplen_width> vci_param_ext;
[396]	390
[1048]	391	#ifdef USE_OPENMP
	392	omp_set_dynamic(false);
	393	omp_set_num_threads(threads_nr);
	394	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	395	std::cerr << "Run with " << threads_nr << " threads" << std::endl;
[344]	396	#endif
	397
[1048]	398	// Define parameters depending on mesh size
	399	size_t x_width;
	400	size_t y_width;
[663]	401
[619]	402	#ifdef USE_ALMOS
[1048]	403	if (X_SIZE == 1) x_width = 0;
	404	else if (X_SIZE == 2) x_width = 1;
	405	else if (X_SIZE <= 4) x_width = 2;
	406	else if (X_SIZE <= 8) x_width = 3;
	407	else x_width = 4;
[344]	408
[1048]	409	if (Y_SIZE == 1) y_width = 0;
	410	else if (Y_SIZE == 2) y_width = 1;
	411	else if (Y_SIZE <= 4) y_width = 2;
	412	else if (Y_SIZE <= 8) y_width = 3;
	413	else y_width = 4;
[344]	414
[619]	415	#else
[1048]	416	size_t x_width = X_WIDTH;
	417	size_t y_width = Y_WIDTH;
[619]	418
[1048]	419	assert((X_WIDTH <= 4) and (Y_WIDTH <= 4) and
	420	"Up to 256 clusters");
[619]	421
[1048]	422	assert((X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and
	423	"The X_WIDTH and Y_WIDTH parameter are insufficient");
[619]	424
[504]	425	#endif
	426
[1048]	427	/////////////////////
	428	// Mapping Tables
	429	/////////////////////
[344]	430
[1048]	431	// internal network
	432	MappingTable maptabd(vci_address_width,
	433	IntTab(x_width + y_width, 16 - x_width - y_width),
	434	IntTab(x_width + y_width, vci_srcid_width - x_width - y_width),
	435	0x00FF800000);
[344]	436
[1048]	437	for (size_t x = 0; x < X_SIZE; x++) {
	438	for (size_t y = 0; y < Y_SIZE; y++) {
	439	sc_uint<vci_address_width> offset;
	440	offset = (sc_uint<vci_address_width>) cluster(x,y)
	441	<< (vci_address_width - x_width - y_width);
[344]	442
[1048]	443	std::ostringstream si;
	444	si << "seg_xicu_" << x << "_" << y;
	445	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
	446	IntTab(cluster(x,y), XCU_TGTID), false));
[344]	447
[1048]	448	std::ostringstream sd;
	449	sd << "seg_mdma_" << x << "_" << y;
	450	maptabd.add(Segment(sd.str(), SEG_DMA_BASE + offset, SEG_DMA_SIZE,
	451	IntTab(cluster(x,y), DMA_TGTID), false));
[344]	452
[1048]	453	std::ostringstream sh;
	454	sh << "seg_memc_" << x << "_" << y;
	455	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
	456	IntTab(cluster(x,y), RAM_TGTID), true));
[547]	457
[1048]	458	if (x == X_IO && y == Y_IO) {
	459	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE, SEG_TTY_SIZE,
	460	IntTab(cluster(x,y),TTY_TGTID), false));
	461	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE, SEG_FBF_SIZE,
	462	IntTab(cluster(x,y),FBF_TGTID), false));
	463	maptabd.add(Segment("seg_bdev", SEG_IOC_BASE, SEG_IOC_SIZE,
	464	IntTab(cluster(x,y),IOC_TGTID), false));
	465	maptabd.add(Segment("seg_brom", SEG_ROM_BASE, SEG_ROM_SIZE,
	466	IntTab(cluster(x,y),ROM_TGTID), true));
	467	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE, SEG_NIC_SIZE,
	468	IntTab(cluster(x,y),NIC_TGTID), false));
	469	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE, SEG_CMA_SIZE,
	470	IntTab(cluster(x,y),CMA_TGTID), false));
	471	maptabd.add(Segment("seg_simh", SEG_SIM_BASE, SEG_SIM_SIZE,
	472	IntTab(cluster(x,y),SIM_TGTID), false));
	473	}
	474	}
	475	}
	476	std::cout << maptabd << std::endl;
[344]	477
[1048]	478	// external network
	479	MappingTable maptabx(vci_address_width,
	480	IntTab(x_width + y_width),
	481	IntTab(x_width + y_width),
	482	0xFFFF000000ULL);
[344]	483
[1048]	484	for (size_t x = 0; x < X_SIZE; x++) {
	485	for (size_t y = 0; y < Y_SIZE ; y++) {
[396]	486
[1048]	487	sc_uint<vci_address_width> offset;
	488	offset = (sc_uint<vci_address_width>) cluster(x,y)
	489	<< (vci_address_width - x_width - y_width);
[396]	490
[1048]	491	std::ostringstream sh;
	492	sh << "x_seg_memc_" << x << "_" << y;
[396]	493
[1048]	494	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
	495	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
	496	}
	497	}
	498	std::cout << maptabx << std::endl;
[344]	499
[1048]	500	////////////////////
	501	// Signals
	502	///////////////////
[344]	503
[1048]	504	sc_clock signal_clk("clk");
	505	sc_signal<bool> signal_resetn("resetn");
[344]	506
[1048]	507	// Horizontal inter-clusters DSPIN signals
	508	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
	509	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE - 1, Y_SIZE);
	510	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
	511	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE - 1, Y_SIZE);
[344]	512
[1048]	513	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
	514	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE - 1, Y_SIZE);
	515	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
	516	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE - 1, Y_SIZE);
[885]	517
[1048]	518	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
	519	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE- 1 , Y_SIZE);
	520	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
	521	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE - 1, Y_SIZE);
[885]	522
[1048]	523	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
	524	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE - 1, Y_SIZE);
	525	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
	526	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE - 1, Y_SIZE);
[885]	527
[1048]	528	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
	529	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE - 1, Y_SIZE);
	530	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
	531	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE - 1, Y_SIZE);
[885]	532
[1048]	533	// Vertical inter-clusters DSPIN signals
	534	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
	535	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE - 1);
	536	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
	537	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE - 1);
[344]	538
[1048]	539	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
	540	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE - 1);
	541	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
	542	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE - 1);
[344]	543
[1048]	544	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
	545	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE - 1);
	546	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
	547	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE - 1);
[885]	548
[1048]	549	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
	550	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE - 1);
	551	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
	552	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE - 1);
[885]	553
[1048]	554	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
	555	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE - 1);
	556	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
	557	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE - 1);
[885]	558
[1048]	559	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
	560	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
	561	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
	562	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
	563	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
[885]	564
[1048]	565	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
	566	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
	567	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
	568	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
[885]	569
[1048]	570	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
	571	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
	572	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
	573	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
[885]	574
[1048]	575	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
	576	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
	577	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
	578	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
[885]	579
[1048]	580	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
	581	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
	582	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
	583	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
[885]	584
	585
[1048]	586	////////////////////////////
	587	// Loader
	588	////////////////////////////
[344]	589
[1048]	590	soclib::common::Loader loader(soft_name);
[344]	591
[1048]	592	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
	593	proc_iss::set_loader(loader);
[344]	594
[1048]	595	////////////////////////////
	596	// Clusters construction
	597	////////////////////////////
[344]	598
[1048]	599	TsarXbarCluster<dspin_cmd_width,
	600	dspin_rsp_width,
	601	vci_param_int,
	602	vci_param_ext> * clusters[X_SIZE][Y_SIZE];
[344]	603
[1048]	604	#ifdef USE_OPENMP
[344]	605	#pragma omp parallel
[1048]	606	#endif
[344]	607	{
[1048]	608	#ifdef USE_OPENMP
[344]	609	#pragma omp for
	610	#endif
[1048]	611	for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) {
	612	size_t x = i / Y_SIZE;
	613	size_t y = i % Y_SIZE;
[344]	614
[1048]	615	#ifdef USE_OPENMP
[344]	616	#pragma omp critical
	617	#endif
[1048]	618	{
[438]	619	std::cout << std::endl;
	620	std::cout << "Cluster_" << x << "_" << y << std::endl;
	621	std::cout << std::endl;
[389]	622
[344]	623	std::ostringstream sc;
	624	sc << "cluster_" << x << "_" << y;
[396]	625	clusters[x][y] = new TsarXbarCluster<dspin_cmd_width,
[1048]	626	dspin_rsp_width,
	627	vci_param_int,
	628	vci_param_ext>
	629	(
	630	sc.str().c_str(),
	631	NB_PROCS_MAX,
	632	NB_TTY_CHANNELS,
	633	NB_DMA_CHANNELS,
	634	x,
	635	y,
	636	cluster(x,y),
	637	maptabd,
	638	maptabx,
	639	x_width,
	640	y_width,
	641	vci_srcid_width - x_width - y_width, // l_id width,
	642	P_WIDTH,
	643	RAM_TGTID,
	644	XCU_TGTID,
	645	DMA_TGTID,
	646	FBF_TGTID,
	647	TTY_TGTID,
	648	ROM_TGTID,
	649	NIC_TGTID,
	650	CMA_TGTID,
	651	IOC_TGTID,
	652	SIM_TGTID,
	653	MEMC_WAYS,
	654	MEMC_SETS,
	655	L1_IWAYS,
	656	L1_ISETS,
	657	L1_DWAYS,
	658	L1_DSETS,
	659	IRQ_PER_PROCESSOR,
	660	XRAM_LATENCY,
	661	x == X_IO && y == Y_IO,
	662	FBF_X_SIZE,
	663	FBF_Y_SIZE,
	664	disk_name,
	665	BDEV_SECTOR_SIZE,
	666	NB_NIC_CHANNELS,
	667	nic_rx_name,
	668	nic_tx_name,
	669	NIC_TIMEOUT,
	670	NB_CMA_CHANNELS,
	671	loader,
	672	frozen_cycles,
	673	debug_from,
	674	debug_ok,
	675	debug_ok
	676	);
[344]	677
[1048]	678	}
[344]	679	}
[1048]	680	}
[344]	681
[1048]	682	///////////////////////////////////////////////////////////////
	683	// Net-list
	684	///////////////////////////////////////////////////////////////
[344]	685
[1048]	686	// Clock & RESET
	687	for (int x = 0; x < X_SIZE; x++) {
	688	for (int y = 0; y < Y_SIZE; y++) {
	689	clusters[x][y]->p_clk (signal_clk);
	690	clusters[x][y]->p_resetn (signal_resetn);
	691	}
	692	}
[344]	693
[1048]	694	// Inter Clusters horizontal connections
	695	for (int x = 0; x < X_SIZE - 1; x++) {
	696	for (int y = 0; y < Y_SIZE; y++) {
	697	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
	698	clusters[x + 1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
	699	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
	700	clusters[x + 1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
[468]	701
[1048]	702	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
	703	clusters[x + 1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
	704	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
	705	clusters[x + 1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
[885]	706
[1048]	707	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
	708	clusters[x + 1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
	709	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
	710	clusters[x + 1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
[885]	711
[1048]	712	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
	713	clusters[x + 1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
	714	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
	715	clusters[x + 1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
[885]	716
[1048]	717	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
	718	clusters[x + 1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
	719	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
	720	clusters[x + 1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
	721	}
	722	}
	723	std::cout << std::endl << "Horizontal connections done" << std::endl;
[344]	724
[1048]	725	// Inter Clusters vertical connections
	726	for (int y = 0; y < Y_SIZE - 1; y++) {
	727	for (int x = 0; x < X_SIZE; x++) {
	728	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
	729	clusters[x][y + 1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
	730	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
	731	clusters[x][y + 1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
[468]	732
[1048]	733	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
	734	clusters[x][y + 1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
	735	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
	736	clusters[x][y + 1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
[885]	737
[1048]	738	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
	739	clusters[x][y + 1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
	740	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
	741	clusters[x][y + 1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
[885]	742
[1048]	743	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
	744	clusters[x][y + 1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
	745	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
	746	clusters[x][y + 1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
[885]	747
[1048]	748	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
	749	clusters[x][y + 1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
	750	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
	751	clusters[x][y + 1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
	752	}
	753	}
	754	std::cout << std::endl << "Vertical connections done" << std::endl;
[344]	755
[1048]	756	// East & West boundary cluster connections
	757	for (size_t y = 0; y < Y_SIZE; y++) {
	758	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
	759	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
	760	clusters[X_SIZE - 1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE - 1][y][EAST]);
	761	clusters[X_SIZE - 1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE - 1][y][EAST]);
[468]	762
[1048]	763	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
	764	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
	765	clusters[X_SIZE - 1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE - 1][y][EAST]);
	766	clusters[X_SIZE - 1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE - 1][y][EAST]);
[885]	767
[1048]	768	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
	769	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
	770	clusters[X_SIZE - 1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE - 1][y][EAST]);
	771	clusters[X_SIZE - 1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE - 1][y][EAST]);
[885]	772
[1048]	773	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
	774	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
	775	clusters[X_SIZE - 1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE - 1][y][EAST]);
	776	clusters[X_SIZE - 1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE - 1][y][EAST]);
[885]	777
[1048]	778	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
	779	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
	780	clusters[X_SIZE - 1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE - 1][y][EAST]);
	781	clusters[X_SIZE - 1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE - 1][y][EAST]);
	782	}
[344]	783
[1048]	784	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
[885]	785
[1048]	786	// North & South boundary clusters connections
	787	for (size_t x = 0; x < X_SIZE; x++) {
	788	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
	789	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
	790	clusters[x][Y_SIZE - 1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE - 1][NORTH]);
	791	clusters[x][Y_SIZE - 1]->p_cmd_out[NORTH](signal_dspin_bound_cmd_out[x][Y_SIZE - 1][NORTH]);
[468]	792
[1048]	793	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
	794	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
	795	clusters[x][Y_SIZE - 1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE - 1][NORTH]);
	796	clusters[x][Y_SIZE - 1]->p_rsp_out[NORTH](signal_dspin_bound_rsp_out[x][Y_SIZE - 1][NORTH]);
[885]	797
[1048]	798	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
	799	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
	800	clusters[x][Y_SIZE - 1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE - 1][NORTH]);
	801	clusters[x][Y_SIZE - 1]->p_m2p_out[NORTH](signal_dspin_bound_m2p_out[x][Y_SIZE - 1][NORTH]);
[885]	802
[1048]	803	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
	804	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
	805	clusters[x][Y_SIZE - 1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE - 1][NORTH]);
	806	clusters[x][Y_SIZE - 1]->p_p2m_out[NORTH](signal_dspin_bound_p2m_out[x][Y_SIZE - 1][NORTH]);
[885]	807
[1048]	808	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
	809	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
	810	clusters[x][Y_SIZE - 1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE - 1][NORTH]);
	811	clusters[x][Y_SIZE - 1]->p_cla_out[NORTH](signal_dspin_bound_cla_out[x][Y_SIZE - 1][NORTH]);
	812	}
[885]	813
[1048]	814	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
	815	std::cout << std::endl;
[344]	816
	817
[836]	818	#ifdef WT_IDL
	819	std::list<VciCcVCacheWrapper<vci_param_int,
	820	dspin_cmd_width,
	821	dspin_rsp_width,
	822	GdbServer<Mips32ElIss> > * > l1_caches;
	823
[1048]	824	for (int x = 0; x < X_SIZE; x++) {
	825	for (int y = 0; y < Y_SIZE; y++) {
	826	for (int proc = 0; proc < NB_PROCS_MAX; proc++) {
	827	l1_caches.push_back(clusters[x][y]->proc[proc]);
	828	}
	829	}
	830	}
[836]	831
[1048]	832	for (int x = 0; x < X_SIZE; x++) {
	833	for (int y = 0; y < Y_SIZE; y++) {
	834	clusters[x][y]->memc->set_vcache_list(l1_caches);
	835	}
	836	}
[836]	837	#endif
	838
	839
[779]	840	//#define SC_TRACE
[752]	841	#ifdef SC_TRACE
[1048]	842	sc_trace_file * tf = sc_create_vcd_trace_file("my_trace_file");
[752]	843
[1048]	844	for (int x = 0; x < X_SIZE - 1; x++) {
	845	for (int y = 0; y < Y_SIZE; y++) {
	846	for (int k = 0; k < 3; k++) {
	847	signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc");
	848	signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec");
	849	}
[752]	850
[1048]	851	for (int k = 0; k < 2; k++) {
	852	signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc");
	853	signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec");
	854	}
	855	}
	856	}
[752]	857
[1048]	858	for (int y = 0; y < Y_SIZE - 1; y++) {
	859	for (int x = 0; x < X_SIZE; x++) {
	860	for (int k = 0; k < 3; k++) {
	861	signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc");
	862	signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec");
	863	}
[752]	864
[1048]	865	for (int k = 0; k < 2; k++) {
	866	signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc");
	867	signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec");
	868	}
	869	}
	870	}
[752]	871
[1048]	872	for (int x = 0; x < (X_SIZE); x++) {
	873	for (int y = 0; y < Y_SIZE; y++) {
	874	std::ostringstream signame;
	875	signame << "cluster" << x << "_" << y;
	876	clusters[x][y]->trace(tf, signame.str());
	877	}
	878	}
[752]	879	#endif
	880
[779]	881
[1048]	882	////////////////////////////////////////////////////////
	883	// Simulation
	884	///////////////////////////////////////////////////////
[779]	885
[1048]	886	sc_start(sc_core::sc_time(0, SC_NS));
	887	signal_resetn = false;
[779]	888
[1048]	889	// set network boundaries signals default values
	890	// for all boundary clusters
	891	for (size_t x = 0; x < X_SIZE ; x++) {
	892	for (size_t y = 0; y < Y_SIZE ; y++) {
	893	for (size_t face = 0; face < 4; face++) {
	894	signal_dspin_bound_cmd_in [x][y][face].write = false;
	895	signal_dspin_bound_cmd_in [x][y][face].read = true;
	896	signal_dspin_bound_cmd_out[x][y][face].write = false;
	897	signal_dspin_bound_cmd_out[x][y][face].read = true;
[885]	898
[1048]	899	signal_dspin_bound_rsp_in [x][y][face].write = false;
	900	signal_dspin_bound_rsp_in [x][y][face].read = true;
	901	signal_dspin_bound_rsp_out[x][y][face].write = false;
	902	signal_dspin_bound_rsp_out[x][y][face].read = true;
[885]	903
[1048]	904	signal_dspin_bound_m2p_in [x][y][face].write = false;
	905	signal_dspin_bound_m2p_in [x][y][face].read = true;
	906	signal_dspin_bound_m2p_out[x][y][face].write = false;
	907	signal_dspin_bound_m2p_out[x][y][face].read = true;
[885]	908
[1048]	909	signal_dspin_bound_p2m_in [x][y][face].write = false;
	910	signal_dspin_bound_p2m_in [x][y][face].read = true;
	911	signal_dspin_bound_p2m_out[x][y][face].write = false;
	912	signal_dspin_bound_p2m_out[x][y][face].read = true;
[885]	913
[1048]	914	signal_dspin_bound_cla_in [x][y][face].write = false;
	915	signal_dspin_bound_cla_in [x][y][face].read = true;
	916	signal_dspin_bound_cla_out[x][y][face].write = false;
	917	signal_dspin_bound_cla_out[x][y][face].read = true;
	918	}
	919	}
	920	}
	921	// @QM : what is the following line?
	922	//clusters[0][0]->signal_dspin_m2p_proc[2].read = true;
[779]	923
[1048]	924	sc_start(sc_core::sc_time(1, SC_NS));
	925	signal_resetn = true;
[779]	926
[1048]	927	if (debug_ok) {
	928	#ifdef USE_OPENMP
	929	assert(false && "OPEN MP should not be used with debug because of its traces");
	930	#endif
[464]	931
[1048]	932	if (gettimeofday(&t1, NULL) != 0) {
	933	perror("gettimeofday");
	934	return EXIT_FAILURE;
	935	}
[396]	936
[1048]	937	for (int64_t n = 1; n < ncycles && !stop_called; n++) {
	938	if ((n % max_cycles) == 0) {
[663]	939
[1048]	940	if (gettimeofday(&t2, NULL) != 0) {
	941	perror("gettimeofday");
	942	return EXIT_FAILURE;
	943	}
[663]	944
[1048]	945	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	946	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
	947	std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
[663]	948
[1048]	949	if (gettimeofday(&t1, NULL) != 0) {
	950	perror("gettimeofday");
	951	return EXIT_FAILURE;
	952	}
[663]	953	}
[464]	954
	955
[1048]	956	if (n == reset_counters) {
	957	for (size_t x = 0; x < (X_SIZE); x++) {
	958	for (size_t y = 0; y < Y_SIZE; y++) {
	959	clusters[x][y]->memc->reset_counters();
	960	}
	961	}
[663]	962	}
[464]	963
[1048]	964	if (n == dump_counters) {
	965	for (size_t x = 0; x < (X_SIZE); x++) {
	966	for (size_t y = 0; y < Y_SIZE; y++) {
	967	clusters[x][y]->memc->print_stats(true, false);
	968	}
	969	}
[663]	970	}
[344]	971
[1048]	972	if ((n > debug_from) and (n % debug_period == 0)) {
	973	std::cout << "****************** cycle " << std::dec << n ;
	974	std::cout << "************************************************" << std::endl;
[379]	975
[1048]	976	for (size_t x = 0; x < X_SIZE ; x++) {
	977	for (size_t y = 0; y < Y_SIZE ; y++) {
	978	for (int proc = 0; proc < NB_PROCS_MAX; proc++) {
	979	clusters[x][y]->proc[proc]->print_trace();
	980	std::ostringstream proc_signame;
	981	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc ;
	982	std::ostringstream p2m_signame;
	983	p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " P2M";
	984	std::ostringstream m2p_signame;
	985	m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " M2P";
[404]	986
[1048]	987	clusters[x][y]->signal_vci_ini_proc[proc].print_trace(proc_signame.str());
	988	clusters[x][y]->signal_dspin_p2m_proc[proc].print_trace(p2m_signame.str());
	989	clusters[x][y]->signal_dspin_m2p_proc[proc].print_trace(m2p_signame.str());
	990	}
[404]	991
[1048]	992	clusters[x][y]->memc->print_trace();
[344]	993
[1048]	994	std::ostringstream smemc;
	995	smemc << "[SIG]MEMC_" << x << "_" << y;
	996	std::ostringstream sxram;
	997	sxram << "[SIG]XRAM_" << x << "_" << y;
	998	std::ostringstream sm2p;
	999	sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P";
	1000	std::ostringstream sp2m;
	1001	sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M";
[344]	1002
[1048]	1003	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	1004	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
	1005	clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str());
	1006	clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str());
	1007	}
	1008	}
[836]	1009	}
[663]	1010
[1048]	1011	sc_start(sc_core::sc_time(1, SC_NS));
	1012	}
	1013	}
	1014	else {
	1015	int64_t n = 0;
	1016	while (!stop_called && n != ncycles) {
	1017	if (gettimeofday(&t1, NULL) != 0) {
	1018	perror("gettimeofday");
	1019	return EXIT_FAILURE;
	1020	}
	1021	int64_t nb_cycles = min(max_cycles, ncycles - n);
	1022	if (do_reset_counters) {
	1023	nb_cycles = min(nb_cycles, reset_counters - n);
	1024	}
	1025	if (do_dump_counters) {
	1026	nb_cycles = min(nb_cycles, dump_counters - n);
	1027	}
[344]	1028
[1048]	1029	sc_start(sc_core::sc_time(nb_cycles, SC_NS));
	1030	n += nb_cycles;
[663]	1031
[1048]	1032	if (do_reset_counters && n == reset_counters) {
	1033	// Reseting counters
	1034	for (size_t x = 0; x < (X_SIZE); x++) {
	1035	for (size_t y = 0; y < Y_SIZE; y++) {
	1036	clusters[x][y]->memc->reset_counters();
	1037	}
	1038	}
	1039	do_reset_counters = false;
[663]	1040	}
	1041
[1048]	1042	if (do_dump_counters && n == dump_counters) {
	1043	// Dumping counters
	1044	for (size_t x = 0; x < (X_SIZE); x++) {
	1045	for (size_t y = 0; y < Y_SIZE; y++) {
	1046	clusters[x][y]->memc->print_stats(true, false);
	1047	}
	1048	}
	1049	do_dump_counters = false;
[663]	1050	}
	1051
	1052
[1048]	1053	if (gettimeofday(&t2, NULL) != 0) {
	1054	perror("gettimeofday");
	1055	return EXIT_FAILURE;
	1056	}
	1057	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	1058	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
	1059	std::cerr << std::dec << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl;
	1060	}
	1061	}
[504]	1062
[885]	1063
[1048]	1064	// Free memory
	1065	for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) {
	1066	size_t x = i / Y_SIZE;
	1067	size_t y = i % Y_SIZE;
	1068	delete clusters[x][y];
	1069	}
[504]	1070
[1048]	1071	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE);
	1072	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE);
[512]	1073
[1048]	1074	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE);
	1075	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE);
[885]	1076
[1048]	1077	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_inc, X_SIZE - 1, Y_SIZE);
	1078	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_m2p_dec, X_SIZE - 1, Y_SIZE);
[885]	1079
[1048]	1080	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_inc, X_SIZE - 1, Y_SIZE);
	1081	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_h_p2m_dec, X_SIZE - 1, Y_SIZE);
[885]	1082
[1048]	1083	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_inc, X_SIZE - 1, Y_SIZE);
	1084	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_h_cla_dec, X_SIZE - 1, Y_SIZE);
[885]	1085
[1048]	1086	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1);
	1087	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1);
[885]	1088
[1048]	1089	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1);
	1090	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1);
[885]	1091
[1048]	1092	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_inc, X_SIZE, Y_SIZE - 1);
	1093	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_m2p_dec, X_SIZE, Y_SIZE - 1);
[885]	1094
[1048]	1095	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_inc, X_SIZE, Y_SIZE - 1);
	1096	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_v_p2m_dec, X_SIZE, Y_SIZE - 1);
[885]	1097
[1048]	1098	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_inc, X_SIZE, Y_SIZE - 1);
	1099	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_v_cla_dec, X_SIZE, Y_SIZE - 1);
[885]	1100
[1048]	1101	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cmd_in, X_SIZE, Y_SIZE, 4);
	1102	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cmd_out, X_SIZE, Y_SIZE, 4);
[885]	1103
[1048]	1104	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_rsp_in, X_SIZE, Y_SIZE, 4);
	1105	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_rsp_out, X_SIZE, Y_SIZE, 4);
[885]	1106
[1048]	1107	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_m2p_in, X_SIZE, Y_SIZE, 4);
	1108	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_m2p_out, X_SIZE, Y_SIZE, 4);
[885]	1109
[1048]	1110	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_p2m_in, X_SIZE, Y_SIZE, 4);
	1111	dealloc_elems<DspinSignals<dspin_rsp_width> >(signal_dspin_bound_p2m_out, X_SIZE, Y_SIZE, 4);
[885]	1112
[1048]	1113	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cla_in, X_SIZE, Y_SIZE, 4);
	1114	dealloc_elems<DspinSignals<dspin_cmd_width> >(signal_dspin_bound_cla_out, X_SIZE, Y_SIZE, 4);
[885]	1115
[1048]	1116	return EXIT_SUCCESS;
[344]	1117	}
	1118
[504]	1119
	1120	void handler(int dummy = 0) {
[1048]	1121	stop_called = true;
	1122	sc_stop();
[504]	1123	}
	1124
[547]	1125	void voidhandler(int dummy = 0) {}
[504]	1126
[1023]	1127	int sc_main (int argc, char *argv[]) {
[1048]	1128	signal(SIGINT, handler);
	1129	signal(SIGPIPE, voidhandler);
[504]	1130
[1048]	1131	try {
	1132	int ret =_main(argc, argv);
	1133	if (!stop_called) {
	1134	sc_stop();
	1135	sc_start(sc_core::sc_time(0, SC_NS));
	1136	}
	1137	return ret;
	1138	} catch (std::exception &e) {
	1139	std::cout << e.what() << std::endl;
	1140	}
	1141	catch (...) {
	1142	std::cout << "Unknown exception occured" << std::endl;
	1143	throw;
	1144	}
	1145	return 1;
[344]	1146	}
	1147
	1148
	1149	// Local Variables:
[1048]	1150	// tab-width: 4
	1151	// c-basic-offset: 4
[344]	1152	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	1153	// indent-tabs-mode: nil
	1154	// End:
	1155
[1048]	1156	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/platforms/tsar_generic_xbar/top.cpp @ 1048

Download in other formats: