Changeset 119 for trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
- Timestamp:
- Dec 6, 2010, 6:12:46 AM (13 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r88 r119 68 68 ICACHE_TLB1_READ, // 02 69 69 ICACHE_TLB1_WRITE, // 03 70 ICACHE_TLB1_UPDT, // 04 71 ICACHE_TLB2_READ, // 05 72 ICACHE_TLB2_WRITE, // 06 73 ICACHE_TLB2_UPDT, // 07 74 ICACHE_SW_FLUSH, // 08 75 ICACHE_TLB_FLUSH, // 09 76 ICACHE_CACHE_FLUSH, // 0a 77 ICACHE_TLB_INVAL, // 0b 78 ICACHE_CACHE_INVAL, // 0c 79 ICACHE_CACHE_INVAL_PA, // 0d 80 ICACHE_MISS_WAIT, // 0e 81 ICACHE_UNC_WAIT, // 0f 82 ICACHE_MISS_UPDT, // 10 83 ICACHE_ERROR, // 11 84 ICACHE_CC_INVAL, // 12 85 ICACHE_TLB_CC_INVAL, // 13 70 ICACHE_TLB1_UPDT_SEL, // 04 71 ICACHE_TLB1_UPDT, // 05 72 ICACHE_TLB2_READ, // 06 73 ICACHE_TLB2_WRITE, // 07 74 ICACHE_TLB2_UPDT_SEL, // 08 75 ICACHE_TLB2_UPDT, // 09 76 ICACHE_SW_FLUSH, // 0a 77 ICACHE_TLB_FLUSH, // 0b 78 ICACHE_CACHE_FLUSH, // 0c 79 ICACHE_TLB_INVAL, // 0d 80 ICACHE_CACHE_INVAL, // 0e 81 ICACHE_CACHE_INVAL_PA, // 0f 82 ICACHE_MISS_WAIT, // 10 83 ICACHE_UNC_WAIT, // 11 84 ICACHE_MISS_UPDT, // 12 85 ICACHE_ERROR, // 13 86 ICACHE_CC_INVAL, // 14 87 ICACHE_TLB_CC_INVAL, // 15 86 88 }; 87 89 … … 94 96 DCACHE_TLB1_READ, // 05 95 97 DCACHE_TLB1_READ_UPDT, // 06 96 DCACHE_TLB1_UPDT, // 07 97 DCACHE_DTLB2_READ_CACHE, // 08 98 DCACHE_TLB2_LL_WAIT, // 09 99 DCACHE_TLB2_SC_WAIT, // 0a 100 DCACHE_TLB2_READ, // 0b 101 DCACHE_TLB2_READ_UPDT, // 0c 102 DCACHE_TLB2_UPDT, // 0d 103 DCACHE_CTXT_SWITCH, // 0e 104 DCACHE_ICACHE_FLUSH, // 0f 105 DCACHE_DCACHE_FLUSH, // 10 106 DCACHE_ITLB_INVAL, // 11 107 DCACHE_DTLB_INVAL, // 12 108 DCACHE_ICACHE_INVAL, // 13 109 DCACHE_DCACHE_INVAL, // 14 110 DCACHE_ICACHE_INVAL_PA, // 15 111 DCACHE_DCACHE_INVAL_PA, // 16 112 DCACHE_DCACHE_SYNC, // 17 113 DCACHE_LL_DIRTY_WAIT, // 18 114 DCACHE_SC_DIRTY_WAIT, // 19 115 DCACHE_WRITE_UPDT, // 1a 116 DCACHE_WRITE_DIRTY, // 1b 117 DCACHE_WRITE_REQ, // 1c 118 DCACHE_MISS_WAIT, // 1d 119 DCACHE_MISS_UPDT, // 1e 120 DCACHE_UNC_WAIT, // 1f 121 DCACHE_ERROR, // 20 122 DCACHE_ITLB_READ, // 21 123 DCACHE_ITLB_UPDT, // 22 124 DCACHE_ITLB_LL_WAIT, // 23 125 DCACHE_ITLB_SC_WAIT, // 24 126 DCACHE_CC_CHECK, // 25 127 DCACHE_CC_INVAL, // 26 128 DCACHE_CC_UPDT, // 27 129 DCACHE_CC_NOP, // 28 130 DCACHE_TLB_CC_INVAL, // 29 131 DCACHE_ITLB_CLEANUP, // 2a 98 DCACHE_TLB1_UPDT_SEL, // 07 99 DCACHE_TLB1_UPDT, // 08 100 DCACHE_DTLB2_READ_CACHE, // 09 101 DCACHE_TLB2_LL_WAIT, // 0a 102 DCACHE_TLB2_SC_WAIT, // 0b 103 DCACHE_TLB2_READ, // 0c 104 DCACHE_TLB2_READ_UPDT, // 0d 105 DCACHE_TLB2_UPDT_SEL, // 0e 106 DCACHE_TLB2_UPDT, // 0f 107 DCACHE_CTXT_SWITCH, // 10 108 DCACHE_ICACHE_FLUSH, // 11 109 DCACHE_DCACHE_FLUSH, // 12 110 DCACHE_ITLB_INVAL, // 13 111 DCACHE_DTLB_INVAL, // 14 112 DCACHE_ICACHE_INVAL, // 15 113 DCACHE_DCACHE_INVAL, // 16 114 DCACHE_ICACHE_INVAL_PA, // 17 115 DCACHE_DCACHE_INVAL_PA, // 18 116 DCACHE_DCACHE_SYNC, // 19 117 DCACHE_LL_DIRTY_WAIT, // 1a 118 DCACHE_SC_DIRTY_WAIT, // 1b 119 DCACHE_WRITE_UPDT, // 1c 120 DCACHE_WRITE_DIRTY, // 1d 121 DCACHE_WRITE_REQ, // 1e 122 DCACHE_MISS_WAIT, // 1f 123 DCACHE_MISS_UPDT, // 20 124 DCACHE_UNC_WAIT, // 21 125 DCACHE_ERROR, // 22 126 DCACHE_ITLB_READ, // 23 127 DCACHE_ITLB_UPDT, // 24 128 DCACHE_ITLB_LL_WAIT, // 25 129 DCACHE_ITLB_SC_WAIT, // 26 130 DCACHE_CC_CHECK, // 27 131 DCACHE_CC_INVAL, // 28 132 DCACHE_CC_UPDT, // 29 133 DCACHE_CC_NOP, // 2a 134 DCACHE_TLB_CC_INVAL, // 2b 135 DCACHE_ITLB_CLEANUP, // 2c 132 136 }; 133 137
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