Changeset 184 for trunk/modules/vci_mem_cache_v4/caba/source/include
- Timestamp:
- Jan 7, 2012, 7:17:34 PM (12 years ago)
- Location:
- trunk/modules/vci_mem_cache_v4/caba/source/include
- Files:
-
- 3 edited
-
update_tab_v4.h (modified) (3 diffs)
-
vci_mem_cache_v4.h (modified) (16 diffs)
-
xram_transaction_v4.h (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h
r2 r184 47 47 size_t i_count) 48 48 { 49 valid 50 update 49 valid = i_valid; 50 update = i_update; 51 51 brdcast = i_brdcast; 52 52 rsp = i_rsp; 53 srcid 54 trdid 55 pktid 56 nline 57 count 53 srcid = i_srcid; 54 trdid = i_trdid; 55 pktid = i_pktid; 56 nline = i_nline; 57 count = i_count; 58 58 } 59 59 … … 156 156 157 157 //////////////////////////////////////////////////////////////////// 158 // The size() function returns the size of the tab158 // The print() function diplays the tab content 159 159 //////////////////////////////////////////////////////////////////// 160 160 void print(){ … … 262 262 263 263 ///////////////////////////////////////////////////////////////////// 264 // The is_not_empty() function returns true if the table is not empty 265 ///////////////////////////////////////////////////////////////////// 266 bool is_not_empty() 267 { 268 for(size_t i = 0 ; i < size_tab ; i++){ 269 if(tab[i].valid){ 270 return true; 271 } 272 } 273 return false; 274 } 275 276 ///////////////////////////////////////////////////////////////////// 264 277 // The need_rsp() function returns the need of a response 265 278 // Arguments : -
trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r177 r184 80 80 TGT_CMD_IDLE, 81 81 TGT_CMD_READ, 82 TGT_CMD_READ_EOP,83 82 TGT_CMD_WRITE, 84 83 TGT_CMD_ATOMIC, … … 89 88 TGT_RSP_READ_IDLE, 90 89 TGT_RSP_WRITE_IDLE, 91 TGT_RSP_ LLSC_IDLE,90 TGT_RSP_SC_IDLE, 92 91 TGT_RSP_XRAM_IDLE, 93 92 TGT_RSP_INIT_IDLE, … … 95 94 TGT_RSP_READ, 96 95 TGT_RSP_WRITE, 97 TGT_RSP_ LLSC,96 TGT_RSP_SC, 98 97 TGT_RSP_XRAM, 99 98 TGT_RSP_INIT, … … 139 138 READ_TRT_LOCK, 140 139 READ_TRT_SET, 141 READ_ XRAM_REQ,140 READ_TRT_REQ, 142 141 }; 143 142 … … 197 196 IXR_CMD_READ_IDLE, 198 197 IXR_CMD_WRITE_IDLE, 199 IXR_CMD_ LLSC_IDLE,198 IXR_CMD_SC_IDLE, 200 199 IXR_CMD_XRAM_IDLE, 201 200 IXR_CMD_READ_NLINE, 202 201 IXR_CMD_WRITE_NLINE, 203 IXR_CMD_ LLSC_NLINE,202 IXR_CMD_SC_NLINE, 204 203 IXR_CMD_XRAM_DATA, 205 204 }; 206 205 207 /* States of the LLSC fsm */208 enum llsc_fsm_state_e{209 LLSC_IDLE,206 /* States of the SC fsm */ 207 enum sc_fsm_state_e{ 208 SC_IDLE, 210 209 SC_DIR_LOCK, 211 210 SC_DIR_HIT_READ, … … 215 214 SC_HEAP_LOCK, 216 215 SC_UPT_REQ, 217 SC_UP DATE,218 SC_TRT_ LOCK,216 SC_UPT_NEXT, 217 SC_TRT_PUT_LOCK, 219 218 SC_INVAL_LOCK, 220 219 SC_DIR_INVAL, 221 220 SC_INVAL, 222 SC_ XRAM_SEND,223 SC_RSP_FA LSE,224 SC_RSP_ TRUE,225 LLSC_TRT_LOCK,226 LLSC_TRT_SET,227 LLSC_XRAM_REQ,221 SC_TRT_PUT_REQ, 222 SC_RSP_FAIL, 223 SC_RSP_SUCCESS, 224 SC_TRT_GET_LOCK, 225 SC_TRT_GET_SET, 226 SC_TRT_GET_REQ, 228 227 }; 229 228 … … 247 246 ALLOC_DIR_READ, 248 247 ALLOC_DIR_WRITE, 249 ALLOC_DIR_ LLSC,248 ALLOC_DIR_SC, 250 249 ALLOC_DIR_CLEANUP, 251 250 ALLOC_DIR_XRAM_RSP, … … 256 255 ALLOC_TRT_READ, 257 256 ALLOC_TRT_WRITE, 258 ALLOC_TRT_ LLSC,257 ALLOC_TRT_SC, 259 258 ALLOC_TRT_XRAM_RSP, 260 259 ALLOC_TRT_IXR_RSP, … … 267 266 ALLOC_UPT_INIT_RSP, 268 267 ALLOC_UPT_CLEANUP, 269 ALLOC_UPT_ LLSC,268 ALLOC_UPT_SC, 270 269 }; 271 270 … … 274 273 ALLOC_HEAP_READ, 275 274 ALLOC_HEAP_WRITE, 276 ALLOC_HEAP_ LLSC,275 ALLOC_HEAP_SC, 277 276 ALLOC_HEAP_CLEANUP, 278 277 ALLOC_HEAP_XRAM_RSP, 279 278 }; 280 279 280 // debug variables (for each FSM) 281 size_t m_debug_start_cycle; 282 bool m_debug_ok; 283 bool m_debug_global; 284 bool m_debug_tgt_cmd_fsm; 285 bool m_debug_tgt_rsp_fsm; 286 bool m_debug_init_cmd_fsm; 287 bool m_debug_init_rsp_fsm; 288 bool m_debug_read_fsm; 289 bool m_debug_write_fsm; 290 bool m_debug_sc_fsm; 291 bool m_debug_cleanup_fsm; 292 bool m_debug_ixr_cmd_fsm; 293 bool m_debug_ixr_rsp_fsm; 294 bool m_debug_xram_rsp_fsm; 295 bool m_debug_previous_hit; 296 size_t m_debug_previous_count; 297 298 // instrumentation counters 281 299 uint32_t m_cpt_cycles; // Counter of cycles 282 300 uint32_t m_cpt_read; // Number of READ transactions … … 297 315 uint32_t m_cpt_sc; // Number of SC transactions 298 316 317 size_t m_prev_count; 318 299 319 protected: 300 320 … … 310 330 311 331 VciMemCacheV4( 312 sc_module_name name, // Instance Name 313 const soclib::common::MappingTable &mtp, // Mapping table for primary requets 314 const soclib::common::MappingTable &mtc, // Mapping table for coherence requets 315 const soclib::common::MappingTable &mtx, // Mapping table for XRAM 316 const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) 317 const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) 318 const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) 319 const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup 320 size_t nways, // Number of ways per set 321 size_t nsets, // Number of sets 322 size_t nwords, // Number of words per line 323 size_t heap_size=1024, // Size of the heap 324 size_t transaction_tab_lines=TRANSACTION_TAB_LINES,// Size of the TRT 325 size_t update_tab_lines=UPDATE_TAB_LINES // Size of the UPT 326 ); 332 sc_module_name name, // Instance Name 333 const soclib::common::MappingTable &mtp, // Mapping table for primary requets 334 const soclib::common::MappingTable &mtc, // Mapping table for coherence requets 335 const soclib::common::MappingTable &mtx, // Mapping table for XRAM 336 const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) 337 const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) 338 const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) 339 const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup 340 size_t nways, // Number of ways per set 341 size_t nsets, // Number of sets 342 size_t nwords, // Number of words per line 343 size_t heap_size=1024, // Size of the heap 344 size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT 345 size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT 346 size_t debug_start_cycle=0, 347 bool debug_ok=false); 327 348 328 349 ~VciMemCacheV4(); 329 350 330 351 void transition(); 331 332 352 void genMoore(); 333 334 353 void print_stats(); 335 336 354 void print_trace(); 355 void cache_monitor(vci_addr_t addr); 337 356 338 357 private: … … 343 362 const size_t m_ways; // Number of ways in a set 344 363 const size_t m_sets; // Number of cache sets 345 const size_t m_words; // Number of words in a line346 const size_t m_srcid_ixr; // Srcid for requests to XRAM347 const size_t m_srcid_ini; // Srcid for requests to processors364 const size_t m_words; // Number of words in a line 365 const size_t m_srcid_ixr; // Srcid for requests to XRAM 366 const size_t m_srcid_ini; // Srcid for requests to processors 348 367 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache 349 368 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache 350 369 vci_addr_t *m_coherence_table; // address(srcid) 351 370 uint32_t m_transaction_tab_lines; 352 TransactionTab m_transaction_tab; // xram transaction table371 TransactionTab m_transaction_tab; // xram transaction table 353 372 uint32_t m_update_tab_lines; 354 UpdateTab m_update_tab; // pending update & invalidate355 CacheDirectory m_cache_directory; // data cache directory356 HeapDirectory m_heap _directory; // heap directory357 358 data_t ***m_cache_data; // data array[set][way][word]373 UpdateTab m_update_tab; // pending update & invalidate 374 CacheDirectory m_cache_directory; // data cache directory 375 HeapDirectory m_heap; // heap for copies 376 377 data_t ***m_cache_data; // data array[set][way][word] 359 378 360 379 // adress masks … … 371 390 ////////////////////////////////////////////////// 372 391 sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line 392 sc_signal<size_t> xxx_count; 373 393 374 394 ////////////////////////////////////////////////// … … 392 412 GenericFifo<be_t> m_cmd_write_be_fifo; 393 413 394 // Fifo between TGT_CMD fsm and LLSC fsm395 GenericFifo<uint64_t> m_cmd_ llsc_addr_fifo;396 GenericFifo<bool> m_cmd_ llsc_eop_fifo;397 GenericFifo<size_t> m_cmd_ llsc_srcid_fifo;398 GenericFifo<size_t> m_cmd_ llsc_trdid_fifo;399 GenericFifo<size_t> m_cmd_ llsc_pktid_fifo;400 GenericFifo<data_t> m_cmd_ llsc_wdata_fifo;414 // Fifo between TGT_CMD fsm and SC fsm 415 GenericFifo<uint64_t> m_cmd_sc_addr_fifo; 416 GenericFifo<bool> m_cmd_sc_eop_fifo; 417 GenericFifo<size_t> m_cmd_sc_srcid_fifo; 418 GenericFifo<size_t> m_cmd_sc_trdid_fifo; 419 GenericFifo<size_t> m_cmd_sc_pktid_fifo; 420 GenericFifo<data_t> m_cmd_sc_wdata_fifo; 401 421 402 422 sc_signal<int> r_tgt_cmd_fsm; … … 555 575 556 576 /////////////////////////////////////////////////////// 557 // Registers controlled by LLSC fsm577 // Registers controlled by SC fsm 558 578 /////////////////////////////////////////////////////// 559 579 560 sc_signal<int> r_ llsc_fsm;// FSM state561 sc_signal<data_t> r_ llsc_wdata;// write data word562 sc_signal<data_t> *r_ llsc_rdata;// read data word563 sc_signal<uint32_t> r_ llsc_lfsr;// lfsr for random introducing564 sc_signal<size_t> r_ llsc_cpt;// size of command565 sc_signal<copy_t> r_ llsc_copy;// Srcid of the first copy566 sc_signal<copy_t> r_ llsc_copy_cache;// Srcid of the first copy567 sc_signal<bool> r_ llsc_copy_inst;// Type of the first copy568 sc_signal<size_t> r_ llsc_count;// number of copies569 sc_signal<size_t> r_ llsc_ptr;// pointer to the heap570 sc_signal<size_t> r_ llsc_next_ptr;// next pointer to the heap571 sc_signal<bool> r_ llsc_is_cnt;// is_cnt bit (in directory)572 sc_signal<bool> r_ llsc_dirty;// dirty bit (in directory)573 sc_signal<size_t> r_ llsc_way;// way in directory574 sc_signal<size_t> r_ llsc_set;// set in directory575 sc_signal<data_t> r_ llsc_tag;// cache line tag (in directory)576 sc_signal<size_t> r_ llsc_trt_index;// Transaction Table index577 sc_signal<size_t> r_ llsc_upt_index;// Update Table index578 579 // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)580 sc_signal<bool> r_ llsc_to_ixr_cmd_req;// valid request581 sc_signal<addr_t> r_ llsc_to_ixr_cmd_nline;// cache line index582 sc_signal<size_t> r_ llsc_to_ixr_cmd_trdid;// index in Transaction Table583 sc_signal<bool> r_ llsc_to_ixr_cmd_write;// write request584 sc_signal<data_t> *r_ llsc_to_ixr_cmd_data;// cache line data585 586 587 // Buffer between LLSC fsm and TGT_RSP fsm588 sc_signal<bool> r_ llsc_to_tgt_rsp_req;// valid request589 sc_signal<data_t> r_ llsc_to_tgt_rsp_data;// read data word590 sc_signal<size_t> r_ llsc_to_tgt_rsp_srcid;// Transaction srcid591 sc_signal<size_t> r_ llsc_to_tgt_rsp_trdid;// Transaction trdid592 sc_signal<size_t> r_ llsc_to_tgt_rsp_pktid;// Transaction pktid593 594 // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)595 sc_signal<bool> r_ llsc_to_init_cmd_multi_req;// valid request596 sc_signal<bool> r_ llsc_to_init_cmd_brdcast_req;// brdcast request597 sc_signal<addr_t> r_ llsc_to_init_cmd_nline;// cache line index598 sc_signal<size_t> r_ llsc_to_init_cmd_trdid;// index in Update Table599 sc_signal<data_t> r_ llsc_to_init_cmd_wdata;// data (one word)600 sc_signal<bool> r_ llsc_to_init_cmd_is_long;// it is a 64 bits SC601 sc_signal<data_t> r_ llsc_to_init_cmd_wdata_high;// data high (one word)602 sc_signal<size_t> r_ llsc_to_init_cmd_index;// index of the word in line603 GenericFifo<bool> m_ llsc_to_init_cmd_inst_fifo;// fifo for the L1 type604 GenericFifo<size_t> m_ llsc_to_init_cmd_srcid_fifo;// fifo for srcids605 GenericFifo<size_t> m_ llsc_to_init_cmd_cache_id_fifo;// fifo for srcids606 607 // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)608 sc_signal<bool> r_ llsc_to_init_rsp_req;// valid request609 sc_signal<size_t> r_ llsc_to_init_rsp_upt_index;// index in update table580 sc_signal<int> r_sc_fsm; // FSM state 581 sc_signal<data_t> r_sc_wdata; // write data word 582 sc_signal<data_t> *r_sc_rdata; // read data word 583 sc_signal<uint32_t> r_sc_lfsr; // lfsr for random introducing 584 sc_signal<size_t> r_sc_cpt; // size of command 585 sc_signal<copy_t> r_sc_copy; // Srcid of the first copy 586 sc_signal<copy_t> r_sc_copy_cache; // Srcid of the first copy 587 sc_signal<bool> r_sc_copy_inst; // Type of the first copy 588 sc_signal<size_t> r_sc_count; // number of copies 589 sc_signal<size_t> r_sc_ptr; // pointer to the heap 590 sc_signal<size_t> r_sc_next_ptr; // next pointer to the heap 591 sc_signal<bool> r_sc_is_cnt; // is_cnt bit (in directory) 592 sc_signal<bool> r_sc_dirty; // dirty bit (in directory) 593 sc_signal<size_t> r_sc_way; // way in directory 594 sc_signal<size_t> r_sc_set; // set in directory 595 sc_signal<data_t> r_sc_tag; // cache line tag (in directory) 596 sc_signal<size_t> r_sc_trt_index; // Transaction Table index 597 sc_signal<size_t> r_sc_upt_index; // Update Table index 598 599 // Buffer between SC fsm and INIT_CMD fsm (XRAM read) 600 sc_signal<bool> r_sc_to_ixr_cmd_req; // valid request 601 sc_signal<addr_t> r_sc_to_ixr_cmd_nline; // cache line index 602 sc_signal<size_t> r_sc_to_ixr_cmd_trdid; // index in Transaction Table 603 sc_signal<bool> r_sc_to_ixr_cmd_write; // write request 604 sc_signal<data_t> *r_sc_to_ixr_cmd_data; // cache line data 605 606 607 // Buffer between SC fsm and TGT_RSP fsm 608 sc_signal<bool> r_sc_to_tgt_rsp_req; // valid request 609 sc_signal<data_t> r_sc_to_tgt_rsp_data; // read data word 610 sc_signal<size_t> r_sc_to_tgt_rsp_srcid; // Transaction srcid 611 sc_signal<size_t> r_sc_to_tgt_rsp_trdid; // Transaction trdid 612 sc_signal<size_t> r_sc_to_tgt_rsp_pktid; // Transaction pktid 613 614 // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) 615 sc_signal<bool> r_sc_to_init_cmd_multi_req; // valid request 616 sc_signal<bool> r_sc_to_init_cmd_brdcast_req; // brdcast request 617 sc_signal<addr_t> r_sc_to_init_cmd_nline; // cache line index 618 sc_signal<size_t> r_sc_to_init_cmd_trdid; // index in Update Table 619 sc_signal<data_t> r_sc_to_init_cmd_wdata; // data (one word) 620 sc_signal<bool> r_sc_to_init_cmd_is_long; // it is a 64 bits SC 621 sc_signal<data_t> r_sc_to_init_cmd_wdata_high; // data high (one word) 622 sc_signal<size_t> r_sc_to_init_cmd_index; // index of the word in line 623 GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type 624 GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids 625 GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids 626 627 // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry) 628 sc_signal<bool> r_sc_to_init_rsp_req; // valid request 629 sc_signal<size_t> r_sc_to_init_rsp_upt_index; // index in update table 610 630 611 631 //////////////////////////////////////////////////// -
trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h
r138 r184 14 14 15 15 class TransactionTabEntry { 16 typedef uint32_t size_t;17 typedef uint32_t data_t;18 typedef sc_dt::sc_uint<40> addr_t;19 typedef uint32_t be_t;16 typedef uint32_t size_t; 17 typedef uint32_t data_t; 18 typedef sc_dt::sc_uint<40> addr_t; 19 typedef uint32_t be_t; 20 20 21 21 public: 22 bool valid; // entry valid23 bool xram_read; // read request to XRAM24 addr_t nline; // index (zy) of the requested line25 size_t srcid; // processor requesting the transaction26 size_t trdid; // processor requesting the transaction27 size_t pktid; // processor requesting the transaction28 bool proc_read; // read request from processor29 size_t read_length;// length of the read (for the response)30 size_t word_index; // index of the first read word (for the response)31 std::vector<data_t> wdata;// write buffer (one cache line)32 std::vector<be_t> wdata_be; // be for each data in the write buffer33 bool rerror;// error returned by xram22 bool valid; // entry valid 23 bool xram_read; // read request to XRAM 24 addr_t nline; // index (zy) of the requested line 25 size_t srcid; // processor requesting the transaction 26 size_t trdid; // processor requesting the transaction 27 size_t pktid; // processor requesting the transaction 28 bool proc_read; // read request from processor 29 size_t read_length; // length of the read (for the response) 30 size_t word_index; // index of the first read word (for the response) 31 std::vector<data_t> wdata; // write buffer (one cache line) 32 std::vector<be_t> wdata_be; // be for each data in the write buffer 33 bool rerror; // error returned by xram 34 34 35 35 ///////////////////////////////////////////////////////////////////// … … 39 39 { 40 40 valid = false; 41 rerror = false; 41 42 } 42 43 … … 50 51 wdata_be.reserve( (int)n_words ); 51 52 wdata.reserve( (int)n_words ); 52 for(size_t i=0; i<n_words; i++){ 53 wdata_be.push_back(false); 53 for(size_t i=0; i<n_words; i++) 54 { 55 wdata_be.push_back(0); 54 56 wdata.push_back(0); 55 57 } … … 352 354 tab[index].read_length = read_length; 353 355 tab[index].word_index = word_index; 354 for(size_t i=0; i<tab[index].wdata.size(); i++) { 356 for(size_t i=0; i<tab[index].wdata.size(); i++) 357 { 355 358 tab[index].wdata_be[i] = data_be[i]; 356 359 tab[index].wdata[i] = data[i]; … … 361 364 // The write_rsp() function writes a word of the response to an 362 365 // XRAM read transaction. 363 // The data is only written when the corresponding BE field is Ox0.366 // The BE field in TRT is taken into account. 364 367 // Arguments : 365 368 // - index : the index of the transaction in the transaction tab 366 369 // - word_index : the index of the data in the line 367 370 // - data : the data to write 371 // - error : invalid data 368 372 ///////////////////////////////////////////////////////////////////// 369 373 void write_rsp(const size_t index, … … 396 400 && "The selected entry is out of range in erase() Transaction Tab"); 397 401 tab[index].valid = false; 402 tab[index].rerror = false; 398 403 } 399 404 }; // end class TransactionTab
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