Changeset 205 for trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h
- Timestamp:
- Mar 11, 2012, 6:42:17 PM (12 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h
r204 r205 100 100 DCACHE_TLB_PTE2_SELECT, 101 101 DCACHE_TLB_PTE2_UPDT, 102 DCACHE_TLB_ SC_UPDT,103 DCACHE_TLB_ SC_WAIT,102 DCACHE_TLB_LR_UPDT, 103 DCACHE_TLB_LR_WAIT, 104 104 DCACHE_TLB_RETURN, 105 105 // handling processor XTN requests … … 116 116 DCACHE_XTN_DC_INVAL_GO, 117 117 DCACHE_XTN_DT_INVAL, 118 //handling fourth stage write119 DCACHE_ WRITE_TLB_DIRTY,120 DCACHE_ WRITE_CACHE_DIRTY,121 DCACHE_ WRITE_SC_WAIT,122 DCACHE_ WRITE_UNC_WAIT,118 //handling long write (set dirty bit) 119 DCACHE_DIRTY_TLB_SET, 120 DCACHE_DIRTY_CACHE_SET, 121 DCACHE_DIRTY_SC_WAIT, 122 DCACHE_DIRTY_UNC_WAIT, 123 123 // handling processor miss requests 124 124 DCACHE_MISS_VICTIM, … … 129 129 // handling processor unc and sc requests 130 130 DCACHE_UNC_WAIT, 131 DCACHE_SC_WAIT, 131 132 // handling coherence requests 132 133 DCACHE_CC_CHECK, … … 263 264 264 265 //////////////////////////////////////// 265 // Variables used by print_trace()266 // Communication with processor ISS 266 267 //////////////////////////////////////// 267 268 bool m_ireq_valid; 269 uint32_t m_ireq_addr; 270 soclib::common::Iss2::ExecMode m_ireq_mode; 271 272 bool m_irsp_valid; 273 uint32_t m_irsp_instruction; 274 bool m_irsp_error; 275 276 bool m_dreq_valid; 277 uint32_t m_dreq_addr; 278 soclib::common::Iss2::ExecMode m_dreq_mode; 279 soclib::common::Iss2::DataOperationType m_dreq_type; 280 uint32_t m_dreq_wdata; 281 uint8_t m_dreq_be; 282 283 bool m_drsp_valid; 284 uint32_t m_drsp_rdata; 285 bool m_drsp_error; 268 typename iss_t::InstructionRequest m_ireq; 269 typename iss_t::InstructionResponse m_irsp; 270 typename iss_t::DataRequest m_dreq; 271 typename iss_t::DataResponse m_drsp; 286 272 287 273 ///////////////////////////////////////////// … … 379 365 sc_signal<bool> r_dcache_p1_tlb_big; // big page bit (from dtlb) 380 366 // registers written in P2 stage (used in long write) 381 sc_signal<uint32_t> r_dcache_p2_vaddr; // virtual address (from proc) 382 sc_signal<size_t> r_dcache_p2_tlb_way; // selected way in dtlb 383 sc_signal<size_t> r_dcache_p2_tlb_set; // selected set in dtlb 384 sc_signal<bool> r_dcache_p2_set_dirty; // PTE dirty bit must be set 367 sc_signal<size_t> r_dcache_p2_way; // selected way in dtlb or dcache 368 sc_signal<size_t> r_dcache_p2_set; // selected set in dtlb or dcache 369 sc_signal<size_t> r_dcache_p2_word; // selected word in dcache 385 370 sc_signal<paddr_t> r_dcache_p2_pte_paddr; // PTE physical address 386 sc_signal<size_t> r_dcache_p2_pte_way; // selected way in dcache 387 sc_signal<size_t> r_dcache_p2_pte_set; // selected set in dcache 388 sc_signal<size_t> r_dcache_p2_pte_word; // selected word in dcache 389 sc_signal<size_t> r_dcache_p2_pte; // pte value read in dcache 371 sc_signal<size_t> r_dcache_p2_pte_value; // PTE value 372 sc_signal<bool> r_dcache_p2_type_sc; // request type (WRITE or SC) 373 sc_signal<bool> r_dcache_p2_sc_success; // successful SC request 390 374 391 375 // communication between DCACHE FSM and VCI_CMD FSM … … 406 390 407 391 // handling dcache miss 408 sc_signal<int> r_dcache_miss_type;// type of miss depending on the requester392 sc_signal<int> r_dcache_miss_type; // type of miss depending on the requester 409 393 sc_signal<size_t> r_dcache_miss_word; // word index for sequencial cache update 410 394 sc_signal<size_t> r_dcache_miss_way; // selected way for cache update
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