Changeset 253


Ignore:
Timestamp:
Aug 16, 2012, 2:41:27 PM (12 years ago)
Author:
meunier
Message:

Added the display of the name of the component in the vci_cc_vcache_v4 and
the vci_mem_cache_v4 in the debug traces.

Location:
trunk/modules
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

    r251 r253  
    20422042if ( m_debug_dcache_fsm )
    20432043{
    2044     std::cout << "  <PROC.DCACHE_IDLE> Cache update in P2 stage" << std::dec
     2044    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> Cache update in P2 stage" << std::dec
    20452045              << " / WAY = " << way
    20462046              << " / SET = " << set
    … …  
    24902490if ( m_debug_dcache_fsm )
    24912491{
    2492     std::cout << "  <PROC.DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
     2492    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
    24932493}
    24942494#endif
    … …  
    25062506if ( m_debug_dcache_fsm )
    25072507{
    2508     std::cout << "  <PROC.DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
     2508    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
    25092509}
    25102510#endif
    … …  
    25552555if ( m_debug_dcache_fsm )
    25562556{
    2557     std::cout << "  <PROC.DCACHE_IDLE> Speculative access miss" << std::endl;
     2557    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> Speculative access miss" << std::endl;
    25582558}
    25592559#endif
    … …  
    25892589if ( m_debug_dcache_fsm )
    25902590{
    2591     std::cout << "  <PROC.DCACHE_IDLE> HIT in dcache" << std::endl;
     2591    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dcache" << std::endl;
    25922592}
    25932593#endif
    … …  
    27772777    if ( r_dcache_tlb_ins.read() )
    27782778    {
    2779         std::cout << "  <PROC.DCACHE_TLB_MISS> ITLB miss";
     2779        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
    27802780    }
    27812781    else
    27822782    {                           
    2783         std::cout << "  <PROC.DCACHE_TLB_MISS> DTLB miss";
     2783        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
    27842784    }
    27852785    std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
    … …  
    28312831if ( m_debug_dcache_fsm )
    28322832{
    2833     std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
     2833    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
    28342834              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
    28352835              << std::dec << " / way = " << way
    … …  
    28662866if ( m_debug_dcache_fsm )
    28672867{
    2868     std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
     2868    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
    28692869              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
    28702870              << std::dec << " / way = " << way
    … …  
    28872887if ( m_debug_dcache_fsm )
    28882888{
    2889     std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> HIT in dcache"
     2889    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
    28902890              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
    28912891              << std::dec << " / way = " << way
    … …  
    29072907if ( m_debug_dcache_fsm )
    29082908{
    2909     std::cout << "  <PROC.DCACHE_TLB_PTE1_GET> MISS in dcache:"
     2909    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
    29102910              << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
    29112911}
    … …  
    29482948{
    29492949    if ( r_dcache_tlb_ins.read() )
    2950         std::cout << "  <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
     2950        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
    29512951    else                           
    2952         std::cout << "  <PROC.DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
     2952        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
    29532953        std::cout << " way = " << std::dec << way
    29542954                  << " / set = " << set << std::endl;
    … …  
    30333033    if ( r_dcache_tlb_ins.read() )
    30343034    {
    3035         std::cout << "  <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
     3035        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
    30363036        std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
    30373037                  << " / way = " << r_dcache_tlb_way.read() << std::endl;
    … …  
    30403040    else                           
    30413041    {
    3042         std::cout << "  <PROC.DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
     3042        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
    30433043        std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
    30443044                  << " / way = " << r_dcache_tlb_way.read() << std::endl;
    … …  
    30923092if ( m_debug_dcache_fsm )
    30933093{
    3094     std::cout << "  <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
     3094    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
    30953095              << " PTE_FLAGS = " << std::hex << pte_flags
    30963096              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
    … …  
    31113111if ( m_debug_dcache_fsm )
    31123112{
    3113     std::cout << "  <PROC.DCACHE_TLB_PTE2_GET> HIT in dcache:"
     3113    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
    31143114              << " PTE_FLAGS = " << std::hex << pte_flags
    31153115              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
    … …  
    31283128if ( m_debug_dcache_fsm )
    31293129{
    3130     std::cout << "  <PROC.DCACHE_TLB_PTE2_GET> MISS in dcache:"
     3130    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> MISS in dcache:"
    31313131              << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
    31323132}
    … …  
    31663166{
    31673167    if ( r_dcache_tlb_ins.read() )
    3168         std::cout << "  <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
     3168        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
    31693169    else                           
    3170         std::cout << "  <PROC.DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
     3170        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
    31713171        std::cout << " way = " << std::dec << way
    31723172                  << " / set = " << set << std::endl;
    … …  
    32523252    if ( r_dcache_tlb_ins.read() )
    32533253    {
    3254         std::cout << "  <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
     3254        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
    32553255        std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
    32563256                  << " / way = " << r_dcache_tlb_way.read() << std::endl;
    … …  
    32593259    else                           
    32603260    {
    3261         std::cout << "  <PROC.DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
     3261        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
    32623262        std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
    32633263                  << " / way = " << r_dcache_tlb_way.read() << std::endl;
    … …  
    32783278if ( m_debug_dcache_fsm )
    32793279{
    3280     std::cout << "  <PROC.DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
     3280    std::cout << "  <PROC " << name() << ".DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
    32813281}
    32823282#endif
    … …  
    33233323if ( m_debug_dcache_fsm )
    33243324{
    3325     std::cout << "  <PROC.DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
     3325    std::cout << "  <PROC " << name() << ".DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
    33263326}
    33273327#endif
    … …  
    33373337if ( m_debug_dcache_fsm )
    33383338{
    3339     std::cout << "  <PROC.DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
     3339    std::cout << "  <PROC " << name() << ".DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
    33403340}
    33413341#endif
    … …  
    34923492if ( m_debug_dcache_fsm )
    34933493{
    3494     std::cout << "  <PROC.DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
     3494    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
    34953495              << " / VADDR = " << r_dcache_p0_wdata.read()
    34963496              << " / PADDR = " << paddr << std::endl;
    … …  
    35333533if ( m_debug_dcache_fsm )
    35343534{
    3535     std::cout << "  <PROC.DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
     3535    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
    35363536              << " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
    35373537              << " / HIT = " << hit
    … …  
    35893589if ( m_debug_dcache_fsm )
    35903590{
    3591     std::cout << "  <PROC.DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
     3591    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
    35923592              << " / NLINE = " << nline << std::endl;
    35933593}
    … …  
    36383638if ( m_debug_dcache_fsm )
    36393639{
    3640     std::cout << "  <PROC.DCACHE_MISS_VICTIM> Select a slot:" << std::dec
     3640    std::cout << "  <PROC " << name() << ".DCACHE_MISS_VICTIM> Select a slot:" << std::dec
    36413641              << " / WAY = "   << way
    36423642              << " / SET = "   << set
    … …  
    36663666if ( m_debug_dcache_fsm )
    36673667{
    3668     std::cout << "  <PROC.DCACHE_MISS_INVAL> inval line:" << std::dec
     3668    std::cout << "  <PROC " << name() << ".DCACHE_MISS_INVAL> inval line:" << std::dec
    36693669              << " / way = "   << way
    36703670              << " / set = "   << set
    … …  
    38443844        if ( r_dcache_miss_word.read() < m_dcache_words-1 )
    38453845        {
    3846             std::cout << "  <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
     3846            std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
    38473847                      << "  pop the FIFO, don't update the cache" << std::endl;
    38483848        }
    38493849        else
    38503850        {
    3851             std::cout << "  <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
     3851            std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
    38523852                      << " last word : send a cleanup request " << std::endl;
    38533853        }
    … …  
    38553855    else
    38563856    {
    3857         std::cout << "  <PROC.DCACHE_MISS_UPDT> Write one word:"
     3857        std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Write one word:"
    38583858                  << " address = " << std::hex << r_dcache_vci_paddr.read()
    38593859                  << " / data = "  << r_vci_rsp_fifo_dcache.read()
    … …  
    39773977if ( m_debug_dcache_fsm )
    39783978{
    3979     std::cout << "  <PROC.DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
     3979    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
    39803980              << " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
    39813981              << " / PTE_VALUE = " << pte << std::dec
    … …  
    40164016if ( m_debug_dcache_fsm )
    40174017{
    4018     std::cout << "  <PROC.DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
     4018    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"
    40194019              << std::endl;
    40204020}
    … …  
    40274027if ( m_debug_dcache_fsm )
    40284028{
    4029     std::cout << "  <PROC.DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
     4029    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"
    40304030              << std::endl;
    40314031}
    … …  
    40934093if ( m_debug_dcache_fsm )
    40944094{
    4095     std::cout << "  <PROC.DCACHE_CC_CHECK> Coherence request matching a pending miss:"
     4095    std::cout << "  <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request matching a pending miss:"
    40964096              << " address = " << std::hex << paddr << std::endl;
    40974097}
    … …  
    41384138{
    41394139   
    4140     std::cout << "  <PROC.DCACHE_CC_CHECK> Coherence request received :"
     4140    std::cout << "  <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request received :"
    41414141              << " address = " << std::hex << paddr << std::dec;
    41424142    if ( hit )
    … …  
    41894189if ( m_debug_dcache_fsm )
    41904190{
    4191     std::cout << "  <PROC.DCACHE_CC_INVAL> Invalidate cache line" << std::dec
     4191    std::cout << "  <PROC " << name() << ".DCACHE_CC_INVAL> Invalidate cache line" << std::dec
    41924192              << " / WAY = " << way
    41934193              << " / SET = " << set << std::endl;
    … …  
    42384238if ( m_debug_dcache_fsm )
    42394239{
    4240     std::cout << "  <PROC.DCACHE_CC_UPDT> Update one word" << std::dec
     4240    std::cout << "  <PROC " << name() << ".DCACHE_CC_UPDT> Update one word" << std::dec
    42414241              << " / WAY = " << way
    42424242              << " / SET = " << set
    … …  
    42834283if ( m_debug_dcache_fsm and ok )
    42844284{
    4285     std::cout << "  <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
     4285    std::cout << "  <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
    42864286              << " line = " << line << std::dec
    42874287              << " / set = " << set
    … …  
    42964296if ( m_debug_dcache_fsm and ok )
    42974297{
    4298     std::cout << "  <PROC.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
     4298    std::cout << "  <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
    42994299              << " line = " << line << std::dec
    43004300              << " / set = " << set
    … …  
    43284328            std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
    43294329                      << " stop at cycle " << m_cpt_total_cycles << std::endl
    4330                       << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
    4331                       << std::endl;
     4330                      << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles << std::endl;
     4331                      r_iss.dump();
    43324332            exit(1);
    43334333        }
    … …  
    47674767if ( m_debug_cleanup_fsm )
    47684768{
    4769     std::cout << "  <PROC.CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
     4769    std::cout << "  <PROC " << name() << ".CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
    47704770              << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4)
    47714771              << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
    … …  
    47864786if ( m_debug_cleanup_fsm )
    47874787{
    4788     std::cout << "  <PROC.CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
     4788    std::cout << "  <PROC " << name() << ".CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
    47894789              << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4)
    47904790              << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;

  • trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h

    r184 r253  
    11#ifndef XRAM_TRANSACTION_V4_H_
    22#define XRAM_TRANSACTION_V4_H_
    3  
     3
    44#include <inttypes.h>
    55#include <systemc>
    … …  
    1414
    1515class TransactionTabEntry {
    16   typedef uint32_t              size_t;
    17   typedef uint32_t              data_t;
    18   typedef sc_dt::sc_uint<40>    addr_t;
    19   typedef uint32_t              be_t;
    20 
    21  public:
    22   bool                      valid;          // entry valid
    23   bool                      xram_read;      // read request to XRAM
    24   addr_t                    nline;          // index (zy) of the requested line
    25   size_t                    srcid;          // processor requesting the transaction
    26   size_t                    trdid;          // processor requesting the transaction
    27   size_t                    pktid;          // processor requesting the transaction
    28   bool                      proc_read;      // read request from processor
    29   size_t                    read_length;    // length of the read (for the response)
    30   size_t                    word_index;         // index of the first read word (for the response)
    31   std::vector<data_t>  wdata;          // write buffer (one cache line)
    32   std::vector<be_t>     wdata_be;       // be for each data in the write buffer
    33   bool                  rerror;         // error returned by xram
    34 
    35   /////////////////////////////////////////////////////////////////////
    36   // The init() function initializes the entry
    37   /////////////////////////////////////////////////////////////////////
    38   void init()
    39   {
    40     valid               = false;
    41     rerror      = false;
    42   }
    43 
    44   /////////////////////////////////////////////////////////////////////
    45   // The alloc() function initializes the vectors of an entry
    46   // Its arguments are :
    47   // - n_words : number of words per line in the cache
    48   /////////////////////////////////////////////////////////////////////
    49   void alloc(size_t n_words)
    50   {
    51     wdata_be.reserve( (int)n_words );
    52     wdata.reserve( (int)n_words );
    53     for(size_t i=0; i<n_words; i++)
    54     {
    55       wdata_be.push_back(0);
    56       wdata.push_back(0);
    57     }
    58   }
    59 
    60   ////////////////////////////////////////////////////////////////////
    61   // The copy() function copies an existing entry
    62   // Its arguments are :
    63   // - source : the transaction tab entry to copy
    64   ////////////////////////////////////////////////////////////////////
    65   void copy(const TransactionTabEntry &source)
    66   {
    67     valid           = source.valid;
    68     xram_read   = source.xram_read;
    69     nline           = source.nline;
    70     srcid           = source.srcid;
    71     trdid           = source.trdid;
    72     pktid           = source.pktid;
    73     proc_read   = source.proc_read;
    74     read_length = source.read_length;
    75     word_index  = source.word_index;
    76     wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
    77     wdata.assign(source.wdata.begin(),source.wdata.end());
    78     rerror      = source.rerror;
    79   }
    80 
    81   ////////////////////////////////////////////////////////////////////
    82   // The print() function prints the entry
    83   ////////////////////////////////////////////////////////////////////
    84   void print(){
    85     std::cout << "valid       = " << valid        << std::endl;
    86     std::cout << "xram_read   = " << xram_read    << std::endl;
    87     std::cout << "nline       = " << std::hex << nline << std::endl;
    88     std::cout << "srcid       = " << srcid        << std::endl;
    89     std::cout << "trdid       = " << trdid        << std::endl;
    90     std::cout << "pktid       = " << pktid        << std::endl;
    91     std::cout << "proc_read   = " << proc_read    << std::endl;
    92     std::cout << "read_length = " << read_length  << std::endl;
    93     std::cout << "word_index  = " << word_index   << std::endl;
    94     for(size_t i=0; i<wdata_be.size() ; i++){
    95       std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
    96     }
    97     for(size_t i=0; i<wdata.size() ; i++){
    98       std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
    99     }
    100     std::cout << std::endl;
    101     std::cout << "rerror      = " << rerror       << std::endl;
    102   }
    103 
    104   /////////////////////////////////////////////////////////////////////
    105   //            Constructors
    106   /////////////////////////////////////////////////////////////////////
    107 
    108   TransactionTabEntry()
    109     {
    110       wdata_be.clear();
    111       wdata.clear();
    112       valid=false;
    113       rerror=false;
    114     }
    115 
    116   TransactionTabEntry(const TransactionTabEntry &source){
    117     valid           = source.valid;
    118     xram_read   = source.xram_read;
    119     nline           = source.nline;
    120     srcid           = source.srcid;
    121     trdid           = source.trdid;
    122     pktid           = source.pktid;
    123     proc_read   = source.proc_read;
    124     read_length = source.read_length;
    125     word_index  = source.word_index;
    126     wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
    127     wdata.assign(source.wdata.begin(),source.wdata.end());     
    128     rerror      = source.rerror;
    129   }
     16    typedef uint32_t              size_t;
     17    typedef uint32_t              data_t;
     18    typedef sc_dt::sc_uint<40>    addr_t;
     19    typedef uint32_t              be_t;
     20
     21    public:
     22    bool                        valid;              // entry valid
     23    bool                        xram_read;          // read request to XRAM
     24    addr_t              nline;              // index (zy) of the requested line
     25    size_t                  srcid;          // processor requesting the transaction
     26    size_t                  trdid;          // processor requesting the transaction
     27    size_t                  pktid;          // processor requesting the transaction
     28    bool                        proc_read;          // read request from processor
     29    size_t                  read_length;    // length of the read (for the response)
     30    size_t                  word_index;         // index of the first read word (for the response)
     31    std::vector<data_t> wdata;          // write buffer (one cache line)
     32    std::vector<be_t>   wdata_be;       // be for each data in the write buffer
     33    bool                rerror;         // error returned by xram
     34
     35    /////////////////////////////////////////////////////////////////////
     36    // The init() function initializes the entry
     37    /////////////////////////////////////////////////////////////////////
     38    void init()
     39    {
     40        valid           = false;
     41        rerror      = false;
     42    }
     43
     44    /////////////////////////////////////////////////////////////////////
     45    // The alloc() function initializes the vectors of an entry
     46    // Its arguments are :
     47    // - n_words : number of words per line in the cache
     48    /////////////////////////////////////////////////////////////////////
     49    void alloc(size_t n_words)
     50    {
     51        wdata_be.reserve( (int)n_words );
     52        wdata.reserve( (int)n_words );
     53        for(size_t i=0; i<n_words; i++)
     54        {
     55            wdata_be.push_back(0);
     56            wdata.push_back(0);
     57        }
     58    }
     59
     60    ////////////////////////////////////////////////////////////////////
     61    // The copy() function copies an existing entry
     62    // Its arguments are :
     63    // - source : the transaction tab entry to copy
     64    ////////////////////////////////////////////////////////////////////
     65    void copy(const TransactionTabEntry &source)
     66    {
     67        valid       = source.valid;
     68        xram_read       = source.xram_read;
     69        nline       = source.nline;
     70        srcid       = source.srcid;
     71        trdid       = source.trdid;
     72        pktid       = source.pktid;
     73        proc_read       = source.proc_read;
     74        read_length = source.read_length;
     75        word_index      = source.word_index;
     76        wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
     77        wdata.assign(source.wdata.begin(),source.wdata.end());
     78        rerror      = source.rerror;
     79    }
     80
     81    ////////////////////////////////////////////////////////////////////
     82    // The print() function prints the entry
     83    ////////////////////////////////////////////////////////////////////
     84    void print(){
     85        std::cout << "valid       = " << valid        << std::endl;
     86        std::cout << "xram_read   = " << xram_read    << std::endl;
     87        std::cout << "nline       = " << std::hex << nline << std::endl;
     88        std::cout << "srcid       = " << srcid        << std::endl;
     89        std::cout << "trdid       = " << trdid        << std::endl;
     90        std::cout << "pktid       = " << pktid        << std::endl;
     91        std::cout << "proc_read   = " << proc_read    << std::endl;
     92        std::cout << "read_length = " << read_length  << std::endl;
     93        std::cout << "word_index  = " << word_index   << std::endl;
     94        for(size_t i=0; i<wdata_be.size() ; i++){
     95            std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
     96        }
     97        for(size_t i=0; i<wdata.size() ; i++){
     98            std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
     99        }
     100        std::cout << std::endl;
     101        std::cout << "rerror      = " << rerror       << std::endl;
     102    }
     103
     104    /////////////////////////////////////////////////////////////////////
     105    //          Constructors
     106    /////////////////////////////////////////////////////////////////////
     107
     108    TransactionTabEntry()
     109    {
     110        wdata_be.clear();
     111        wdata.clear();
     112        valid=false;
     113        rerror=false;
     114    }
     115
     116    TransactionTabEntry(const TransactionTabEntry &source){
     117        valid       = source.valid;
     118        xram_read       = source.xram_read;
     119        nline       = source.nline;
     120        srcid       = source.srcid;
     121        trdid       = source.trdid;
     122        pktid       = source.pktid;
     123        proc_read       = source.proc_read;
     124        read_length = source.read_length;
     125        word_index      = source.word_index;
     126        wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
     127        wdata.assign(source.wdata.begin(),source.wdata.end()); 
     128        rerror      = source.rerror;
     129    }
    130130
    131131}; // end class TransactionTabEntry
    … …  
    135135////////////////////////////////////////////////////////////////////////
    136136class TransactionTab{
    137   typedef uint32_t size_t;
    138   typedef uint32_t data_t;
    139   typedef sc_dt::sc_uint<40> addr_t;
    140   typedef uint32_t be_t;
    141 
    142  private:
    143   size_t size_tab;                // The size of the tab
    144 
    145   data_t be_to_mask(be_t be)
    146   {
    147     data_t ret = 0;
    148     if ( be&0x1 ) {
    149       ret = ret | 0x000000FF;
    150     }
    151     if ( be&0x2 ) {
    152       ret = ret | 0x0000FF00;
    153     }
    154     if ( be&0x4 ) {
    155       ret = ret | 0x00FF0000;
    156     }
    157     if ( be&0x8 ) {
    158       ret = ret | 0xFF000000;
    159     }
    160     return ret;
    161   }
    162 
    163  public:
    164   TransactionTabEntry *tab;       // The transaction tab
    165 
    166   ////////////////////////////////////////////////////////////////////
    167   //            Constructors
    168   ////////////////////////////////////////////////////////////////////
    169   TransactionTab()
    170     {
    171       size_tab=0;
    172       tab=NULL;
    173     }
    174 
    175   TransactionTab(size_t n_entries, size_t n_words)
    176     {
    177       size_tab = n_entries;
    178       tab = new TransactionTabEntry[size_tab];
    179       for ( size_t i=0; i<size_tab; i++) {
    180         tab[i].alloc(n_words);
    181       }
    182     }
    183 
    184   ~TransactionTab()
    185     {
    186       delete [] tab;
    187     }
    188 
    189   /////////////////////////////////////////////////////////////////////
    190   // The size() function returns the size of the tab
    191   /////////////////////////////////////////////////////////////////////
    192   size_t size()
    193   {
    194     return size_tab;
    195   }
    196 
    197   /////////////////////////////////////////////////////////////////////
    198   // The init() function initializes the transaction tab entries
    199   /////////////////////////////////////////////////////////////////////
    200   void init()
    201   {
    202     for ( size_t i=0; i<size_tab; i++) {
    203       tab[i].init();
    204     }
    205   }
    206 
    207   /////////////////////////////////////////////////////////////////////
    208   // The print() function prints a transaction tab entry
    209   // Arguments :
    210   // - index : the index of the entry to print
    211   /////////////////////////////////////////////////////////////////////
    212   void print(const size_t index)
    213   {
    214     assert( (index < size_tab)
    215             && "Invalid Transaction Tab Entry");
    216     tab[index].print();
    217     return;
    218   }
    219 
    220   /////////////////////////////////////////////////////////////////////
    221   // The read() function returns a transaction tab entry.
    222   // Arguments :
    223   // - index : the index of the entry to read
    224   /////////////////////////////////////////////////////////////////////
    225   TransactionTabEntry read(const size_t index)
    226   {
    227     assert( (index < size_tab)
    228             && "Invalid Transaction Tab Entry");
    229     return tab[index];
    230   }
    231 
    232   /////////////////////////////////////////////////////////////////////
    233   // The full() function returns the state of the transaction tab
    234   // Arguments :
    235   // - index : (return argument) the index of an empty entry
    236   // The function returns true if the transaction tab is full
    237   /////////////////////////////////////////////////////////////////////
    238   bool full(size_t &index)
    239   {
    240     for(size_t i=0; i<size_tab; i++){
    241       if(!tab[i].valid){
    242             index=i;
    243             return false;       
    244       }
    245     }
    246     return true;
    247   }
    248 
    249   /////////////////////////////////////////////////////////////////////
    250   // The hit_read() function checks if an XRAM read transaction exists
    251   // for a given cache line.
    252   // Arguments :
    253   // - index : (return argument) the index of the hit entry, if there is
    254   // - nline : the index (zy) of the requested line
    255   // The function returns true if a read request has already been sent
    256   //////////////////////////////////////////////////////////////////////
    257   bool hit_read(const addr_t nline,size_t &index)
    258   {
    259     for(size_t i=0; i<size_tab; i++){
    260       if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
    261             index=i;
    262             return true;       
    263       }
    264     }
    265     return false;
    266   }
    267 
    268   ///////////////////////////////////////////////////////////////////////
    269   // The hit_write() function looks if an XRAM write transaction exists
    270   // for a given line.
    271   // Arguments :
    272   // - nline : the index (zy) of the requested line
    273   // The function returns true if a write request has already been sent
    274   ///////////////////////////////////////////////////////////////////////
    275   bool hit_write(const addr_t nline)
    276   {
    277     for(size_t i=0; i<size_tab; i++){
    278       if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
    279             return true;       
    280       }
    281     }
    282     return false;
    283   }
    284 
    285   /////////////////////////////////////////////////////////////////////
    286   // The write_data_mask() function writes a vector of data (a line).
    287   // The data is written only if the corresponding bits are set
    288   // in the be vector.
    289   // Arguments :
    290   // - index : the index of the request in the transaction tab
    291   // - be   : vector of be
    292   // - data : vector of data
    293   /////////////////////////////////////////////////////////////////////
    294   void write_data_mask(const size_t index,
    295                        const std::vector<be_t> &be,
    296                        const std::vector<data_t> &data)
    297   {
    298     assert( (index < size_tab)
    299             && "Invalid Transaction Tab Entry");
    300     assert(be.size()==tab[index].wdata_be.size()
    301            && "Bad data mask in write_data_mask in TransactionTab");
    302     assert(data.size()==tab[index].wdata.size()
    303            && "Bad data in write_data_mask in TransactionTab");
    304 
    305     for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
    306       tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
    307       data_t mask = be_to_mask(be[i]);
    308       tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
    309     }
    310   }
    311 
    312   /////////////////////////////////////////////////////////////////////
    313   // The set() function registers a transaction (read or write)
    314   // to the XRAM in the transaction tab.
    315   // Arguments :
    316   // - index : index in the transaction tab
    317   // - xram_read : transaction type (read or write a cache line)
    318   // - nline : the index (zy) of the cache line
    319   // - srcid : srcid of the initiator that caused the transaction
    320   // - trdid : trdid of the initiator that caused the transaction
    321   // - pktid : pktid of the initiator that caused the transaction
    322   // - proc_read : does the initiator want a copy
    323   // - read_length : length of read (in case of processor read)
    324   // - word_index : index in the line (in case of single word read)
    325   // - data : the data to write (in case of write)
    326   // - data_be : the mask of the data to write (in case of write)
    327   /////////////////////////////////////////////////////////////////////
    328   void set(const size_t index,
    329            const bool xram_read,
    330            const addr_t nline,
    331            const size_t srcid,
    332            const size_t trdid,
    333            const size_t pktid,
    334            const bool proc_read,
    335            const size_t read_length,
    336            const size_t word_index,
    337            const std::vector<be_t> &data_be,
    338            const std::vector<data_t> &data)
    339   {
    340     assert( (index < size_tab)
    341             && "The selected entry is out of range in set() Transaction Tab");
    342     assert(data_be.size()==tab[index].wdata_be.size()
    343            && "Bad data_be argument in set() TransactionTab");
    344     assert(data.size()==tab[index].wdata.size()
    345            && "Bad data argument in set() TransactionTab");
    346 
    347     tab[index].valid            = true;
    348     tab[index].xram_read        = xram_read;
    349     tab[index].nline            = nline;
    350     tab[index].srcid            = srcid;
    351     tab[index].trdid            = trdid;
    352     tab[index].pktid            = pktid;
    353     tab[index].proc_read            = proc_read;
    354     tab[index].read_length          = read_length;
    355     tab[index].word_index           = word_index;
    356     for(size_t i=0; i<tab[index].wdata.size(); i++)
    357     {
    358       tab[index].wdata_be[i]    = data_be[i];
    359       tab[index].wdata[i]       = data[i];
    360     }
    361   }
    362 
    363   /////////////////////////////////////////////////////////////////////
    364   // The write_rsp() function writes a word of the response to an
    365   // XRAM read transaction.
    366   // The BE field in TRT is taken into account.
    367   // Arguments :
    368   // - index : the index of the transaction in the transaction tab
    369   // - word_index : the index of the data in the line
    370   // - data : the data to write
    371   // - error : invalid data
    372   /////////////////////////////////////////////////////////////////////
    373   void write_rsp(const size_t index,
    374                  const size_t word,
    375                  const data_t data,
    376                  const bool   rerror)
    377   {
    378     assert( (index < size_tab)
    379             && "Selected entry  out of range in write_rsp() Transaction Tab");
    380     assert( (word <= tab[index].wdata_be.size())
    381             && "Bad word_index in write_rsp() in TransactionTab");
    382     assert( tab[index].valid
    383             && "Transaction Tab Entry invalid in write_rsp()");
    384     assert( tab[index].xram_read
    385             && "Selected entry is not an XRAM read transaction in write_rsp()");
    386 
    387     data_t mask = be_to_mask(tab[index].wdata_be[word]);
    388     tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
    389     tab[index].rerror |= rerror;
    390   }
    391 
    392   /////////////////////////////////////////////////////////////////////
    393   // The erase() function erases an entry in the transaction tab.
    394   // Arguments :
    395   // - index : the index of the request in the transaction tab
    396   /////////////////////////////////////////////////////////////////////
    397   void erase(const size_t index)
    398   {
    399     assert( (index < size_tab)
    400             && "The selected entry is out of range in erase() Transaction Tab");
    401     tab[index].valid    = false;
    402     tab[index].rerror   = false;
    403   }
     137    typedef uint32_t size_t;
     138    typedef uint32_t data_t;
     139    typedef sc_dt::sc_uint<40> addr_t;
     140    typedef uint32_t be_t;
     141
     142    private:
     143    size_t size_tab;                // The size of the tab
     144
     145    data_t be_to_mask(be_t be)
     146    {
     147        data_t ret = 0;
     148        if ( be&0x1 ) {
     149            ret = ret | 0x000000FF;
     150        }
     151        if ( be&0x2 ) {
     152            ret = ret | 0x0000FF00;
     153        }
     154        if ( be&0x4 ) {
     155            ret = ret | 0x00FF0000;
     156        }
     157        if ( be&0x8 ) {
     158            ret = ret | 0xFF000000;
     159        }
     160        return ret;
     161    }
     162
     163    public:
     164    TransactionTabEntry *tab;       // The transaction tab
     165
     166    ////////////////////////////////////////////////////////////////////
     167    //          Constructors
     168    ////////////////////////////////////////////////////////////////////
     169    TransactionTab()
     170    {
     171        size_tab=0;
     172        tab=NULL;
     173    }
     174
     175    TransactionTab(size_t n_entries, size_t n_words)
     176    {
     177        size_tab = n_entries;
     178        tab = new TransactionTabEntry[size_tab];
     179        for ( size_t i=0; i<size_tab; i++) {
     180            tab[i].alloc(n_words);
     181        }
     182    }
     183
     184    ~TransactionTab()
     185    {
     186        delete [] tab;
     187    }
     188
     189    /////////////////////////////////////////////////////////////////////
     190    // The size() function returns the size of the tab
     191    /////////////////////////////////////////////////////////////////////
     192    size_t size()
     193    {
     194        return size_tab;
     195    }
     196
     197    /////////////////////////////////////////////////////////////////////
     198    // The init() function initializes the transaction tab entries
     199    /////////////////////////////////////////////////////////////////////
     200    void init()
     201    {
     202        for ( size_t i=0; i<size_tab; i++) {
     203            tab[i].init();
     204        }
     205    }
     206
     207    /////////////////////////////////////////////////////////////////////
     208    // The print() function prints a transaction tab entry
     209    // Arguments :
     210    // - index : the index of the entry to print
     211    /////////////////////////////////////////////////////////////////////
     212    void print(const size_t index)
     213    {
     214        assert( (index < size_tab)
     215                && "Invalid Transaction Tab Entry");
     216        tab[index].print();
     217        return;
     218    }
     219
     220    /////////////////////////////////////////////////////////////////////
     221    // The read() function returns a transaction tab entry.
     222    // Arguments :
     223    // - index : the index of the entry to read
     224    /////////////////////////////////////////////////////////////////////
     225    TransactionTabEntry read(const size_t index)
     226    {
     227        assert( (index < size_tab)
     228                && "Invalid Transaction Tab Entry");
     229        return tab[index];
     230    }
     231
     232    /////////////////////////////////////////////////////////////////////
     233    // The full() function returns the state of the transaction tab
     234    // Arguments :
     235    // - index : (return argument) the index of an empty entry
     236    // The function returns true if the transaction tab is full
     237    /////////////////////////////////////////////////////////////////////
     238    bool full(size_t &index)
     239    {
     240        for(size_t i=0; i<size_tab; i++){
     241            if(!tab[i].valid){
     242                index=i;
     243                return false;   
     244            }
     245        }
     246        return true;
     247    }
     248
     249    /////////////////////////////////////////////////////////////////////
     250    // The hit_read() function checks if an XRAM read transaction exists
     251    // for a given cache line.
     252    // Arguments :
     253    // - index : (return argument) the index of the hit entry, if there is
     254    // - nline : the index (zy) of the requested line
     255    // The function returns true if a read request has already been sent
     256    //////////////////////////////////////////////////////////////////////
     257    bool hit_read(const addr_t nline,size_t &index)
     258    {
     259        for(size_t i=0; i<size_tab; i++){
     260            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
     261                index=i;
     262                return true;   
     263            }
     264        }
     265        return false;
     266    }
     267
     268    ///////////////////////////////////////////////////////////////////////
     269    // The hit_write() function looks if an XRAM write transaction exists
     270    // for a given line.
     271    // Arguments :
     272    // - nline : the index (zy) of the requested line
     273    // The function returns true if a write request has already been sent
     274    ///////////////////////////////////////////////////////////////////////
     275    bool hit_write(const addr_t nline)
     276    {
     277        for(size_t i=0; i<size_tab; i++){
     278            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
     279                return true;   
     280            }
     281        }
     282        return false;
     283    }
     284
     285    /////////////////////////////////////////////////////////////////////
     286    // The write_data_mask() function writes a vector of data (a line).
     287    // The data is written only if the corresponding bits are set
     288    // in the be vector.
     289    // Arguments :
     290    // - index : the index of the request in the transaction tab
     291    // - be   : vector of be
     292    // - data : vector of data
     293    /////////////////////////////////////////////////////////////////////
     294    void write_data_mask(const size_t index,
     295            const std::vector<be_t> &be,
     296            const std::vector<data_t> &data)
     297    {
     298        assert( (index < size_tab)
     299                && "Invalid Transaction Tab Entry");
     300        assert(be.size()==tab[index].wdata_be.size()
     301                && "Bad data mask in write_data_mask in TransactionTab");
     302        assert(data.size()==tab[index].wdata.size()
     303                && "Bad data in write_data_mask in TransactionTab");
     304
     305        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
     306            tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
     307            data_t mask = be_to_mask(be[i]);
     308            tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
     309        }
     310    }
     311
     312    /////////////////////////////////////////////////////////////////////
     313    // The set() function registers a transaction (read or write)
     314    // to the XRAM in the transaction tab.
     315    // Arguments :
     316    // - index : index in the transaction tab
     317    // - xram_read : transaction type (read or write a cache line)
     318    // - nline : the index (zy) of the cache line
     319    // - srcid : srcid of the initiator that caused the transaction
     320    // - trdid : trdid of the initiator that caused the transaction
     321    // - pktid : pktid of the initiator that caused the transaction
     322    // - proc_read : does the initiator want a copy
     323    // - read_length : length of read (in case of processor read)
     324    // - word_index : index in the line (in case of single word read)
     325    // - data : the data to write (in case of write)
     326    // - data_be : the mask of the data to write (in case of write)
     327    /////////////////////////////////////////////////////////////////////
     328    void set(const size_t index,
     329            const bool xram_read,
     330            const addr_t nline,
     331            const size_t srcid,
     332            const size_t trdid,
     333            const size_t pktid,
     334            const bool proc_read,
     335            const size_t read_length,
     336            const size_t word_index,
     337            const std::vector<be_t> &data_be,
     338            const std::vector<data_t> &data)
     339    {
     340        assert( (index < size_tab)
     341                && "The selected entry is out of range in set() Transaction Tab");
     342        assert(data_be.size()==tab[index].wdata_be.size()
     343                && "Bad data_be argument in set() TransactionTab");
     344        assert(data.size()==tab[index].wdata.size()
     345                && "Bad data argument in set() TransactionTab");
     346
     347        tab[index].valid                = true;
     348        tab[index].xram_read        = xram_read;
     349        tab[index].nline                = nline;
     350        tab[index].srcid                = srcid;
     351        tab[index].trdid                = trdid;
     352        tab[index].pktid                = pktid;
     353        tab[index].proc_read        = proc_read;
     354        tab[index].read_length      = read_length;
     355        tab[index].word_index       = word_index;
     356        for(size_t i=0; i<tab[index].wdata.size(); i++)
     357        {
     358            tab[index].wdata_be[i]    = data_be[i];
     359            tab[index].wdata[i]       = data[i];
     360        }
     361    }
     362
     363    /////////////////////////////////////////////////////////////////////
     364    // The write_rsp() function writes a word of the response to an
     365    // XRAM read transaction.
     366    // The BE field in TRT is taken into account.
     367    // Arguments :
     368    // - index : the index of the transaction in the transaction tab
     369    // - word_index : the index of the data in the line
     370    // - data : the data to write
     371    // - error : invalid data
     372    /////////////////////////////////////////////////////////////////////
     373    void write_rsp(const size_t index,
     374            const size_t word,
     375            const data_t data,
     376            const bool   rerror)
     377    {
     378        assert( (index < size_tab)
     379                && "Selected entry  out of range in write_rsp() Transaction Tab");
     380        assert( (word <= tab[index].wdata_be.size())
     381                && "Bad word_index in write_rsp() in TransactionTab");
     382        assert( tab[index].valid
     383                && "Transaction Tab Entry invalid in write_rsp()");
     384        assert( tab[index].xram_read
     385                && "Selected entry is not an XRAM read transaction in write_rsp()");
     386
     387        data_t mask = be_to_mask(tab[index].wdata_be[word]);
     388        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
     389        tab[index].rerror |= rerror;
     390    }
     391
     392    /////////////////////////////////////////////////////////////////////
     393    // The erase() function erases an entry in the transaction tab.
     394    // Arguments :
     395    // - index : the index of the request in the transaction tab
     396    /////////////////////////////////////////////////////////////////////
     397    void erase(const size_t index)
     398    {
     399        assert( (index < size_tab)
     400                && "The selected entry is out of range in erase() Transaction Tab");
     401        tab[index].valid        = false;
     402        tab[index].rerror   = false;
     403    }
    404404}; // end class TransactionTab
    405405

  • trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

    r247 r253  
    802802if( m_debug_tgt_cmd_fsm )
    803803{
    804     std::cout << "  <MEMC.TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read()
     804    std::cout << "  <MEMC " << name() << ".TGT_CMD_IDLE> Receive command from srcid " << std::dec << p_vci_tgt.srcid.read()
    805805              << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl;
    806806}
    … …  
    821821                {
    822822                    std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl;
    823                     std::cout << "Out of segment VCI address in TGT_CMD_IDLE state" << std::endl;
     823                    std::cout << "Out of segment VCI address in TGT_CMD_IDLE state (address = " << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read() << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl;
    824824                    exit(0);
    825825                }
    … …  
    869869if( m_debug_tgt_cmd_fsm )
    870870{
    871     std::cout << "  <MEMC.TGT_CMD_READ> Push into read_fifo:"
     871    std::cout << "  <MEMC " << name() << ".TGT_CMD_READ> Push into read_fifo:"
    872872              << " address = " << std::hex << p_vci_tgt.address.read()
    873873              << " srcid = " << std::dec << p_vci_tgt.srcid.read()
    … …  
    891891if( m_debug_tgt_cmd_fsm )
    892892{
    893     std::cout << "  <MEMC.TGT_CMD_WRITE> Push into write_fifo:"
     893    std::cout << "  <MEMC " << name() << ".TGT_CMD_WRITE> Push into write_fifo:"
    894894              << " address = " << std::hex << p_vci_tgt.address.read()
    895895              << " srcid = " << std::dec << p_vci_tgt.srcid.read()
    … …  
    921921if( m_debug_tgt_cmd_fsm )
    922922{
    923     std::cout << "  <MEMC.TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:"
     923    std::cout << "  <MEMC " << name() << ".TGT_CMD_ATOMIC> Pushing command into cmd_sc_fifo:"
    924924              << " address = " << std::hex << p_vci_tgt.address.read()
    925925              << " srcid = " << std::dec << p_vci_tgt.srcid.read()
    … …  
    969969if( m_debug_init_rsp_fsm )
    970970{
    971     std::cout <<  "  <MEMC.INIT_RSP_IDLE> Response for UPT entry "
     971    std::cout <<  "  <MEMC " << name() << ".INIT_RSP_IDLE> Response for UPT entry "
    972972              << p_vci_ini.rtrdid.read() << std::endl;
    973973}
    … …  
    10121012if( m_debug_init_rsp_fsm )
    10131013{
    1014     std::cout << "  <MEMC.INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:"
     1014    std::cout << "  <MEMC " << name() << ".INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:"
    10151015              << " entry = " << r_init_rsp_upt_index.read()
    10161016              << " / rsp_count = " << std::dec << count << std::endl;
    … …  
    10491049if ( m_debug_init_rsp_fsm )
    10501050{
    1051     std::cout <<  "  <MEMC.INIT_RSP_UPT_CLEAR> Clear UPT entry "
     1051    std::cout <<  "  <MEMC " << name() << ".INIT_RSP_UPT_CLEAR> Clear UPT entry "
    10521052              << r_init_rsp_upt_index.read() <<  std::endl;
    10531053}
    … …  
    10701070if ( m_debug_init_rsp_fsm )
    10711071{
    1072     std::cout <<  "  <MEMC.INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid "
     1072    std::cout <<  "  <MEMC " << name() << ".INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid "
    10731073              << r_init_rsp_srcid.read() <<  std::endl;
    10741074}
    … …  
    11131113if( m_debug_read_fsm )
    11141114{
    1115     std::cout << "  <MEMC.READ_IDLE> Read request:"
     1115    std::cout << "  <MEMC " << name() << ".READ_IDLE> Read request:"
    11161116              << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
    11171117              << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
    … …  
    11621162if( m_debug_read_fsm )
    11631163{
    1164     std::cout << "  <MEMC.READ_DIR_LOCK> Accessing directory: "
     1164    std::cout << "  <MEMC " << name() << ".READ_DIR_LOCK> Accessing directory: "
    11651165              << " address = " << std::hex << m_cmd_read_addr_fifo.read()
    11661166              << " / hit = " << std::dec << entry.valid
    … …  
    12331233if( m_debug_read_fsm )
    12341234{
    1235     std::cout << "  <MEMC.READ_DIR_HIT> Update directory entry:"
     1235    std::cout << "  <MEMC " << name() << ".READ_DIR_HIT> Update directory entry:"
    12361236              << " set = " << std::dec << set
    12371237              << " / way = " << way
    … …  
    13291329if( m_debug_read_fsm )
    13301330{
    1331     std::cout << "  <MEMC.READ_HEAP_LOCK> Update directory:"
     1331    std::cout << "  <MEMC " << name() << ".READ_HEAP_LOCK> Update directory:"
    13321332              << " tag = " << std::hex << entry.tag
    13331333              << " set = " << std::dec << set
    … …  
    13691369if( m_debug_read_fsm )
    13701370{
    1371     std::cout << "  <MEMC.READ_HEAP_WRITE> Add an entry in the heap:"
     1371    std::cout << "  <MEMC " << name() << ".READ_HEAP_WRITE> Add an entry in the heap:"
    13721372              << " owner_id = " << heap_entry.owner.srcid
    13731373              << " owner_ins = " << heap_entry.owner.inst << std::endl;
    … …  
    14601460if( m_debug_read_fsm )
    14611461{
    1462     std::cout << "  <MEMC.READ_RSP> Request the TGT_RSP FSM to return data:"
     1462    std::cout << "  <MEMC " << name() << ".READ_RSP> Request the TGT_RSP FSM to return data:"
    14631463              << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
    14641464              << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
    … …  
    14961496if( m_debug_read_fsm )
    14971497{
    1498     std::cout << "  <MEMC.READ_TRT_LOCK> Check TRT:"
     1498    std::cout << "  <MEMC " << name() << ".READ_TRT_LOCK> Check TRT:"
    14991499              << " hit_read = " << hit_read
    15001500              << " / hit_write = " << hit_write
    … …  
    15241524if( m_debug_read_fsm )
    15251525{
    1526     std::cout << "  <MEMC.READ_TRT_SET> Write in Transaction Table: " << std::hex
     1526    std::cout << "  <MEMC " << name() << ".READ_TRT_SET> Write in Transaction Table: " << std::hex
    15271527              << " address = " << std::hex << m_cmd_read_addr_fifo.read()
    15281528              << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
    … …  
    15491549if( m_debug_read_fsm )
    15501550{
    1551     std::cout << "  <MEMC.READ_TRT_REQ> Request GET transaction for address "
     1551    std::cout << "  <MEMC " << name() << ".READ_TRT_REQ> Request GET transaction for address "
    15521552              << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
    15531553}
    … …  
    16291629if( m_debug_write_fsm )
    16301630{
    1631     std::cout << "  <MEMC.WRITE_IDLE> Write request "
     1631    std::cout << "  <MEMC " << name() << ".WRITE_IDLE> Write request "
    16321632              << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
    16331633              << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
    … …  
    16471647if( m_debug_write_fsm )
    16481648{
    1649     std::cout << "  <MEMC.WRITE_NEXT> Write another word in local buffer" << std::endl;
     1649    std::cout << "  <MEMC " << name() << ".WRITE_NEXT> Write another word in local buffer" << std::endl;
    16501650}
    16511651#endif
    … …  
    17171717if( m_debug_write_fsm )
    17181718{
    1719     std::cout << "  <MEMC.WRITE_DIR_LOCK> Check the directory: "
     1719    std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> Check the directory: "
    17201720              << " address = " << std::hex << r_write_address.read()
    17211721              << " hit = " << std::dec << entry.valid
    … …  
    17561756if( m_debug_write_fsm )
    17571757{
    1758     std::cout << "  <MEMC.WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
     1758    std::cout << "  <MEMC " << name() << ".WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
    17591759}
    17601760#endif
    … …  
    18321832    if ( no_update )
    18331833    {
    1834         std::cout << "  <MEMC.WRITE_DIR_HIT> Write into cache / No coherence transaction"
     1834        std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Write into cache / No coherence transaction"
    18351835                  << std::endl;
    18361836    }
    18371837    else
    18381838    {
    1839         std::cout << "  <MEMC.WRITE_DIR_HIT> Coherence update required:"
     1839        std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Coherence update required:"
    18401840                  << " is_cnt = " << r_write_is_cnt.read()
    18411841                  << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
    … …  
    18951895    if ( wok )
    18961896    {
    1897         std::cout << "  <MEMC.WRITE_UPT_LOCK> Register the multicast update in UPT / "
     1897        std::cout << "  <MEMC " << name() << ".WRITE_UPT_LOCK> Register the multicast update in UPT / "
    18981898                  << " nb_copies = " << r_write_count.read() << std::endl;
    18991899    }
    … …  
    19161916if( m_debug_write_fsm )
    19171917{
    1918     std::cout << "  <MEMC.WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
     1918    std::cout << "  <MEMC " << name() << ".WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
    19191919}
    19201920#endif
    … …  
    19771977if( m_debug_write_fsm )
    19781978{
    1979     std::cout << "  <MEMC.WRITE_UPT_REQ> Post first request to INIT_CMD FSM"
     1979    std::cout << "  <MEMC " << name() << ".WRITE_UPT_REQ> Post first request to INIT_CMD FSM"
    19801980              << " / srcid = " << std::dec << r_write_copy.read()
    19811981              << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
    … …  
    20182018if( m_debug_write_fsm )
    20192019{
    2020     std::cout << "  <MEMC.WRITE_UPT_NEXT> Post another request to INIT_CMD FSM"
     2020    std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Post another request to INIT_CMD FSM"
    20212021              << " / heap_index = " << std::dec << r_write_ptr.read()
    20222022              << " / srcid = " << std::dec << r_write_copy.read()
    … …  
    20342034if( m_debug_write_fsm )
    20352035{
    2036     std::cout << "  <MEMC.WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
     2036    std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
    20372037              << " / heap_index = " << std::dec << r_write_ptr.read()
    20382038              << " / srcid = " << std::dec << r_write_copy.read()
    … …  
    21332133if( m_debug_write_fsm )
    21342134{
    2135     std::cout << "  <MEMC.WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
     2135    std::cout << "  <MEMC " << name() << ".WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
    21362136              << std::dec << r_write_srcid.read() << std::endl;
    21372137    if ( m_cmd_write_addr_fifo.rok() )
    … …  
    21562156if( m_debug_write_fsm )
    21572157{
    2158     std::cout << "  <MEMC.WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
     2158    std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
    21592159}
    21602160#endif
    … …  
    21932193if( m_debug_write_fsm )
    21942194{
    2195     std::cout << "  <MEMC.WRITE_WAIT> Releases the locks before retry" << std::endl;
     2195    std::cout << "  <MEMC " << name() << ".WRITE_WAIT> Releases the locks before retry" << std::endl;
    21962196}
    21972197#endif
    … …  
    22292229if( m_debug_write_fsm )
    22302230{
    2231     std::cout << "  <MEMC.WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
     2231    std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
    22322232}
    22332233#endif
    … …  
    22572257if( m_debug_write_fsm )
    22582258{
    2259     std::cout << "  <MEMC.WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
     2259    std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
    22602260    m_transaction_tab.print( r_write_trt_index.read() );
    22612261}
    … …  
    22782278if( m_debug_write_fsm )
    22792279{
    2280     std::cout << "  <MEMC.WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
     2280    std::cout << "  <MEMC " << name() << ".WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
    22812281}
    22822282#endif
    … …  
    23042304if( m_debug_write_fsm )
    23052305{
    2306     std::cout << "  <MEMC.WRITE_BC_TRT_LOCK> Check TRT : wok = "
     2306    std::cout << "  <MEMC " << name() << ".WRITE_BC_TRT_LOCK> Check TRT : wok = "
    23072307              << wok << " / index = " << wok_index << std::endl;
    23082308}
    … …  
    23392339    if ( wok )
    23402340    {
    2341         std::cout << "  <MEMC.WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
     2341        std::cout << "  <MEMC " << name() << ".WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
    23422342                  << " nb_copies = " << r_write_count.read() << std::endl;
    23432343    }
    … …  
    23982398if( m_debug_write_fsm )
    23992399{
    2400     std::cout << "  <MEMC.WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
     2400    std::cout << "  <MEMC " << name() << ".WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
    24012401              << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
    24022402}
    … …  
    24272427if( m_debug_write_fsm )
    24282428{
    2429     std::cout << "  <MEMC.WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
     2429    std::cout << "  <MEMC " << name() << ".WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
    24302430}
    24312431#endif
    … …  
    24502450if( m_debug_write_fsm )
    24512451{
    2452     std::cout << "  <MEMC.WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
     2452    std::cout << "  <MEMC " << name() << ".WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
    24532453}
    24542454#endif
    … …  
    25142514if( m_debug_ixr_cmd_fsm )
    25152515{
    2516     std::cout << "  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
     2516    std::cout << "  <MEMC " << name() << ".IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
    25172517}
    25182518#endif
    … …  
    25392539if( m_debug_ixr_cmd_fsm )
    25402540{
    2541     std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
     2541    std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
    25422542}
    25432543#endif
    … …  
    25512551if( m_debug_ixr_cmd_fsm )
    25522552{
    2553     std::cout << "  <MEMC.IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
     2553    std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
    25542554}
    25552555#endif
    … …  
    25772577if( m_debug_ixr_cmd_fsm )
    25782578{
    2579     std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;
     2579    std::cout << "  <MEMC " << name() << ".IXR_CMD_SC_NLINE> Send a put request to xram" << std::endl;
    25802580}
    25812581#endif
    … …  
    25892589if( m_debug_ixr_cmd_fsm )
    25902590{
    2591     std::cout << "  <MEMC.IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;
     2591    std::cout << "  <MEMC " << name() << ".IXR_CMD_SC_NLINE> Send a get request to xram" << std::endl;
    25922592}
    25932593#endif
    … …  
    26132613if( m_debug_ixr_cmd_fsm )
    26142614{
    2615     std::cout << "  <MEMC.IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
     2615    std::cout << "  <MEMC " << name() << ".IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
    26162616}
    26172617#endif
    … …  
    26562656if( m_debug_ixr_rsp_fsm )
    26572657{
    2658     std::cout << "  <MEMC.IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
     2658    std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
    26592659}
    26602660#endif
    … …  
    26672667if( m_debug_ixr_rsp_fsm )
    26682668{
    2669     std::cout << "  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
     2669    std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
    26702670}
    26712671#endif
    … …  
    26822682if( m_debug_ixr_rsp_fsm )
    26832683{
    2684     std::cout << "  <MEMC.IXR_RSP_ACK>" << std::endl;
     2684    std::cout << "  <MEMC " << name() << ".IXR_RSP_ACK>" << std::endl;
    26852685}
    26862686#endif
    … …  
    26982698if( m_debug_ixr_rsp_fsm )
    26992699{
    2700     std::cout << "  <MEMC.IXR_RSP_TRT_ERASE> Erase TRT entry "
     2700    std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_ERASE> Erase TRT entry "
    27012701              << r_ixr_rsp_trt_index.read() << std::endl;
    27022702}
    … …  
    27302730if( m_debug_ixr_rsp_fsm )
    27312731{
    2732     std::cout << "  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT : "
     2732    std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_READ> Writing a word in TRT : "
    27332733              << " index = " << std::dec << index
    27342734              << " / word = " << r_ixr_rsp_cpt.read()
    … …  
    27832783if( m_debug_xram_rsp_fsm )
    27842784{       
    2785     std::cout << "  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT:"
     2785    std::cout << "  <MEMC " << name() << ".XRAM_RSP_IDLE> Available cache line in TRT:"
    27862786              << " index = " << std::dec << index << std::endl;
    27872787}
    … …  
    28022802if( m_debug_xram_rsp_fsm )
    28032803{       
    2804     std::cout << "  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
     2804    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
    28052805}
    28062806#endif
    … …  
    28502850if( m_debug_xram_rsp_fsm )
    28512851{
    2852     std::cout << "  <MEMC.XRAM_RSP_TRT_COPY> Select a slot: "
     2852    std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_COPY> Select a slot: "
    28532853              << " way = " << std::dec << way
    28542854              << " / set = " << set
    … …  
    28722872if( m_debug_xram_rsp_fsm )
    28732873{
    2874     std::cout << "  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
     2874    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
    28752875              << " but an invalidation is already registered at this address" << std::endl;
    28762876    m_update_tab.print();
    … …  
    28862886if( m_debug_xram_rsp_fsm )
    28872887{
    2888     std::cout << "  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
     2888    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
    28892889              << " but the table is full" << std::endl;
    28902890    m_update_tab.print();
    … …  
    28992899if( m_debug_xram_rsp_fsm )
    29002900{
    2901     std::cout << "  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
     2901    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
    29022902}
    29032903#endif
    … …  
    29912991if( m_debug_xram_rsp_fsm )
    29922992{
    2993     std::cout << "  <MEMC.XRAM_RSP_DIR_UPDT> Directory update: "
     2993    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_UPDT> Directory update: "
    29942994              << " way = " << std::dec << way
    29952995              << " / set = " << set
    … …  
    30343034if( m_debug_xram_rsp_fsm )
    30353035{
    3036     std::cout << "  <MEMC.XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
     3036    std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
    30373037              << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
    30383038}
    … …  
    30663066if( m_debug_xram_rsp_fsm )
    30673067{
    3068     std::cout << "  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
     3068    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
    30693069              << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
    30703070              << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
    … …  
    31043104if( m_debug_xram_rsp_fsm )
    31053105{
    3106     std::cout << "  <MEMC.XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:"
     3106    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:"
    31073107              << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
    31083108}
    … …  
    31303130if( m_debug_xram_rsp_fsm )
    31313131{
    3132     std::cout << "  <MEMC.XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
     3132    std::cout << "  <MEMC " << name() << ".XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
    31333133              << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
    31343134}
    … …  
    31713171if( m_debug_xram_rsp_fsm )
    31723172{
    3173     std::cout << "  <MEMC.XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
     3173    std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
    31743174              << " srcid = " << std::dec << entry.owner.srcid
    31753175              << " / inst = " << std::dec << entry.owner.inst << std::endl;
    … …  
    32143214if( m_debug_xram_rsp_fsm )
    32153215{
    3216     std::cout << "  <MEMC.XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
     3216    std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
    32173217}
    32183218#endif
    … …  
    32313231if( m_debug_xram_rsp_fsm )
    32323232{
    3233     std::cout << "  <MEMC.XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
     3233    std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
    32343234}
    32353235#endif
    … …  
    32553255if( m_debug_xram_rsp_fsm )
    32563256{
    3257     std::cout << "  <MEMC.XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
     3257    std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
    32583258              << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
    32593259}
    … …  
    33093309if( m_debug_cleanup_fsm )
    33103310{
    3311     std::cout << "  <MEMC.CLEANUP_IDLE> Cleanup request:" << std::hex
    3312               << " line = " << line * m_words * 4
     3311    std::cout << "  <MEMC " << name() << ".CLEANUP_IDLE> Cleanup request:" << std::hex
     3312              << " line addr = " << line * m_words * 4
    33133313              << " / owner_id = " << p_vci_tgt_cleanup.srcid.read()
    33143314              << " / owner_ins = " << (p_vci_tgt_cleanup.trdid.read()&0x1)
    … …  
    33623362if( m_debug_cleanup_fsm )
    33633363{
    3364     std::cout << "  <MEMC.CLEANUP_DIR_LOCK> Test directory status: " << std::hex
     3364    std::cout << "  <MEMC " << name() << ".CLEANUP_DIR_LOCK> Test directory status: " << std::hex
    33653365              << " line = " << r_cleanup_nline.read() * m_words * 4
    33663366              << " / hit = " << entry.valid
    … …  
    34463446if( m_debug_cleanup_fsm )
    34473447{
    3448     std::cout << "  <MEMC.CLEANUP_DIR_WRITE> Update directory:" << std::hex
     3448    std::cout << "  <MEMC " << name() << ".CLEANUP_DIR_WRITE> Update directory:" << std::hex
    34493449              << " line = " << r_cleanup_nline.read() * m_words * 4
    34503450              << " / dir_id = " << entry.owner.srcid
    … …  
    35673567if( m_debug_cleanup_fsm )
    35683568{
    3569     std::cout << "  <MEMC.CLEANUP_HEAP_LOCK> Checks matching:"
     3569    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_LOCK> Checks matching:"
    35703570              << " line = " << r_cleanup_nline.read() * m_words * 4
    35713571              << " / dir_id = " << r_cleanup_copy.read()
    … …  
    36053605if( m_debug_cleanup_fsm )
    36063606{
    3607     std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Cheks matching:"
     3607    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Cheks matching:"
    36083608              << " line = " << r_cleanup_nline.read() * m_words * 4
    36093609              << " / heap_id = " << heap_entry.owner.srcid
    … …  
    36423642if( m_debug_cleanup_fsm )
    36433643{
    3644     std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
     3644    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
    36453645              << " line = " << r_cleanup_nline.read() * m_words * 4
    36463646              << " / heap_id = " << heap_entry.owner.srcid
    … …  
    36863686if( m_debug_cleanup_fsm )
    36873687{
    3688     std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl;
     3688    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl;
    36893689}
    36903690#endif
    … …  
    37193719if( m_debug_cleanup_fsm )
    37203720{
    3721     std::cout << "  <MEMC.CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl;
     3721    std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl;
    37223722}
    37233723#endif
    … …  
    37393739if( m_debug_cleanup_fsm )
    37403740{
    3741     std::cout << "  <MEMC.CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:"
     3741    std::cout << "  <MEMC " << name() << ".CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:"
    37423742              << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl;
    37433743}
    … …  
    37693769if( m_debug_cleanup_fsm )
    37703770{
    3771     std::cout << "  <MEMC.CLEANUP_UPT_WRITE> Decrement response counter in UPT:"
     3771    std::cout << "  <MEMC " << name() << ".CLEANUP_UPT_WRITE> Decrement response counter in UPT:"
    37723772              << " UPT_index = " << r_cleanup_index.read()
    37733773              << " rsp_count = " << count << std::endl;
    … …  
    37973797if( m_debug_cleanup_fsm )
    37983798{
    3799     std::cout << "  <MEMC.CLEANUP_WRITE_RSP> Send a response to a cleanup request:"
     3799    std::cout << "  <MEMC " << name() << ".CLEANUP_WRITE_RSP> Send a response to a cleanup request:"
    38003800              << " rsrcid = " << std::dec << r_cleanup_write_srcid.read()
    38013801              << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() << std::endl;
    … …  
    38153815if( m_debug_cleanup_fsm )
    38163816{
    3817     std::cout << "  <MEMC.CLEANUP_RSP> Send the response to a cleanup request:"
     3817    std::cout << "  <MEMC " << name() << ".CLEANUP_RSP> Send the response to a cleanup request:"
    38183818              << " rsrcid = " << std::dec << r_cleanup_write_srcid.read()
    38193819              << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl;
    … …  
    38613861if( m_debug_sc_fsm )
    38623862{
    3863     std::cout << "  <MEMC.SC_IDLE> SC command: " << std::hex
     3863    std::cout << "  <MEMC " << name() << ".SC_IDLE> SC command: " << std::hex
    38643864              << " srcid = " <<  std::dec << m_cmd_sc_srcid_fifo.read()
    38653865              << " addr = " << std::hex << m_cmd_sc_addr_fifo.read()
    … …  
    39253925if( m_debug_sc_fsm )
    39263926{
    3927     std::cout << "  <MEMC.SC_DIR_LOCK> Directory acces"
     3927    std::cout << "  <MEMC " << name() << ".SC_DIR_LOCK> Directory acces"
    39283928              << " / address = " << std::hex << m_cmd_sc_addr_fifo.read()
    39293929              << " / hit = " << std::dec << entry.valid
    … …  
    39813981if( m_debug_sc_fsm )
    39823982{
    3983     std::cout << "  <MEMC.SC_DIR_HIT_READ> Test if SC success:"
     3983    std::cout << "  <MEMC " << name() << ".SC_DIR_HIT_READ> Test if SC success:"
    39843984              << " / expected value = " << r_sc_rdata[0].read()
    39853985              << " / actual value = " << m_cache_data[way][set][word]
    … …  
    40364036if( m_debug_sc_fsm )
    40374037{
    4038     std::cout << "  <MEMC.SC_DIR_HIT_WRITE> Update cache:"
     4038    std::cout << "  <MEMC " << name() << ".SC_DIR_HIT_WRITE> Update cache:"
    40394039              << " way = " << std::dec << way
    40404040              << " / set = " << set
    … …  
    41044104if( m_debug_sc_fsm )
    41054105{
    4106     std::cout << "  <MEMC.SC_UPT_LOCK> Register multi-update transaction in UPT" 
     4106    std::cout << "  <MEMC " << name() << ".SC_UPT_LOCK> Register multi-update transaction in UPT" 
    41074107              << " / wok = " << wok
    41084108              << " / nline  = " << std::hex << nline
    … …  
    41204120if( m_debug_sc_fsm )
    41214121{
    4122     std::cout << "  <MEMC.SC_WAIT> Release all locks" << std::endl;
     4122    std::cout << "  <MEMC " << name() << ".SC_WAIT> Release all locks" << std::endl;
    41234123}
    41244124#endif
    … …  
    41354135if( m_debug_sc_fsm )
    41364136{
    4137     std::cout << "  <MEMC.SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
     4137    std::cout << "  <MEMC " << name() << ".SC_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
    41384138}
    41394139#endif
    … …  
    41904190if( m_debug_sc_fsm )
    41914191{
    4192     std::cout << "  <MEMC.SC_UPT_REQ> Send the first update request to INIT_CMD FSM "
     4192    std::cout << "  <MEMC " << name() << ".SC_UPT_REQ> Send the first update request to INIT_CMD FSM "
    41934193              << " / address = " << std::hex << m_cmd_sc_addr_fifo.read()
    41944194              << " / wdata = " << std::hex << r_sc_wdata.read()
    … …  
    42304230if( m_debug_sc_fsm )
    42314231{
    4232     std::cout << "  <MEMC.SC_UPT_NEXT> Send the next update request to INIT_CMD FSM "
     4232    std::cout << "  <MEMC " << name() << ".SC_UPT_NEXT> Send the next update request to INIT_CMD FSM "
    42334233              << " / address = " << std::hex << m_cmd_sc_addr_fifo.read()
    42344234              << " / wdata = " << std::hex << r_sc_wdata.read()
    … …  
    43354335if( m_debug_sc_fsm )
    43364336{
    4337     std::cout << "  <MEMC.SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
     4337    std::cout << "  <MEMC " << name() << ".SC_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
    43384338              << " / nline = " << nline
    43394339              << " / count = " << nb_copies
    … …  
    43924392if( m_debug_sc_fsm )
    43934393{
    4394     std::cout << "  <MEMC.SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
     4394    std::cout << "  <MEMC " << name() << ".SC_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
    43954395              << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_sc_addr_fifo.read())]
    43964396              << " / set = " << std::dec << set << " / way = " << way << std::endl;
    … …  
    44374437if( m_debug_sc_fsm )
    44384438{
    4439     std::cout << "  <MEMC.SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
     4439    std::cout << "  <MEMC " << name() << ".SC_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
    44404440              << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
    44414441              << " / trt_index = " << r_sc_trt_index.read() << std::endl;
    … …  
    44674467if( m_debug_sc_fsm )
    44684468{
    4469     std::cout << "  <MEMC.SC_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
     4469    std::cout << "  <MEMC " << name() << ".SC_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
    44704470}
    44714471#endif
    … …  
    44904490if( m_debug_sc_fsm )
    44914491{
    4492     std::cout << "  <MEMC.SC_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
     4492    std::cout << "  <MEMC " << name() << ".SC_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
    44934493}
    44944494#endif
    … …  
    45114511if( m_debug_sc_fsm )
    45124512{
    4513     std::cout << "  <MEMC.SC_MISS_TRT_LOCK> Check TRT state"
     4513    std::cout << "  <MEMC " << name() << ".SC_MISS_TRT_LOCK> Check TRT state"
    45144514              << " / hit_read = "  << hit_read
    45154515              << " / hit_write = " << hit_write
    … …  
    45624562if( m_debug_sc_fsm )
    45634563{
    4564     std::cout << "  <MEMC.SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
     4564    std::cout << "  <MEMC " << name() << ".SC_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
    45654565              << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
    45664566              << " / trt_index = " << r_sc_trt_index.read() << std::endl;
    … …  
    45844584if( m_debug_sc_fsm )
    45854585{
    4586     std::cout << "  <MEMC.SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
     4586    std::cout << "  <MEMC " << name() << ".SC_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
    45874587              << " / nline = " << m_nline[(vci_addr_t)m_cmd_sc_addr_fifo.read()]
    45884588              << " / trt_index = " << r_sc_trt_index.read() << std::endl;
    … …  
    47734773if( m_debug_init_cmd_fsm )
    47744774{
    4775     std::cout << "  <MEMC.INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line "
     4775    std::cout << "  <MEMC " << name() << ".INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line "
    47764776              << r_write_to_init_cmd_nline.read() << std::endl;
    47774777}
    … …  
    50315031if( m_debug_tgt_rsp_fsm )
    50325032{
    5033     std::cout << "  <MEMC.TGT_RSP_READ> Read response"
     5033    std::cout << "  <MEMC " << name() << ".TGT_RSP_READ> Read response"
    50345034              << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read()
    50355035              << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
    … …  
    50595059if( m_debug_tgt_rsp_fsm )
    50605060{
    5061     std::cout << "  <MEMC.TGT_RSP_WRITE> Write response"
     5061    std::cout << "  <MEMC " << name() << ".TGT_RSP_WRITE> Write response"
    50625062              << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read()
    50635063              << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() << std::endl;
    … …  
    50785078if( m_debug_tgt_rsp_fsm )
    50795079{
    5080     std::cout << "  <MEMC.TGT_RSP_CLEANUP> Cleanup response"
     5080    std::cout << "  <MEMC " << name() << ".TGT_RSP_CLEANUP> Cleanup response"
    50815081              << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
    50825082              << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() << std::endl;
    … …  
    50975097if( m_debug_tgt_rsp_fsm )
    50985098{
    5099     std::cout << "  <MEMC.TGT_RSP_SC> SC response"
     5099    std::cout << "  <MEMC " << name() << ".TGT_RSP_SC> SC response"
    51005100              << " / rsrcid = " << std::dec << r_sc_to_tgt_rsp_srcid.read()
    51015101              << " / rtrdid = " << r_sc_to_tgt_rsp_trdid.read() << std::endl;
    … …  
    51175117if( m_debug_tgt_rsp_fsm )
    51185118{
    5119     std::cout << "  <MEMC.TGT_RSP_XRAM> Response following XRAM access"
     5119    std::cout << "  <MEMC " << name() << ".TGT_RSP_XRAM> Response following XRAM access"
    51205120              << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read()
    51215121              << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
    … …  
    51475147if( m_debug_tgt_rsp_fsm )
    51485148{
    5149     std::cout << "  <MEMC.TGT_RSP_INIT> Write response after coherence transaction"
     5149    std::cout << "  <MEMC " << name() << ".TGT_RSP_INIT> Write response after coherence transaction"
    51505150              << " / rsrcid = " << std::dec << r_init_rsp_to_tgt_rsp_srcid.read()
    51515151              << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read() << std::endl;
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