Ignore:
Timestamp:
Feb 28, 2014, 4:45:35 PM (9 years ago)
Author:
haoliu
Message:

(RWT) merging the lastest modification in trunk:

Modification in vci_cc_vcache_wrapper:
a) Non cacheable write request will not any more be sent by multi_write_buffer.

A write non cacheable access is retreated with a synchronous way, like the
read non cacheable access. When Cache L1 receives a write non cacheable request,
it will block the processor until the response of this request arrives.
The advantage of this method is that the cache L1 can supply the virtual address
to OS when it receives a bus error response.

b) In VCI_CMD_STATE, the unc_read request will not check the multi_write_buffer for

an matching address. But the CAS and SC request must be check this point
before sent to the target.

Modifcation in vci_mem_cache:
Change an assert in memcache for the modification in cache L1(UNC WRITE)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r645 r646  
    152152        CMD_INS_UNC,
    153153        CMD_DATA_MISS,
    154         CMD_DATA_UNC,
     154        CMD_DATA_UNC_READ,
     155        CMD_DATA_UNC_WRITE,
    155156        CMD_DATA_WRITE,
    156157        CMD_DATA_LL,
     
    207208        //  b1 accÚs table llsc type SW / other
    208209        //  b2 WRITE/CAS/LL/SC
    209         TYPE_READ_DATA_UNC          = 0x0,
     210        TYPE_DATA_UNC               = 0x0,
    210211        TYPE_READ_DATA_MISS         = 0x1,
    211212        TYPE_READ_INS_UNC           = 0x2,
     
    279280    };
    280281
    281     enum transaction_type_d_e
    282     {
    283         // b0 : 1 if cached
    284         // b1 : 1 if instruction
    285         TYPE_DATA_UNC     = 0x0,
    286         TYPE_DATA_MISS    = 0x1,
    287         TYPE_INS_UNC      = 0x2,
    288         TYPE_INS_MISS     = 0x3,
    289     };
     282//    enum transaction_type_d_e
     283//    {
     284//        // b0 : 1 if cached
     285//        // b1 : 1 if instruction
     286//        TYPE_DATA_UNC     = 0x0,
     287//        TYPE_DATA_MISS    = 0x1,
     288//        TYPE_INS_UNC      = 0x2,
     289//        TYPE_INS_MISS     = 0x3,
     290//    };
    290291
    291292    //////////////////MODIFIED////////////////
     
    428429    sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
    429430    sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
    430     sc_signal<bool>         r_dcache_save_cacheable;    // address cacheable
    431431    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
    432432    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
     
    439439    // communication between DCACHE FSM and VCI_CMD FSM
    440440    sc_signal<paddr_t>      r_dcache_vci_paddr;             // physical address for VCI command
     441    sc_signal<uint32_t>     r_dcache_vci_wdata;             // write unc data for VCI command
    441442    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
    442     sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
    443     sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable read byte enable
     443    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
     444    sc_signal<uint32_t>     r_dcache_vci_unc_be;        // uncacheable byte enable
     445    sc_signal<uint32_t>     r_dcache_vci_unc_write;     // uncacheable data write request
    444446    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
    445447    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for a CAS
     
    458460    sc_signal<size_t>       r_dcache_xtn_way;               // selected way (from dcache)
    459461    sc_signal<size_t>       r_dcache_xtn_set;               // selected set (from dcache)
    460 
    461     // write buffer state extension
    462     sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
    463462
    464463    // handling dcache miss
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