Ignore:
Timestamp:
Aug 25, 2014, 5:58:16 PM (8 years ago)
Author:
devigne
Message:

RWT commit :

  • Merge with trunk.
  • Cosmetic
  • Bugfix in state WRITE_IVT_LOCK_HIT_WB.

MemCache? records invalidation in IVT in this state but we do not check that
the IVT was full. Thus invalidation was issued without actually recorded in the
query IVT ...

  • Bugfix :

When a NCC line owned by a L1 cache with srcid != 0 was removed from MemCache?,
the owner field was reset to 0. If this same L1 cache was sending a read to
retrieve this line the MemCache? sent this line on CC mode.

  • Bugfix :

The MemCache? reset the 'inst' field to 0 when solving a
invalidation due to a change of state of line (NCC to CC).
But a line can be NCC (ie contained in a DATA cache) then asked by INST cache,
this read triggers a transition NCC to CC but we must save the nature of this read.
Now this information is stored in a register (r_read_to_cleanup_inst).

  • Add a counter for the number of minimum inputs available

in the heap. This counter indicates whether the heap size of 4096 is relevant.

File:
1 edited

Legend:

Unmodified
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Removed
  • branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r646 r767  
    280280    };
    281281
    282 //    enum transaction_type_d_e
    283 //    {
    284 //        // b0 : 1 if cached
    285 //        // b1 : 1 if instruction
    286 //        TYPE_DATA_UNC     = 0x0,
    287 //        TYPE_DATA_MISS    = 0x1,
    288 //        TYPE_INS_UNC      = 0x2,
    289 //        TYPE_INS_MISS     = 0x3,
    290 //    };
    291 
    292     //////////////////MODIFIED////////////////
     282
     283    // cache line status
    293284    enum content_line_cache_status_e
    294285    {
     
    522513    sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
    523514   
    524     // special registers for ODCCP/RWT
    525     sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
    526     sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
    527     sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
    528     sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
     515    // special registers for RWT
     516    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;     // Register for cleanup with data (wb updt)
     517    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;      // Register for cleanup with data (wb updt)
     518    sc_signal<bool>         r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
     519    sc_signal<bool>         r_dcache_line_no_coherence;        // Register for line current in no coherence mode
    529520    sc_signal<bool>         r_dcache_dirty_save;             
    530521    sc_signal<uint32_t>     r_cc_send_cpt_word;
     
    536527    sc_signal<paddr_t>      r_dcache_xtn_data_addr;
    537528    sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
     529    sc_signal<bool>         r_dcache_read_state;
     530
    538531    // dcache directory extension
    539     ///////////////////////////MODIFIED///////////////////////////////////////////////////
    540     //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
    541     //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
    542532    int                     *r_dcache_content_state; // content state of one cache line
    543     int                     *r_dcache_dirty_word;   
    544     bool                    *r_dcache_zombi_ncc;     
     533    // Stats
     534    int                     *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
     535    bool                    *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
    545536    //////////////////////////////////////////////////////////////////////////////////////
    546537
    547     //RWT
    548     sc_signal<bool>         r_dcache_read_state;
    549    
    550      ///////////////////////////////////
     538    ///////////////////////////////////
    551539    // Physical address extension for data access
    552540    sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
     
    574562    //RWT
    575563    GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
    576 
    577564    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
    578565
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