Changeset 718 for trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

Timestamp:

Jun 24, 2014, 10:15:26 AM (10 years ago)

Author:

cfuguet

Message:

tsar_generic_iob:

• Replacing "ad-hoc" dspin_tsar router by standard dspin_router on the RAM interconnect. To do so, in IO clusters (clusters with IOB) two crossbars are implemented:

+ One for commands which interconnects MEMC and IOB to the

local interface of RAM CMD dspin_router.

+ One for responses which interconnects local interface of RAM

RSP dspin_router to MEMC and IOB.

• Introducing modified vci_io_bridge component

• Modifying IOX memory segments used by IOX network for routing:

+ bugfix: all segments of IOX interconnect must have

global id = 0.

+ Adding XICU segments with special attribute. This

attribute is used by IOB to determine if a command coming
from external DMA peripheral should be routed
through INT or RAM networks.

+ Using bit 32 of physical address to determine if an

external DMA command should be routed through IOB0
or IOB1.

File:

• trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (8 diffs)

trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

@@ -26 +26 @@
 #include "vci_dspin_initiator_wrapper.h"
 #include "vci_dspin_target_wrapper.h"
-#include "dspin_router_tsar.h"
+#include "dspin_router.h"
 #include "virtual_dspin_router.h"
 #include "vci_multi_dma.h"
@@ -57 +57 @@
     soclib::caba::VciTarget<vci_param_ext>*            p_vci_iob_iox_tgt; 
 
-    // These ports are used to connect IOB to RAM network in top cell
-    soclib::caba::DspinOutput<dspin_ram_cmd_width>*    p_dspin_iob_cmd_out;  
-    soclib::caba::DspinInput<dspin_ram_rsp_width>*     p_dspin_iob_rsp_in;  
-
     // These arrays of ports are used to connect the INT & RAM networks in top cell
     soclib::caba::DspinOutput<dspin_int_cmd_width>**   p_dspin_int_cmd_out;
@@ -116 +112 @@
     VciSignals<vci_param_ext>             signal_ram_vci_tgt_xram;
 
-    // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 
+    // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar
+    // and routers 
     DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xram_t;
     DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xram_t;
     DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_memc_i;
     DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_memc_i;
+    DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_iob_i;
+    DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_iob_i;
+    DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xbar;
+    DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xbar;
+    DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_false;
+    DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_false;
   
     //////////////////////////////////////
@@ -166 +169 @@
                           dspin_ram_rsp_width>*       xram_ram_wt;
     
-    DspinRouterTsar<dspin_ram_cmd_width>*             ram_router_cmd;
-    DspinRouterTsar<dspin_ram_rsp_width>*             ram_router_rsp;
+    DspinRouter<dspin_ram_cmd_width>*                 ram_router_cmd;
+    DspinRouter<dspin_ram_rsp_width>*                 ram_router_rsp;
+
+    DspinLocalCrossbar<dspin_ram_cmd_width>*          ram_xbar_cmd;
+    DspinLocalCrossbar<dspin_ram_rsp_width>*          ram_xbar_rsp;
+    
 
     // IO Network Components (not instanciated in all clusters)
@@ -177 +184 @@
                              dspin_ram_cmd_width,
                              dspin_ram_rsp_width>*    iob_ram_wi;
-    
+
     // cluster constructor
     TsarIobCluster( sc_module_name                     insname,
@@ -195 +202 @@
                     size_t                             l_width,       // l field  bits
 
-                    size_t                             int_memc_tgtid,
-                    size_t                             int_xicu_tgtid,
-                    size_t                             int_mdma_tgtid,
-                    size_t                             int_iobx_tgtid,
-
-                    size_t                             int_proc_srcid,
-                    size_t                             int_mdma_srcid,
-                    size_t                             int_iobx_srcid,
-
-                    size_t                             ext_xram_tgtid,
-
-                    size_t                             ext_memc_srcid,
-                    size_t                             ext_iobx_srcid,
+                    size_t                             int_memc_tgt_id,
+                    size_t                             int_xicu_tgt_id,
+                    size_t                             int_mdma_tgt_id,
+                    size_t                             int_iobx_tgt_id,
+                    size_t                             int_proc_ini_id,
+                    size_t                             int_mdma_ini_id,
+                    size_t                             int_iobx_ini_id,
+
+                    size_t                             ram_xram_tgt_id,
+                    size_t                             ram_memc_ini_id,
+                    size_t                             ram_iobx_ini_id,
+
+                    bool                               is_io,
+                    size_t                             iox_iobx_tgt_id,
+                    size_t                             iox_iobx_ini_id,
 
                     size_t                             memc_ways,
@@ -226 +235 @@
                     bool                               iob0_debug_ok ); 
 
+  protected:
+
+    SC_HAS_PROCESS(TsarIobCluster);
+
+    void init();
+ 
+
 };
 
@@ -231 +247 @@
 
 #endif
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+//