[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.h |
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[648] | 3 | // Author: Alain Greiner |
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[450] | 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | |
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| 9 | #ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 10 | #define SOCLIB_CABA_TSAR_IOB_CLUSTER_H |
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| 11 | |
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| 12 | #include <systemc> |
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| 13 | #include <sys/time.h> |
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| 14 | #include <iostream> |
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| 15 | #include <sstream> |
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| 16 | #include <cstdlib> |
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| 17 | #include <cstdarg> |
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| 18 | |
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| 19 | #include "gdbserver.h" |
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| 20 | #include "mapping_table.h" |
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| 21 | #include "mips32.h" |
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| 22 | #include "vci_simple_ram.h" |
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| 23 | #include "vci_xicu.h" |
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| 24 | #include "dspin_local_crossbar.h" |
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| 25 | #include "vci_dspin_initiator_wrapper.h" |
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| 26 | #include "vci_dspin_target_wrapper.h" |
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[550] | 27 | #include "dspin_router_tsar.h" |
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[450] | 28 | #include "virtual_dspin_router.h" |
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| 29 | #include "vci_multi_dma.h" |
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| 30 | #include "vci_mem_cache.h" |
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| 31 | #include "vci_cc_vcache_wrapper.h" |
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| 32 | #include "vci_io_bridge.h" |
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| 33 | |
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[648] | 34 | namespace soclib { namespace caba { |
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[450] | 35 | |
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| 36 | /////////////////////////////////////////////////////////////////////////// |
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[648] | 37 | template<typename vci_param_int, |
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[450] | 38 | typename vci_param_ext, |
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[648] | 39 | size_t dspin_int_cmd_width, |
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[450] | 40 | size_t dspin_int_rsp_width, |
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| 41 | size_t dspin_ram_cmd_width, |
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| 42 | size_t dspin_ram_rsp_width> |
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[648] | 43 | class TsarIobCluster |
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[450] | 44 | /////////////////////////////////////////////////////////////////////////// |
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| 45 | : public soclib::caba::BaseModule |
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| 46 | { |
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| 47 | |
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[648] | 48 | public: |
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[450] | 49 | |
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[648] | 50 | // Ports |
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| 51 | sc_in<bool> p_clk; |
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| 52 | sc_in<bool> p_resetn; |
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[450] | 53 | |
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[648] | 54 | // Thes two ports are used to connect IOB to IOX nework in top cell |
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| 55 | soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; |
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| 56 | soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; |
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[450] | 57 | |
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[648] | 58 | // These ports are used to connect IOB to RAM network in top cell |
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| 59 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out; |
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| 60 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; |
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[450] | 61 | |
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[648] | 62 | // These ports are used to connect hard IRQ from external peripherals to |
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| 63 | // IOB0 |
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| 64 | sc_in<bool>* p_irq[32]; |
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[550] | 65 | |
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[648] | 66 | // These arrays of ports are used to connect the INT & RAM networks in |
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| 67 | // top cell |
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| 68 | soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; |
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| 69 | soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; |
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| 70 | soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; |
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| 71 | soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; |
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[450] | 72 | |
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[648] | 73 | soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; |
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| 74 | soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; |
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| 75 | soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; |
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| 76 | soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; |
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[450] | 77 | |
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[648] | 78 | // interrupt signals |
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| 79 | sc_signal<bool> signal_false; |
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| 80 | sc_signal<bool> signal_proc_it[8]; |
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| 81 | sc_signal<bool> signal_irq_mdma[8]; |
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| 82 | sc_signal<bool> signal_irq_memc; |
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[450] | 83 | |
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[648] | 84 | // INT network DSPIN signals between DSPIN routers and DSPIN |
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| 85 | // local_crossbars |
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| 86 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; |
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| 87 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; |
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| 88 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; |
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| 89 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; |
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| 90 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; |
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| 91 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; |
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| 92 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; |
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| 93 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; |
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| 94 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; |
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| 95 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; |
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[450] | 96 | |
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[648] | 97 | // INT network VCI signals between VCI components and VCI/DSPIN wrappers |
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| 98 | VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; |
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| 99 | VciSignals<vci_param_int> signal_int_vci_ini_mdma; |
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| 100 | VciSignals<vci_param_int> signal_int_vci_ini_iobx; |
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[450] | 101 | |
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[648] | 102 | VciSignals<vci_param_int> signal_int_vci_tgt_memc; |
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| 103 | VciSignals<vci_param_int> signal_int_vci_tgt_xicu; |
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| 104 | VciSignals<vci_param_int> signal_int_vci_tgt_mdma; |
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| 105 | VciSignals<vci_param_int> signal_int_vci_tgt_iobx; |
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[450] | 106 | |
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[648] | 107 | // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN |
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| 108 | // wrappers |
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| 109 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8]; |
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| 110 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8]; |
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| 111 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i; |
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| 112 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i; |
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| 113 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i; |
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| 114 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i; |
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[450] | 115 | |
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[648] | 116 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t; |
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| 117 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t; |
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| 118 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t; |
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| 119 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t; |
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| 120 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t; |
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| 121 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t; |
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| 122 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t; |
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| 123 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t; |
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[450] | 124 | |
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[648] | 125 | // Coherence DSPIN signals between DSPIN local crossbars and CC |
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| 126 | // components |
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| 127 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; |
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| 128 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; |
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| 129 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; |
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| 130 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; |
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| 131 | DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; |
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| 132 | DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; |
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[450] | 133 | |
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[648] | 134 | // RAM network VCI signals between VCI components and VCI/DSPIN wrappers |
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| 135 | VciSignals<vci_param_ext> signal_ram_vci_ini_memc; |
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| 136 | VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; |
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| 137 | VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; |
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[450] | 138 | |
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[648] | 139 | // RAM network DSPIN signals between VCI/DSPIN wrappers and routers |
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| 140 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; |
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| 141 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; |
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| 142 | DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; |
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| 143 | DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; |
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[450] | 144 | |
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[648] | 145 | ////////////////////////////////////// |
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| 146 | // Hardwate Components (pointers) |
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| 147 | ////////////////////////////////////// |
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| 148 | typedef VciCcVCacheWrapper<vci_param_int, dspin_int_cmd_width, |
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| 149 | dspin_int_rsp_width, GdbServer<Mips32ElIss> > |
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| 150 | VciCcVCacheWrapperType; |
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[450] | 151 | |
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[648] | 152 | typedef VciMemCache<vci_param_int, vci_param_ext, dspin_int_rsp_width, |
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| 153 | dspin_int_cmd_width> VciMemCacheType; |
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[450] | 154 | |
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[648] | 155 | typedef VciDspinInitiatorWrapper<vci_param_int, dspin_int_cmd_width, |
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| 156 | dspin_int_rsp_width> VciIntDspinInitiatorWrapperType; |
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[450] | 157 | |
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[648] | 158 | typedef VciDspinTargetWrapper<vci_param_int, dspin_int_cmd_width, |
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| 159 | dspin_int_rsp_width> VciIntDspinTargetWrapperType; |
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[450] | 160 | |
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[648] | 161 | typedef VciDspinInitiatorWrapper<vci_param_ext, dspin_ram_cmd_width, |
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| 162 | dspin_ram_rsp_width> VciExtDspinInitiatorWrapperType; |
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[450] | 163 | |
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[648] | 164 | typedef VciDspinTargetWrapper<vci_param_ext, dspin_ram_cmd_width, |
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| 165 | dspin_ram_rsp_width> VciExtDspinTargetWrapperType; |
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[450] | 166 | |
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[648] | 167 | VciCcVCacheWrapperType* proc[8]; |
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| 168 | VciIntDspinInitiatorWrapperType* proc_wi[8]; |
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[450] | 169 | |
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[648] | 170 | VciMemCacheType* memc; |
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| 171 | VciIntDspinTargetWrapperType* memc_int_wt; |
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| 172 | VciExtDspinInitiatorWrapperType* memc_ram_wi; |
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[450] | 173 | |
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[648] | 174 | VciXicu<vci_param_int>* xicu; |
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| 175 | VciIntDspinTargetWrapperType* xicu_int_wt; |
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[450] | 176 | |
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[648] | 177 | VciMultiDma<vci_param_int>* mdma; |
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| 178 | VciIntDspinInitiatorWrapperType* mdma_int_wi; |
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| 179 | VciIntDspinTargetWrapperType* mdma_int_wt; |
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[450] | 180 | |
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[648] | 181 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d; |
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| 182 | DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d; |
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| 183 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; |
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| 184 | DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; |
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| 185 | DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; |
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[450] | 186 | |
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[648] | 187 | VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; |
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| 188 | VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; |
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[450] | 189 | |
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[648] | 190 | VciSimpleRam<vci_param_ext>* xram; |
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| 191 | VciExtDspinTargetWrapperType* xram_ram_wt; |
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[450] | 192 | |
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[648] | 193 | DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; |
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| 194 | DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; |
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[450] | 195 | |
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[648] | 196 | // IO Network Components (not instanciated in all clusters) |
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[450] | 197 | |
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[648] | 198 | VciIoBridge<vci_param_int, vci_param_ext>* iob; |
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| 199 | VciIntDspinInitiatorWrapperType* iob_int_wi; |
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| 200 | VciIntDspinTargetWrapperType* iob_int_wt; |
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| 201 | VciExtDspinInitiatorWrapperType* iob_ram_wi; |
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[450] | 202 | |
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[648] | 203 | size_t m_procs; |
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[450] | 204 | |
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[648] | 205 | struct ClusterParams { |
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| 206 | sc_module_name insname; |
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[450] | 207 | |
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[648] | 208 | size_t nb_procs; |
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| 209 | size_t nb_dmas; |
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| 210 | size_t x_id; |
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| 211 | size_t y_id; |
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| 212 | size_t x_size; |
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| 213 | size_t y_size; |
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[450] | 214 | |
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[648] | 215 | const soclib::common::MappingTable &mt_int; |
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| 216 | const soclib::common::MappingTable &mt_ext; |
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| 217 | const soclib::common::MappingTable &mt_iox; |
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[450] | 218 | |
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[648] | 219 | size_t x_width; |
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| 220 | size_t y_width; |
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| 221 | size_t l_width; |
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[450] | 222 | |
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[648] | 223 | size_t int_memc_tgtid; |
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| 224 | size_t int_xicu_tgtid; |
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| 225 | size_t int_mdma_tgtid; |
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| 226 | size_t int_iobx_tgtid; |
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| 227 | size_t int_proc_srcid; |
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| 228 | size_t int_mdma_srcid; |
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| 229 | size_t int_iobx_srcid; |
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| 230 | size_t ext_xram_tgtid; |
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| 231 | size_t ext_memc_srcid; |
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| 232 | size_t ext_iobx_srcid; |
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[450] | 233 | |
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[648] | 234 | size_t memc_ways; |
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| 235 | size_t memc_sets; |
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| 236 | size_t l1_i_ways; |
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| 237 | size_t l1_i_sets; |
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| 238 | size_t l1_d_ways; |
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| 239 | size_t l1_d_sets; |
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| 240 | size_t xram_latency; |
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[450] | 241 | |
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[648] | 242 | const Loader& loader; |
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[450] | 243 | |
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[648] | 244 | uint32_t frozen_cycles; |
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| 245 | uint32_t debug_start_cycle; |
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| 246 | bool memc_debug_ok; |
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| 247 | bool proc_debug_ok; |
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| 248 | bool iob_debug_ok; |
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| 249 | }; |
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[450] | 250 | |
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[648] | 251 | // cluster constructor |
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| 252 | TsarIobCluster(struct ClusterParams& params); |
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| 253 | ~TsarIobCluster(); |
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[450] | 254 | }; |
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| 255 | |
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| 256 | }} |
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| 257 | |
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| 258 | #endif |
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[648] | 259 | |
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| 260 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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