[2] | 1 | /* -*- c++ -*- |
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| 2 | * File : vci_mem_cache_v4.h |
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| 3 | * Date : 26/10/2008 |
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| 4 | * Copyright : UPMC / LIP6 |
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| 5 | * Authors : Alain Greiner / Eric Guthmuller |
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| 6 | * |
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| 7 | * SOCLIB_LGPL_HEADER_BEGIN |
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| 8 | * |
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| 9 | * This file is part of SoCLib, GNU LGPLv2.1. |
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| 10 | * |
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| 11 | * SoCLib is free software; you can redistribute it and/or modify it |
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| 12 | * under the terms of the GNU Lesser General Public License as published |
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| 13 | * by the Free Software Foundation; version 2.1 of the License. |
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| 14 | * |
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| 15 | * SoCLib is distributed in the hope that it will be useful, but |
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| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 18 | * Lesser General Public License for more details. |
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| 19 | * |
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| 20 | * You should have received a copy of the GNU Lesser General Public |
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| 21 | * License along with SoCLib; if not, write to the Free Software |
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| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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| 23 | * 02110-1301 USA |
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| 24 | * |
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| 25 | * SOCLIB_LGPL_HEADER_END |
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| 26 | * |
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| 27 | * Maintainers: alain eric.guthmuller@polytechnique.edu |
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[273] | 28 | * cesar.fuguet-tortolero@lip6.fr |
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[284] | 29 | * alexandre.joannou@lip6.fr |
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[2] | 30 | * |
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| 31 | * Modifications done by Christophe Choichillon on the 7/04/2009: |
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| 32 | * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE |
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| 33 | * - Adding a new VCI target port for the CLEANUP network |
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| 34 | * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP |
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[273] | 35 | * |
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[2] | 36 | * Modifications to do : |
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| 37 | * - Adding new variables used by the CLEANUP FSM |
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| 38 | * |
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| 39 | */ |
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| 40 | |
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| 41 | #ifndef SOCLIB_CABA_MEM_CACHE_V4_H |
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| 42 | #define SOCLIB_CABA_MEM_CACHE_V4_H |
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| 43 | |
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| 44 | #include <inttypes.h> |
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| 45 | #include <systemc> |
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| 46 | #include <list> |
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| 47 | #include <cassert> |
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| 48 | #include "arithmetics.h" |
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| 49 | #include "alloc_elems.h" |
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| 50 | #include "caba_base_module.h" |
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| 51 | #include "vci_target.h" |
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| 52 | #include "vci_initiator.h" |
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| 53 | #include "generic_fifo.h" |
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| 54 | #include "mapping_table.h" |
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| 55 | #include "int_tab.h" |
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| 56 | #include "mem_cache_directory_v4.h" |
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| 57 | #include "xram_transaction_v4.h" |
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| 58 | #include "update_tab_v4.h" |
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| 59 | |
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[273] | 60 | #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab |
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| 61 | #define UPDATE_TAB_LINES 4 // Number of lines in the update tab |
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[2] | 62 | |
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| 63 | namespace soclib { namespace caba { |
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| 64 | using namespace sc_core; |
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| 65 | |
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| 66 | template<typename vci_param> |
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| 67 | class VciMemCacheV4 |
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| 68 | : public soclib::caba::BaseModule |
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| 69 | { |
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| 70 | typedef sc_dt::sc_uint<40> addr_t; |
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| 71 | typedef typename vci_param::fast_addr_t vci_addr_t; |
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| 72 | typedef uint32_t data_t; |
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| 73 | typedef uint32_t tag_t; |
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| 74 | typedef uint32_t size_t; |
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| 75 | typedef uint32_t be_t; |
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| 76 | typedef uint32_t copy_t; |
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| 77 | |
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| 78 | /* States of the TGT_CMD fsm */ |
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| 79 | enum tgt_cmd_fsm_state_e{ |
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| 80 | TGT_CMD_IDLE, |
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| 81 | TGT_CMD_READ, |
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| 82 | TGT_CMD_WRITE, |
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[284] | 83 | TGT_CMD_CAS |
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[2] | 84 | }; |
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| 85 | |
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| 86 | /* States of the TGT_RSP fsm */ |
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| 87 | enum tgt_rsp_fsm_state_e{ |
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| 88 | TGT_RSP_READ_IDLE, |
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| 89 | TGT_RSP_WRITE_IDLE, |
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[284] | 90 | TGT_RSP_CAS_IDLE, |
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[2] | 91 | TGT_RSP_XRAM_IDLE, |
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| 92 | TGT_RSP_INIT_IDLE, |
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| 93 | TGT_RSP_CLEANUP_IDLE, |
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| 94 | TGT_RSP_READ, |
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| 95 | TGT_RSP_WRITE, |
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[284] | 96 | TGT_RSP_CAS, |
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[2] | 97 | TGT_RSP_XRAM, |
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| 98 | TGT_RSP_INIT, |
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[273] | 99 | TGT_RSP_CLEANUP |
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[2] | 100 | }; |
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| 101 | |
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| 102 | /* States of the INIT_CMD fsm */ |
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| 103 | enum init_cmd_fsm_state_e{ |
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| 104 | INIT_CMD_INVAL_IDLE, |
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| 105 | INIT_CMD_INVAL_NLINE, |
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| 106 | INIT_CMD_XRAM_BRDCAST, |
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| 107 | INIT_CMD_UPDT_IDLE, |
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| 108 | INIT_CMD_WRITE_BRDCAST, |
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| 109 | INIT_CMD_UPDT_NLINE, |
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| 110 | INIT_CMD_UPDT_INDEX, |
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| 111 | INIT_CMD_UPDT_DATA, |
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[284] | 112 | INIT_CMD_CAS_UPDT_IDLE, |
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| 113 | INIT_CMD_CAS_BRDCAST, |
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| 114 | INIT_CMD_CAS_UPDT_NLINE, |
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| 115 | INIT_CMD_CAS_UPDT_INDEX, |
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| 116 | INIT_CMD_CAS_UPDT_DATA, |
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| 117 | INIT_CMD_CAS_UPDT_DATA_HIGH |
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[2] | 118 | }; |
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| 119 | |
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| 120 | /* States of the INIT_RSP fsm */ |
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| 121 | enum init_rsp_fsm_state_e{ |
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| 122 | INIT_RSP_IDLE, |
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| 123 | INIT_RSP_UPT_LOCK, |
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| 124 | INIT_RSP_UPT_CLEAR, |
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[273] | 125 | INIT_RSP_END |
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[2] | 126 | }; |
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| 127 | |
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| 128 | /* States of the READ fsm */ |
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| 129 | enum read_fsm_state_e{ |
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| 130 | READ_IDLE, |
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[273] | 131 | READ_DIR_REQ, |
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[2] | 132 | READ_DIR_LOCK, |
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| 133 | READ_DIR_HIT, |
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[273] | 134 | READ_HEAP_REQ, |
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[2] | 135 | READ_HEAP_LOCK, |
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| 136 | READ_HEAP_WRITE, |
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| 137 | READ_HEAP_ERASE, |
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| 138 | READ_HEAP_LAST, |
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| 139 | READ_RSP, |
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| 140 | READ_TRT_LOCK, |
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| 141 | READ_TRT_SET, |
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[273] | 142 | READ_TRT_REQ |
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[2] | 143 | }; |
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| 144 | |
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| 145 | /* States of the WRITE fsm */ |
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| 146 | enum write_fsm_state_e{ |
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| 147 | WRITE_IDLE, |
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| 148 | WRITE_NEXT, |
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[273] | 149 | WRITE_DIR_REQ, |
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[2] | 150 | WRITE_DIR_LOCK, |
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[200] | 151 | WRITE_DIR_READ, |
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[2] | 152 | WRITE_DIR_HIT, |
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| 153 | WRITE_UPT_LOCK, |
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[200] | 154 | WRITE_UPT_HEAP_LOCK, |
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[2] | 155 | WRITE_UPT_REQ, |
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[200] | 156 | WRITE_UPT_NEXT, |
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[2] | 157 | WRITE_UPT_DEC, |
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| 158 | WRITE_RSP, |
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[200] | 159 | WRITE_MISS_TRT_LOCK, |
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| 160 | WRITE_MISS_TRT_DATA, |
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| 161 | WRITE_MISS_TRT_SET, |
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| 162 | WRITE_MISS_XRAM_REQ, |
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| 163 | WRITE_BC_TRT_LOCK, |
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| 164 | WRITE_BC_UPT_LOCK, |
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| 165 | WRITE_BC_DIR_INVAL, |
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| 166 | WRITE_BC_CC_SEND, |
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| 167 | WRITE_BC_XRAM_REQ, |
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[273] | 168 | WRITE_WAIT |
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[2] | 169 | }; |
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| 170 | |
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| 171 | /* States of the IXR_RSP fsm */ |
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| 172 | enum ixr_rsp_fsm_state_e{ |
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| 173 | IXR_RSP_IDLE, |
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| 174 | IXR_RSP_ACK, |
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| 175 | IXR_RSP_TRT_ERASE, |
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[273] | 176 | IXR_RSP_TRT_READ |
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[2] | 177 | }; |
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| 178 | |
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| 179 | /* States of the XRAM_RSP fsm */ |
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| 180 | enum xram_rsp_fsm_state_e{ |
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| 181 | XRAM_RSP_IDLE, |
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| 182 | XRAM_RSP_TRT_COPY, |
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| 183 | XRAM_RSP_TRT_DIRTY, |
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| 184 | XRAM_RSP_DIR_LOCK, |
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| 185 | XRAM_RSP_DIR_UPDT, |
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| 186 | XRAM_RSP_DIR_RSP, |
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| 187 | XRAM_RSP_INVAL_LOCK, |
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| 188 | XRAM_RSP_INVAL_WAIT, |
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| 189 | XRAM_RSP_INVAL, |
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| 190 | XRAM_RSP_WRITE_DIRTY, |
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[273] | 191 | XRAM_RSP_HEAP_REQ, |
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[2] | 192 | XRAM_RSP_HEAP_ERASE, |
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| 193 | XRAM_RSP_HEAP_LAST, |
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[138] | 194 | XRAM_RSP_ERROR_ERASE, |
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[273] | 195 | XRAM_RSP_ERROR_RSP |
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[2] | 196 | }; |
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| 197 | |
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| 198 | /* States of the IXR_CMD fsm */ |
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| 199 | enum ixr_cmd_fsm_state_e{ |
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| 200 | IXR_CMD_READ_IDLE, |
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| 201 | IXR_CMD_WRITE_IDLE, |
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[284] | 202 | IXR_CMD_CAS_IDLE, |
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[2] | 203 | IXR_CMD_XRAM_IDLE, |
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| 204 | IXR_CMD_READ_NLINE, |
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| 205 | IXR_CMD_WRITE_NLINE, |
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[284] | 206 | IXR_CMD_CAS_NLINE, |
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[273] | 207 | IXR_CMD_XRAM_DATA |
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[2] | 208 | }; |
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| 209 | |
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[284] | 210 | /* States of the CAS fsm */ |
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| 211 | enum cas_fsm_state_e{ |
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| 212 | CAS_IDLE, |
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| 213 | CAS_DIR_REQ, |
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| 214 | CAS_DIR_LOCK, |
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| 215 | CAS_DIR_HIT_READ, |
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| 216 | CAS_DIR_HIT_WRITE, |
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| 217 | CAS_UPT_LOCK, |
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| 218 | CAS_UPT_HEAP_LOCK, |
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| 219 | CAS_UPT_REQ, |
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| 220 | CAS_UPT_NEXT, |
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| 221 | CAS_BC_TRT_LOCK, |
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| 222 | CAS_BC_UPT_LOCK, |
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| 223 | CAS_BC_DIR_INVAL, |
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| 224 | CAS_BC_CC_SEND, |
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| 225 | CAS_BC_XRAM_REQ, |
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| 226 | CAS_RSP_FAIL, |
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| 227 | CAS_RSP_SUCCESS, |
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| 228 | CAS_MISS_TRT_LOCK, |
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| 229 | CAS_MISS_TRT_SET, |
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| 230 | CAS_MISS_XRAM_REQ, |
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| 231 | CAS_WAIT |
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[2] | 232 | }; |
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| 233 | |
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| 234 | /* States of the CLEANUP fsm */ |
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| 235 | enum cleanup_fsm_state_e{ |
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| 236 | CLEANUP_IDLE, |
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[273] | 237 | CLEANUP_DIR_REQ, |
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[2] | 238 | CLEANUP_DIR_LOCK, |
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| 239 | CLEANUP_DIR_WRITE, |
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[273] | 240 | CLEANUP_HEAP_REQ, |
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[2] | 241 | CLEANUP_HEAP_LOCK, |
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| 242 | CLEANUP_HEAP_SEARCH, |
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| 243 | CLEANUP_HEAP_CLEAN, |
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| 244 | CLEANUP_HEAP_FREE, |
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| 245 | CLEANUP_UPT_LOCK, |
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| 246 | CLEANUP_UPT_WRITE, |
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| 247 | CLEANUP_WRITE_RSP, |
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[273] | 248 | CLEANUP_RSP |
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[2] | 249 | }; |
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| 250 | |
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| 251 | /* States of the ALLOC_DIR fsm */ |
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| 252 | enum alloc_dir_fsm_state_e{ |
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[273] | 253 | ALLOC_DIR_RESET, |
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[2] | 254 | ALLOC_DIR_READ, |
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| 255 | ALLOC_DIR_WRITE, |
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[284] | 256 | ALLOC_DIR_CAS, |
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[2] | 257 | ALLOC_DIR_CLEANUP, |
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[273] | 258 | ALLOC_DIR_XRAM_RSP |
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[2] | 259 | }; |
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| 260 | |
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| 261 | /* States of the ALLOC_TRT fsm */ |
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| 262 | enum alloc_trt_fsm_state_e{ |
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| 263 | ALLOC_TRT_READ, |
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| 264 | ALLOC_TRT_WRITE, |
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[284] | 265 | ALLOC_TRT_CAS, |
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[2] | 266 | ALLOC_TRT_XRAM_RSP, |
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[273] | 267 | ALLOC_TRT_IXR_RSP |
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[2] | 268 | }; |
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| 269 | |
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| 270 | /* States of the ALLOC_UPT fsm */ |
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| 271 | enum alloc_upt_fsm_state_e{ |
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| 272 | ALLOC_UPT_WRITE, |
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| 273 | ALLOC_UPT_XRAM_RSP, |
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| 274 | ALLOC_UPT_INIT_RSP, |
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| 275 | ALLOC_UPT_CLEANUP, |
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[284] | 276 | ALLOC_UPT_CAS |
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[2] | 277 | }; |
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| 278 | |
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| 279 | /* States of the ALLOC_HEAP fsm */ |
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| 280 | enum alloc_heap_fsm_state_e{ |
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[273] | 281 | ALLOC_HEAP_RESET, |
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[2] | 282 | ALLOC_HEAP_READ, |
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| 283 | ALLOC_HEAP_WRITE, |
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[284] | 284 | ALLOC_HEAP_CAS, |
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[2] | 285 | ALLOC_HEAP_CLEANUP, |
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[273] | 286 | ALLOC_HEAP_XRAM_RSP |
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[2] | 287 | }; |
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| 288 | |
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[284] | 289 | /* transaction type, pktid field */ |
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| 290 | enum transaction_type_e |
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| 291 | { |
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| 292 | // b3 unused |
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| 293 | // b2 READ / NOT READ |
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| 294 | // Si READ |
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| 295 | // b1 DATA / INS |
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| 296 | // b0 UNC / MISS |
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| 297 | // Si NOT READ |
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| 298 | // b1 accÚs table llsc type SW / other |
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| 299 | // b2 WRITE/CAS/LL/SC |
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| 300 | TYPE_READ_DATA_UNC = 0x0, |
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| 301 | TYPE_READ_DATA_MISS = 0x1, |
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| 302 | TYPE_READ_INS_UNC = 0x2, |
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| 303 | TYPE_READ_INS_MISS = 0x3, |
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| 304 | TYPE_WRITE = 0x4, |
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| 305 | TYPE_CAS = 0x5, |
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| 306 | TYPE_LL = 0x6, |
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| 307 | TYPE_SC = 0x7 |
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| 308 | }; |
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| 309 | |
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| 310 | /* SC return values */ |
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| 311 | enum sc_status_type_e |
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| 312 | { |
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| 313 | SC_SUCCESS = 0x00000000, |
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| 314 | SC_FAIL = 0x00000001 |
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| 315 | }; |
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| 316 | |
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[184] | 317 | // debug variables (for each FSM) |
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| 318 | size_t m_debug_start_cycle; |
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| 319 | bool m_debug_ok; |
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| 320 | bool m_debug_global; |
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| 321 | bool m_debug_tgt_cmd_fsm; |
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| 322 | bool m_debug_tgt_rsp_fsm; |
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| 323 | bool m_debug_init_cmd_fsm; |
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| 324 | bool m_debug_init_rsp_fsm; |
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| 325 | bool m_debug_read_fsm; |
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| 326 | bool m_debug_write_fsm; |
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[284] | 327 | bool m_debug_cas_fsm; |
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[184] | 328 | bool m_debug_cleanup_fsm; |
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| 329 | bool m_debug_ixr_cmd_fsm; |
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| 330 | bool m_debug_ixr_rsp_fsm; |
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| 331 | bool m_debug_xram_rsp_fsm; |
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| 332 | bool m_debug_previous_hit; |
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| 333 | size_t m_debug_previous_count; |
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| 334 | |
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[215] | 335 | bool m_monitor_ok; |
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| 336 | vci_addr_t m_monitor_base; |
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| 337 | vci_addr_t m_monitor_length; |
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| 338 | |
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[184] | 339 | // instrumentation counters |
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[273] | 340 | uint32_t m_cpt_cycles; // Counter of cycles |
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| 341 | uint32_t m_cpt_read; // Number of READ transactions |
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| 342 | uint32_t m_cpt_read_miss; // Number of MISS READ |
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| 343 | uint32_t m_cpt_write; // Number of WRITE transactions |
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| 344 | uint32_t m_cpt_write_miss; // Number of MISS WRITE |
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| 345 | uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions |
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| 346 | uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions |
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| 347 | uint32_t m_cpt_update; // Number of UPDATE transactions |
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| 348 | uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt |
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| 349 | uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt |
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| 350 | uint32_t m_cpt_update_mult; // Number of targets for UPDATE |
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| 351 | uint32_t m_cpt_inval; // Number of INVAL transactions |
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| 352 | uint32_t m_cpt_inval_mult; // Number of targets for INVAL |
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| 353 | uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL |
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| 354 | uint32_t m_cpt_cleanup; // Number of CLEANUP transactions |
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| 355 | uint32_t m_cpt_ll; // Number of LL transactions |
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| 356 | uint32_t m_cpt_sc; // Number of SC transactions |
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[284] | 357 | uint32_t m_cpt_cas; // Number of CAS transactions |
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[2] | 358 | |
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[184] | 359 | size_t m_prev_count; |
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| 360 | |
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[2] | 361 | protected: |
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| 362 | |
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| 363 | SC_HAS_PROCESS(VciMemCacheV4); |
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| 364 | |
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| 365 | public: |
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[273] | 366 | sc_in<bool> p_clk; |
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| 367 | sc_in<bool> p_resetn; |
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| 368 | soclib::caba::VciTarget<vci_param> p_vci_tgt; |
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| 369 | soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup; |
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| 370 | soclib::caba::VciInitiator<vci_param> p_vci_ini; |
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| 371 | soclib::caba::VciInitiator<vci_param> p_vci_ixr; |
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[2] | 372 | |
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| 373 | VciMemCacheV4( |
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[273] | 374 | sc_module_name name, // Instance Name |
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[184] | 375 | const soclib::common::MappingTable &mtp, // Mapping table for primary requets |
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| 376 | const soclib::common::MappingTable &mtc, // Mapping table for coherence requets |
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| 377 | const soclib::common::MappingTable &mtx, // Mapping table for XRAM |
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| 378 | const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator) |
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| 379 | const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator) |
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| 380 | const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) |
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| 381 | const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup |
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[273] | 382 | size_t nways, // Number of ways per set |
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[184] | 383 | size_t nsets, // Number of sets |
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| 384 | size_t nwords, // Number of words per line |
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| 385 | size_t heap_size=1024, // Size of the heap |
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| 386 | size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT |
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| 387 | size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT |
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[273] | 388 | size_t debug_start_cycle=0, |
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[184] | 389 | bool debug_ok=false); |
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[2] | 390 | |
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| 391 | ~VciMemCacheV4(); |
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| 392 | |
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| 393 | void print_stats(); |
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[116] | 394 | void print_trace(); |
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[215] | 395 | void copies_monitor(vci_addr_t addr); |
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| 396 | void start_monitor(vci_addr_t addr, vci_addr_t length); |
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| 397 | void stop_monitor(); |
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[116] | 398 | |
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[2] | 399 | private: |
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| 400 | |
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[215] | 401 | void transition(); |
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| 402 | void genMoore(); |
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[222] | 403 | void check_monitor( const char *buf, vci_addr_t addr, data_t data); |
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[215] | 404 | |
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[2] | 405 | // Component attributes |
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[273] | 406 | std::list<soclib::common::Segment> m_seglist; // memory cached into the cache |
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| 407 | std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache |
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[2] | 408 | |
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[273] | 409 | const size_t m_initiators; // Number of initiators |
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| 410 | const size_t m_heap_size; // Size of the heap |
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| 411 | const size_t m_ways; // Number of ways in a set |
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| 412 | const size_t m_sets; // Number of cache sets |
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| 413 | const size_t m_words; // Number of words in a line |
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| 414 | const size_t m_srcid_ixr; // Srcid for requests to XRAM |
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| 415 | const size_t m_srcid_ini; // Srcid for requests to processors |
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[2] | 416 | |
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[273] | 417 | uint32_t m_transaction_tab_lines; |
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| 418 | TransactionTab m_transaction_tab; // xram transaction table |
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| 419 | uint32_t m_update_tab_lines; |
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| 420 | UpdateTab m_update_tab; // pending update & invalidate |
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| 421 | CacheDirectory m_cache_directory; // data cache directory |
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[289] | 422 | CacheData m_cache_data; // data array[set][way][word] |
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[273] | 423 | HeapDirectory m_heap; // heap for copies |
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| 424 | |
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[2] | 425 | // adress masks |
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[273] | 426 | const soclib::common::AddressMaskingTable<vci_addr_t> m_x; |
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| 427 | const soclib::common::AddressMaskingTable<vci_addr_t> m_y; |
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| 428 | const soclib::common::AddressMaskingTable<vci_addr_t> m_z; |
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| 429 | const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; |
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[2] | 430 | |
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[82] | 431 | // broadcast address |
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[273] | 432 | vci_addr_t m_broadcast_address; |
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[82] | 433 | |
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[2] | 434 | ////////////////////////////////////////////////// |
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| 435 | // Others registers |
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| 436 | ////////////////////////////////////////////////// |
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[273] | 437 | sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line |
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| 438 | sc_signal<size_t> xxx_count; |
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[2] | 439 | |
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| 440 | ////////////////////////////////////////////////// |
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| 441 | // Registers controlled by the TGT_CMD fsm |
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| 442 | ////////////////////////////////////////////////// |
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| 443 | |
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| 444 | // Fifo between TGT_CMD fsm and READ fsm |
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| 445 | GenericFifo<uint64_t> m_cmd_read_addr_fifo; |
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| 446 | GenericFifo<size_t> m_cmd_read_length_fifo; |
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| 447 | GenericFifo<size_t> m_cmd_read_srcid_fifo; |
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| 448 | GenericFifo<size_t> m_cmd_read_trdid_fifo; |
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| 449 | GenericFifo<size_t> m_cmd_read_pktid_fifo; |
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| 450 | |
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[273] | 451 | // Fifo between TGT_CMD fsm and WRITE fsm |
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[2] | 452 | GenericFifo<uint64_t> m_cmd_write_addr_fifo; |
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| 453 | GenericFifo<bool> m_cmd_write_eop_fifo; |
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| 454 | GenericFifo<size_t> m_cmd_write_srcid_fifo; |
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| 455 | GenericFifo<size_t> m_cmd_write_trdid_fifo; |
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| 456 | GenericFifo<size_t> m_cmd_write_pktid_fifo; |
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| 457 | GenericFifo<data_t> m_cmd_write_data_fifo; |
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[273] | 458 | GenericFifo<be_t> m_cmd_write_be_fifo; |
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[2] | 459 | |
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[284] | 460 | // Fifo between TGT_CMD fsm and CAS fsm |
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| 461 | GenericFifo<uint64_t> m_cmd_cas_addr_fifo; |
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| 462 | GenericFifo<bool> m_cmd_cas_eop_fifo; |
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| 463 | GenericFifo<size_t> m_cmd_cas_srcid_fifo; |
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| 464 | GenericFifo<size_t> m_cmd_cas_trdid_fifo; |
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| 465 | GenericFifo<size_t> m_cmd_cas_pktid_fifo; |
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| 466 | GenericFifo<data_t> m_cmd_cas_wdata_fifo; |
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[2] | 467 | |
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| 468 | sc_signal<int> r_tgt_cmd_fsm; |
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| 469 | |
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[245] | 470 | size_t m_nseg; |
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| 471 | size_t m_ncseg; |
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[2] | 472 | soclib::common::Segment **m_seg; |
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| 473 | soclib::common::Segment **m_cseg; |
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| 474 | /////////////////////////////////////////////////////// |
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| 475 | // Registers controlled by the READ fsm |
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| 476 | /////////////////////////////////////////////////////// |
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| 477 | |
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[273] | 478 | sc_signal<int> r_read_fsm; // FSM state |
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| 479 | sc_signal<size_t> r_read_copy; // Srcid of the first copy |
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| 480 | sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy |
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| 481 | sc_signal<bool> r_read_copy_inst; // Type of the first copy |
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| 482 | sc_signal<tag_t> r_read_tag; // cache line tag (in directory) |
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| 483 | sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) |
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| 484 | sc_signal<bool> r_read_lock; // lock bit (in directory) |
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| 485 | sc_signal<bool> r_read_dirty; // dirty bit (in directory) |
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| 486 | sc_signal<size_t> r_read_count; // number of copies |
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| 487 | sc_signal<size_t> r_read_ptr; // pointer to the heap |
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| 488 | sc_signal<data_t> * r_read_data; // data (one cache line) |
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| 489 | sc_signal<size_t> r_read_way; // associative way (in cache) |
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| 490 | sc_signal<size_t> r_read_trt_index; // Transaction Table index |
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| 491 | sc_signal<size_t> r_read_next_ptr; // Next entry to point to |
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| 492 | sc_signal<bool> r_read_last_free; // Last free entry |
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[2] | 493 | |
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[273] | 494 | // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
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| 495 | sc_signal<bool> r_read_to_ixr_cmd_req; // valid request |
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| 496 | sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index |
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| 497 | sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table |
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[2] | 498 | |
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| 499 | // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) |
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[273] | 500 | sc_signal<bool> r_read_to_tgt_rsp_req; // valid request |
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| 501 | sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid |
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| 502 | sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid |
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| 503 | sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid |
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| 504 | sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) |
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| 505 | sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response |
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| 506 | sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response |
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[2] | 507 | |
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| 508 | /////////////////////////////////////////////////////////////// |
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| 509 | // Registers controlled by the WRITE fsm |
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| 510 | /////////////////////////////////////////////////////////////// |
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| 511 | |
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[273] | 512 | sc_signal<int> r_write_fsm; // FSM state |
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| 513 | sc_signal<addr_t> r_write_address; // first word address |
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| 514 | sc_signal<size_t> r_write_word_index; // first word index in line |
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| 515 | sc_signal<size_t> r_write_word_count; // number of words in line |
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| 516 | sc_signal<size_t> r_write_srcid; // transaction srcid |
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| 517 | sc_signal<size_t> r_write_trdid; // transaction trdid |
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| 518 | sc_signal<size_t> r_write_pktid; // transaction pktid |
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| 519 | sc_signal<data_t> * r_write_data; // data (one cache line) |
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| 520 | sc_signal<be_t> * r_write_be; // one byte enable per word |
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| 521 | sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) |
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| 522 | sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) |
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| 523 | sc_signal<bool> r_write_lock; // lock bit (in directory) |
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| 524 | sc_signal<tag_t> r_write_tag; // cache line tag (in directory) |
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| 525 | sc_signal<size_t> r_write_copy; // first owner of the line |
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| 526 | sc_signal<size_t> r_write_copy_cache; // first owner of the line |
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| 527 | sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? |
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| 528 | sc_signal<size_t> r_write_count; // number of copies |
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| 529 | sc_signal<size_t> r_write_ptr; // pointer to the heap |
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| 530 | sc_signal<size_t> r_write_next_ptr; // next pointer to the heap |
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| 531 | sc_signal<bool> r_write_to_dec; // need to decrement update counter |
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| 532 | sc_signal<size_t> r_write_way; // way of the line |
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| 533 | sc_signal<size_t> r_write_trt_index; // index in Transaction Table |
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| 534 | sc_signal<size_t> r_write_upt_index; // index in Update Table |
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[2] | 535 | |
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| 536 | // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) |
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[273] | 537 | sc_signal<bool> r_write_to_tgt_rsp_req; // valid request |
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| 538 | sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid |
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| 539 | sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid |
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| 540 | sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid |
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[2] | 541 | |
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[273] | 542 | // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) |
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| 543 | sc_signal<bool> r_write_to_ixr_cmd_req; // valid request |
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| 544 | sc_signal<bool> r_write_to_ixr_cmd_write; // write request |
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| 545 | sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index |
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| 546 | sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data |
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| 547 | sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table |
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[2] | 548 | |
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| 549 | // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
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[273] | 550 | sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request |
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| 551 | sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request |
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| 552 | sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index |
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| 553 | sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table |
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| 554 | sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line) |
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| 555 | sc_signal<be_t> * r_write_to_init_cmd_be; // word enable |
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| 556 | sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line |
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| 557 | sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line |
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| 558 | GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type |
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| 559 | GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids |
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[283] | 560 | #if L1_MULTI_CACHE |
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[273] | 561 | GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids |
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[283] | 562 | #endif |
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[2] | 563 | |
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| 564 | // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) |
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[273] | 565 | sc_signal<bool> r_write_to_init_rsp_req; // valid request |
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| 566 | sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table |
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[2] | 567 | |
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| 568 | ///////////////////////////////////////////////////////// |
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| 569 | // Registers controlled by INIT_RSP fsm |
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| 570 | ////////////////////////////////////////////////////////// |
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| 571 | |
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[273] | 572 | sc_signal<int> r_init_rsp_fsm; // FSM state |
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| 573 | sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table |
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| 574 | sc_signal<size_t> r_init_rsp_srcid; // pending write srcid |
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| 575 | sc_signal<size_t> r_init_rsp_trdid; // pending write trdid |
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| 576 | sc_signal<size_t> r_init_rsp_pktid; // pending write pktid |
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| 577 | sc_signal<addr_t> r_init_rsp_nline; // pending write nline |
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[2] | 578 | |
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| 579 | // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) |
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[273] | 580 | sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request |
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| 581 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid |
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| 582 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid |
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| 583 | sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid |
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[2] | 584 | |
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| 585 | /////////////////////////////////////////////////////// |
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| 586 | // Registers controlled by CLEANUP fsm |
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| 587 | /////////////////////////////////////////////////////// |
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| 588 | |
---|
[273] | 589 | sc_signal<int> r_cleanup_fsm; // FSM state |
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| 590 | sc_signal<size_t> r_cleanup_srcid; // transaction srcid |
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| 591 | sc_signal<size_t> r_cleanup_trdid; // transaction trdid |
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| 592 | sc_signal<size_t> r_cleanup_pktid; // transaction pktid |
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| 593 | sc_signal<addr_t> r_cleanup_nline; // cache line index |
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[2] | 594 | |
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[273] | 595 | sc_signal<copy_t> r_cleanup_copy; // first copy |
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| 596 | sc_signal<copy_t> r_cleanup_copy_cache; // first copy |
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| 597 | sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy |
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| 598 | sc_signal<copy_t> r_cleanup_count; // number of copies |
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| 599 | sc_signal<size_t> r_cleanup_ptr; // pointer to the heap |
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| 600 | sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap |
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| 601 | sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry |
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| 602 | sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry |
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| 603 | sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry |
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| 604 | sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap |
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| 605 | sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) |
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| 606 | sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) |
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| 607 | sc_signal<bool> r_cleanup_lock; // lock bit (in directory) |
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| 608 | sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) |
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| 609 | sc_signal<size_t> r_cleanup_way; // associative way (in cache) |
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[2] | 610 | |
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[273] | 611 | sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response |
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| 612 | sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp |
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| 613 | sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp |
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| 614 | sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp |
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[2] | 615 | |
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[273] | 616 | sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) |
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[2] | 617 | |
---|
| 618 | // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) |
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[273] | 619 | sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request |
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| 620 | sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid |
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| 621 | sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid |
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| 622 | sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid |
---|
[2] | 623 | |
---|
| 624 | /////////////////////////////////////////////////////// |
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[284] | 625 | // Registers controlled by CAS fsm |
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[2] | 626 | /////////////////////////////////////////////////////// |
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| 627 | |
---|
[284] | 628 | sc_signal<int> r_cas_fsm; // FSM state |
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| 629 | sc_signal<data_t> r_cas_wdata; // write data word |
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| 630 | sc_signal<data_t> * r_cas_rdata; // read data word |
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| 631 | sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing |
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| 632 | sc_signal<size_t> r_cas_cpt; // size of command |
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| 633 | sc_signal<copy_t> r_cas_copy; // Srcid of the first copy |
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| 634 | sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy |
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| 635 | sc_signal<bool> r_cas_copy_inst; // Type of the first copy |
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| 636 | sc_signal<size_t> r_cas_count; // number of copies |
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| 637 | sc_signal<size_t> r_cas_ptr; // pointer to the heap |
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| 638 | sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap |
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| 639 | sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory) |
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| 640 | sc_signal<bool> r_cas_dirty; // dirty bit (in directory) |
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| 641 | sc_signal<size_t> r_cas_way; // way in directory |
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| 642 | sc_signal<size_t> r_cas_set; // set in directory |
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| 643 | sc_signal<data_t> r_cas_tag; // cache line tag (in directory) |
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| 644 | sc_signal<size_t> r_cas_trt_index; // Transaction Table index |
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| 645 | sc_signal<size_t> r_cas_upt_index; // Update Table index |
---|
[2] | 646 | |
---|
[284] | 647 | // Buffer between CAS fsm and INIT_CMD fsm (XRAM read) |
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| 648 | sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request |
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| 649 | sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index |
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| 650 | sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table |
---|
| 651 | sc_signal<bool> r_cas_to_ixr_cmd_write; // write request |
---|
| 652 | sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data |
---|
[2] | 653 | |
---|
| 654 | |
---|
[284] | 655 | // Buffer between CAS fsm and TGT_RSP fsm |
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| 656 | sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request |
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| 657 | sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word |
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| 658 | sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid |
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| 659 | sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid |
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| 660 | sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid |
---|
[2] | 661 | |
---|
[284] | 662 | // Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches) |
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| 663 | sc_signal<bool> r_cas_to_init_cmd_multi_req; // valid request |
---|
| 664 | sc_signal<bool> r_cas_to_init_cmd_brdcast_req; // brdcast request |
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| 665 | sc_signal<addr_t> r_cas_to_init_cmd_nline; // cache line index |
---|
| 666 | sc_signal<size_t> r_cas_to_init_cmd_trdid; // index in Update Table |
---|
| 667 | sc_signal<data_t> r_cas_to_init_cmd_wdata; // data (one word) |
---|
| 668 | sc_signal<bool> r_cas_to_init_cmd_is_long; // it is a 64 bits CAS |
---|
| 669 | sc_signal<data_t> r_cas_to_init_cmd_wdata_high; // data high (one word) |
---|
| 670 | sc_signal<size_t> r_cas_to_init_cmd_index; // index of the word in line |
---|
| 671 | GenericFifo<bool> m_cas_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 672 | GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo; // fifo for srcids |
---|
[283] | 673 | #if L1_MULTI_CACHE |
---|
[284] | 674 | GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids |
---|
[283] | 675 | #endif |
---|
[2] | 676 | |
---|
[284] | 677 | // Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry) |
---|
| 678 | sc_signal<bool> r_cas_to_init_rsp_req; // valid request |
---|
| 679 | sc_signal<size_t> r_cas_to_init_rsp_upt_index; // index in update table |
---|
[2] | 680 | |
---|
| 681 | //////////////////////////////////////////////////// |
---|
| 682 | // Registers controlled by the IXR_RSP fsm |
---|
| 683 | //////////////////////////////////////////////////// |
---|
| 684 | |
---|
[273] | 685 | sc_signal<int> r_ixr_rsp_fsm; // FSM state |
---|
| 686 | sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index |
---|
| 687 | sc_signal<size_t> r_ixr_rsp_cpt; // word counter |
---|
[2] | 688 | |
---|
| 689 | // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) |
---|
[273] | 690 | sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready |
---|
[2] | 691 | |
---|
| 692 | //////////////////////////////////////////////////// |
---|
| 693 | // Registers controlled by the XRAM_RSP fsm |
---|
| 694 | //////////////////////////////////////////////////// |
---|
| 695 | |
---|
[273] | 696 | sc_signal<int> r_xram_rsp_fsm; // FSM state |
---|
| 697 | sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index |
---|
| 698 | TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer |
---|
| 699 | sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate |
---|
| 700 | sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit |
---|
| 701 | sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit |
---|
| 702 | sc_signal<size_t> r_xram_rsp_victim_way; // victim line way |
---|
| 703 | sc_signal<size_t> r_xram_rsp_victim_set; // victim line set |
---|
| 704 | sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index |
---|
| 705 | sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy |
---|
| 706 | sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy |
---|
| 707 | sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy |
---|
| 708 | sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies |
---|
| 709 | sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap |
---|
| 710 | sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data |
---|
| 711 | sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index |
---|
| 712 | sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap |
---|
[2] | 713 | |
---|
| 714 | // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) |
---|
[273] | 715 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request |
---|
| 716 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid |
---|
| 717 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid |
---|
| 718 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid |
---|
| 719 | sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) |
---|
| 720 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index |
---|
| 721 | sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response |
---|
| 722 | sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester |
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[2] | 723 | |
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[273] | 724 | // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) |
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| 725 | sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request |
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| 726 | sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request |
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| 727 | sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index; |
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| 728 | sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry |
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| 729 | GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type |
---|
| 730 | GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids |
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[283] | 731 | #if L1_MULTI_CACHE |
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[273] | 732 | GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids |
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[283] | 733 | #endif |
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[2] | 734 | |
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| 735 | // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) |
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[273] | 736 | sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request |
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| 737 | sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index |
---|
| 738 | sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data |
---|
| 739 | sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table |
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[2] | 740 | |
---|
| 741 | //////////////////////////////////////////////////// |
---|
| 742 | // Registers controlled by the IXR_CMD fsm |
---|
| 743 | //////////////////////////////////////////////////// |
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| 744 | |
---|
[273] | 745 | sc_signal<int> r_ixr_cmd_fsm; |
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| 746 | sc_signal<size_t> r_ixr_cmd_cpt; |
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[2] | 747 | |
---|
| 748 | //////////////////////////////////////////////////// |
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| 749 | // Registers controlled by TGT_RSP fsm |
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| 750 | //////////////////////////////////////////////////// |
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| 751 | |
---|
[273] | 752 | sc_signal<int> r_tgt_rsp_fsm; |
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| 753 | sc_signal<size_t> r_tgt_rsp_cpt; |
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[2] | 754 | |
---|
| 755 | //////////////////////////////////////////////////// |
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| 756 | // Registers controlled by INIT_CMD fsm |
---|
| 757 | //////////////////////////////////////////////////// |
---|
| 758 | |
---|
[273] | 759 | sc_signal<int> r_init_cmd_fsm; |
---|
[2] | 760 | sc_signal<size_t> r_init_cmd_cpt; |
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| 761 | sc_signal<bool> r_init_cmd_inst; |
---|
| 762 | |
---|
| 763 | //////////////////////////////////////////////////// |
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| 764 | // Registers controlled by ALLOC_DIR fsm |
---|
| 765 | //////////////////////////////////////////////////// |
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| 766 | |
---|
[273] | 767 | sc_signal<int> r_alloc_dir_fsm; |
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| 768 | sc_signal<unsigned> r_alloc_dir_reset_cpt; |
---|
[2] | 769 | |
---|
| 770 | //////////////////////////////////////////////////// |
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| 771 | // Registers controlled by ALLOC_TRT fsm |
---|
| 772 | //////////////////////////////////////////////////// |
---|
| 773 | |
---|
[273] | 774 | sc_signal<int> r_alloc_trt_fsm; |
---|
[2] | 775 | |
---|
| 776 | //////////////////////////////////////////////////// |
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| 777 | // Registers controlled by ALLOC_UPT fsm |
---|
| 778 | //////////////////////////////////////////////////// |
---|
| 779 | |
---|
[273] | 780 | sc_signal<int> r_alloc_upt_fsm; |
---|
[2] | 781 | |
---|
| 782 | //////////////////////////////////////////////////// |
---|
| 783 | // Registers controlled by ALLOC_HEAP fsm |
---|
| 784 | //////////////////////////////////////////////////// |
---|
| 785 | |
---|
[273] | 786 | sc_signal<int> r_alloc_heap_fsm; |
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| 787 | sc_signal<unsigned> r_alloc_heap_reset_cpt; |
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[2] | 788 | }; // end class VciMemCacheV4 |
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| 789 | |
---|
| 790 | }} |
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| 791 | |
---|
| 792 | #endif |
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| 793 | |
---|
| 794 | // Local Variables: |
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[141] | 795 | // tab-width: 2 |
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| 796 | // c-basic-offset: 2 |
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[2] | 797 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 798 | // indent-tabs-mode: nil |
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| 799 | // End: |
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| 800 | |
---|
[273] | 801 | // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 |
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[2] | 802 | |
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