Context Navigation

← Previous Revision
Next Revision →
Normal
Revision Log

tsar_iob_cluster.h

Last change on this file was 1051, checked in by alain, 7 years ago
Replace the vci_mwmr_dma hardware component by the vci_multi_dma component.
File size: 12.0 KB

Rev	Line
[450]	1	//////////////////////////////////////////////////////////////////////////////
	2	// File: tsar_iob_cluster.h
	3	// Author: Alain Greiner
	4	// Copyright: UPMC/LIP6
	5	// Date : april 2013
	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
	8
	9	#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H
	10	#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H
	11
	12	#include <systemc>
	13	#include <sys/time.h>
	14	#include <iostream>
	15	#include <sstream>
	16	#include <cstdlib>
	17	#include <cstdarg>
	18
	19	#include "gdbserver.h"
	20	#include "mapping_table.h"
	21	#include "mips32.h"
	22	#include "vci_simple_ram.h"
	23	#include "vci_xicu.h"
[693]	24	#include "vci_local_crossbar.h"
[450]	25	#include "dspin_local_crossbar.h"
	26	#include "vci_dspin_initiator_wrapper.h"
	27	#include "vci_dspin_target_wrapper.h"
[718]	28	#include "dspin_router.h"
[1051]	29	#include "vci_multi_dma.h"
[450]	30	#include "vci_mem_cache.h"
	31	#include "vci_cc_vcache_wrapper.h"
	32	#include "vci_io_bridge.h"
	33
[693]	34	namespace soclib { namespace caba {
[450]	35
	36	///////////////////////////////////////////////////////////////////////////
	37	template<typename vci_param_int,
	38	typename vci_param_ext,
	39	size_t dspin_int_cmd_width,
	40	size_t dspin_int_rsp_width,
	41	size_t dspin_ram_cmd_width,
	42	size_t dspin_ram_rsp_width>
	43	class TsarIobCluster
	44	///////////////////////////////////////////////////////////////////////////
	45	: public soclib::caba::BaseModule
	46	{
	47
	48	public:
	49
[693]	50	// Ports
	51	sc_in<bool> p_clk;
	52	sc_in<bool> p_resetn;
[450]	53
[550]	54	// Thes two ports are used to connect IOB to IOX nework in top cell
	55	soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini;
	56	soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt;
[450]	57
[550]	58	// These arrays of ports are used to connect the INT & RAM networks in top cell
[1002]	59	soclib::caba::DspinOutput<dspin_int_cmd_width>* p_dspin_int_cmd_out;
	60	soclib::caba::DspinInput<dspin_int_cmd_width>* p_dspin_int_cmd_in;
	61	soclib::caba::DspinOutput<dspin_int_rsp_width>* p_dspin_int_rsp_out;
	62	soclib::caba::DspinInput<dspin_int_rsp_width>* p_dspin_int_rsp_in;
	63	soclib::caba::DspinOutput<dspin_int_cmd_width>* p_dspin_int_m2p_out;
	64	soclib::caba::DspinInput<dspin_int_cmd_width>* p_dspin_int_m2p_in;
	65	soclib::caba::DspinOutput<dspin_int_rsp_width>* p_dspin_int_p2m_out;
	66	soclib::caba::DspinInput<dspin_int_rsp_width>* p_dspin_int_p2m_in;
	67	soclib::caba::DspinOutput<dspin_int_cmd_width>* p_dspin_int_cla_out;
	68	soclib::caba::DspinInput<dspin_int_cmd_width>* p_dspin_int_cla_in;
[450]	69
[693]	70	soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out;
	71	soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in;
[450]	72	soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out;
	73	soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in;
	74
	75	// interrupt signals
[693]	76	sc_signal<bool> signal_false;
[959]	77	sc_signal<bool> signal_proc_it[32];
[1051]	78	sc_signal<bool> signal_irq_mdma[8];
[693]	79	sc_signal<bool> signal_irq_memc;
	80
	81	// INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars
	82	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d;
	83	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d;
[1002]	84
	85	DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d;
	86	DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d;
	87
[693]	88	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c;
	89	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c;
[1002]	90
[693]	91	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c;
	92	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c;
[450]	93
[1002]	94	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_l2g_c;
	95	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_g2l_c;
	96
[693]	97	// INT network VCI signals between VCI components and VCI local crossbar
	98	VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
[1051]	99	VciSignals<vci_param_int> signal_int_vci_ini_mdma;
[693]	100	VciSignals<vci_param_int> signal_int_vci_ini_iobx;
[450]	101
[693]	102	VciSignals<vci_param_int> signal_int_vci_tgt_memc;
	103	VciSignals<vci_param_int> signal_int_vci_tgt_xicu;
[1051]	104	VciSignals<vci_param_int> signal_int_vci_tgt_mdma;
[693]	105	VciSignals<vci_param_int> signal_int_vci_tgt_iobx;
[450]	106
[693]	107	VciSignals<vci_param_int> signal_int_vci_l2g;
	108	VciSignals<vci_param_int> signal_int_vci_g2l;
[450]	109
[693]	110	// Coherence DSPIN signals between DSPIN local crossbars and CC components
	111	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc;
[1002]	112	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_memc;
[693]	113	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
	114	DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
[1002]	115	DspinSignals<dspin_int_cmd_width> signal_int_dspin_cla_proc[8];
[693]	116	DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
[450]	117
[693]	118	// RAM network VCI signals between VCI components and VCI/DSPIN wrappers
	119	VciSignals<vci_param_ext> signal_ram_vci_ini_memc;
	120	VciSignals<vci_param_ext> signal_ram_vci_ini_iobx;
	121	VciSignals<vci_param_ext> signal_ram_vci_tgt_xram;
[450]	122
[718]	123	// RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar
	124	// and routers
[693]	125	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
	126	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
	127	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
	128	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
[718]	129	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i;
	130	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i;
	131	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar;
	132	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar;
	133	DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false;
	134	DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false;
[450]	135
	136	//////////////////////////////////////
	137	// Hardwate Components (pointers)
	138	//////////////////////////////////////
	139	VciCcVCacheWrapper<vci_param_int,
	140	dspin_int_cmd_width,
	141	dspin_int_rsp_width,
	142	GdbServer<Mips32ElIss> >* proc[8];
	143
	144	VciMemCache<vci_param_int,
	145	vci_param_ext,
	146	dspin_int_rsp_width,
	147	dspin_int_cmd_width>* memc;
	148
	149	VciDspinInitiatorWrapper<vci_param_ext,
	150	dspin_ram_cmd_width,
	151	dspin_ram_rsp_width>* memc_ram_wi;
	152
[693]	153	VciXicu<vci_param_int>* xicu;
[450]	154
[1051]	155	VciMultiDma<vci_param_int>* mdma;
[450]	156
[693]	157	VciLocalCrossbar<vci_param_int>* int_xbar_d;
	158
[450]	159	VciDspinInitiatorWrapper<vci_param_int,
	160	dspin_int_cmd_width,
[693]	161	dspin_int_rsp_width>* int_wi_gate_d;
[450]	162
	163	VciDspinTargetWrapper<vci_param_int,
	164	dspin_int_cmd_width,
[693]	165	dspin_int_rsp_width>* int_wt_gate_d;
[450]	166
	167	DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c;
	168	DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c;
[468]	169	DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c;
[450]	170
[1002]	171	DspinRouter<dspin_int_cmd_width>* int_router_cmd;
	172	DspinRouter<dspin_int_rsp_width>* int_router_rsp;
	173	DspinRouter<dspin_int_cmd_width>* int_router_m2p;
	174	DspinRouter<dspin_int_rsp_width>* int_router_p2m;
	175	DspinRouter<dspin_int_cmd_width>* int_router_cla;
[450]	176
	177	VciSimpleRam<vci_param_ext>* xram;
	178
	179	VciDspinTargetWrapper<vci_param_ext,
	180	dspin_ram_cmd_width,
	181	dspin_ram_rsp_width>* xram_ram_wt;
[693]	182
[718]	183	DspinRouter<dspin_ram_cmd_width>* ram_router_cmd;
	184	DspinRouter<dspin_ram_rsp_width>* ram_router_rsp;
[450]	185
[1050]	186	// IO Network Components (not instanciated in all clusters)
	187
[718]	188	DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd;
	189	DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp;
	190
[450]	191	VciIoBridge<vci_param_int,
	192	vci_param_ext>* iob;
	193
	194	VciDspinInitiatorWrapper<vci_param_ext,
	195	dspin_ram_cmd_width,
	196	dspin_ram_rsp_width>* iob_ram_wi;
[718]	197
[450]	198	// cluster constructor
[693]	199	TsarIobCluster( sc_module_name insname,
[450]	200	size_t nb_procs,
	201	size_t x, // x coordinate
	202	size_t y, // y coordinate
	203	size_t xmax,
	204	size_t ymax,
	205
	206	const soclib::common::MappingTable &mt_int,
	207	const soclib::common::MappingTable &mt_ext,
	208	const soclib::common::MappingTable &mt_iox,
	209
[959]	210	size_t x_width, // x field bits
	211	size_t y_width, // y field bits
	212	size_t l_width, // l field bits
	213	size_t p_width, // p field bits
[450]	214
[718]	215	size_t int_memc_tgt_id,
	216	size_t int_xicu_tgt_id,
[1051]	217	size_t int_mdma_tgt_id,
[718]	218	size_t int_iobx_tgt_id,
	219	size_t int_proc_ini_id,
[1051]	220	size_t int_mdma_ini_id,
[718]	221	size_t int_iobx_ini_id,
[450]	222
[718]	223	size_t ram_xram_tgt_id,
	224	size_t ram_memc_ini_id,
	225	size_t ram_iobx_ini_id,
[450]	226
[718]	227	bool is_io,
	228	size_t iox_iobx_tgt_id,
	229	size_t iox_iobx_ini_id,
[450]	230
	231	size_t memc_ways,
	232	size_t memc_sets,
	233	size_t l1_i_ways,
	234	size_t l1_i_sets,
	235	size_t l1_d_ways,
[693]	236	size_t l1_d_sets,
[450]	237	size_t xram_latency,
[959]	238	size_t xcu_nb_hwi,
	239	size_t xcu_nb_pti,
	240	size_t xcu_nb_wti,
	241	size_t xcu_nb_irq,
[450]	242
[972]	243	size_t coproc_type,
	244
[959]	245	const Loader &loader, // loader for XRAM
[450]	246
	247	uint32_t frozen_cycles,
[1030]	248	bool debug_ok,
	249	uint32_t debug_start_cycle,
	250	uint32_t debug_proc_id,
	251	uint32_t debug_memc_id,
	252	bool debug_iob );
[450]	253
[718]	254	protected:
	255
	256	SC_HAS_PROCESS(TsarIobCluster);
	257
	258	void init();
	259
[450]	260	};
	261
	262	}}
	263
	264	#endif
[718]	265
	266	// Local Variables:
	267	// tab-width: 3
	268	// c-basic-offset: 3
	269	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	270	// indent-tabs-mode: nil
	271	// End:
	272
	273	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
	274	//

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

Download in other formats: