[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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| 7 | ////////////////////////////////////////////////////////////////////////////// |
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| 8 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 9 | // These two clusters contain 6 extra components: |
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| 10 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 11 | // - 3 vci_dspin_wrapper for the IOB. |
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| 12 | // - 2 dspin_local_crossbar for commands and responses. |
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| 13 | ////////////////////////////////////////////////////////////////////////////// |
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| 14 | |
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| 15 | #include "../include/tsar_iob_cluster.h" |
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| 16 | |
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| 17 | namespace soclib { namespace caba { |
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| 18 | |
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| 19 | ////////////////////////////////////////////////////////////////////////// |
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| 20 | // Constructor |
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| 21 | ////////////////////////////////////////////////////////////////////////// |
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| 22 | template<typename vci_param_int, |
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| 23 | typename vci_param_ext, |
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| 24 | size_t dspin_int_cmd_width, |
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| 25 | size_t dspin_int_rsp_width, |
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| 26 | size_t dspin_ram_cmd_width, |
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| 27 | size_t dspin_ram_rsp_width> |
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| 28 | TsarIobCluster<vci_param_int, |
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| 29 | vci_param_ext, |
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| 30 | dspin_int_cmd_width, |
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| 31 | dspin_int_rsp_width, |
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| 32 | dspin_ram_cmd_width, |
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| 33 | dspin_ram_rsp_width>::TsarIobCluster( |
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| 34 | ////////////////////////////////////////////////////////////////////////// |
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| 35 | sc_module_name insname, |
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| 36 | size_t nb_procs, |
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| 37 | size_t nb_dmas, |
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| 38 | size_t x_id, |
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| 39 | size_t y_id, |
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| 40 | size_t xmax, |
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| 41 | size_t ymax, |
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| 42 | |
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| 43 | const soclib::common::MappingTable &mt_int, |
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| 44 | const soclib::common::MappingTable &mt_ram, |
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| 45 | const soclib::common::MappingTable &mt_iox, |
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| 46 | |
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| 47 | size_t x_width, |
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| 48 | size_t y_width, |
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| 49 | size_t l_width, |
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| 50 | |
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[550] | 51 | size_t memc_int_tgtid, // local index |
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| 52 | size_t xicu_int_tgtid, // local index |
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| 53 | size_t mdma_int_tgtid, // local index |
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| 54 | size_t iobx_int_tgtid, // local index |
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[450] | 55 | |
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[550] | 56 | size_t proc_int_srcid, // local index |
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| 57 | size_t mdma_int_srcid, // local index |
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| 58 | size_t iobx_int_srcid, // local index |
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[450] | 59 | |
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[550] | 60 | size_t xram_ram_tgtid, // local index |
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[450] | 61 | |
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[550] | 62 | size_t memc_ram_srcid, // local index |
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| 63 | size_t iobx_ram_srcid, // local index |
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[450] | 64 | |
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| 65 | size_t memc_ways, |
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| 66 | size_t memc_sets, |
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| 67 | size_t l1_i_ways, |
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| 68 | size_t l1_i_sets, |
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| 69 | size_t l1_d_ways, |
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| 70 | size_t l1_d_sets, |
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| 71 | size_t xram_latency, |
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[714] | 72 | size_t xcu_nb_inputs, |
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[450] | 73 | |
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| 74 | const Loader &loader, |
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| 75 | |
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| 76 | uint32_t frozen_cycles, |
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| 77 | uint32_t debug_start_cycle, |
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| 78 | bool memc_debug_ok, |
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| 79 | bool proc_debug_ok, |
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| 80 | bool iob_debug_ok ) |
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| 81 | : soclib::caba::BaseModule(insname), |
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| 82 | p_clk("clk"), |
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| 83 | p_resetn("resetn") |
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| 84 | { |
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| 85 | assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); |
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| 86 | |
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[607] | 87 | size_t cluster_id = (x_id<<4) + y_id; |
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[450] | 88 | |
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[607] | 89 | size_t cluster_iob0 = 0; // South-West cluster |
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| 90 | size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster |
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[550] | 91 | |
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[450] | 92 | // Vectors of DSPIN ports for inter-cluster communications |
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[468] | 93 | p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 94 | p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 95 | p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 96 | p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 97 | |
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| 98 | p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 99 | p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 100 | p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 101 | p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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| 102 | |
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[550] | 103 | // ports in cluster_iob0 and cluster_iob1 only |
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[450] | 104 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 105 | { |
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[550] | 106 | // VCI ports from IOB to IOX network |
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| 107 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 108 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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| 109 | |
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| 110 | // DSPIN ports from IOB to RAM network |
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| 111 | p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; |
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| 112 | p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; |
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[450] | 113 | } |
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| 114 | |
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| 115 | ///////////////////////////////////////////////////////////////////////////// |
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| 116 | // Hardware components |
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| 117 | ///////////////////////////////////////////////////////////////////////////// |
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| 118 | |
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| 119 | //////////// PROCS |
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| 120 | for (size_t p = 0; p < nb_procs; p++) |
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| 121 | { |
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| 122 | std::ostringstream s_proc; |
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| 123 | s_proc << "proc_" << x_id << "_" << y_id << "_" << p; |
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| 124 | proc[p] = new VciCcVCacheWrapper<vci_param_int, |
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| 125 | dspin_int_cmd_width, |
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| 126 | dspin_int_rsp_width, |
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| 127 | GdbServer<Mips32ElIss> >( |
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| 128 | s_proc.str().c_str(), |
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| 129 | cluster_id*nb_procs + p, // GLOBAL PROC_ID |
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| 130 | mt_int, // Mapping Table INT network |
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| 131 | IntTab(cluster_id,p), // SRCID |
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| 132 | (cluster_id << l_width) + p, // CC_GLOBAL_ID |
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| 133 | 8, // ITLB ways |
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| 134 | 8, // ITLB sets |
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| 135 | 8, // DTLB ways |
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| 136 | 8, // DTLB sets |
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| 137 | l1_i_ways,l1_i_sets,16, // ICACHE size |
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| 138 | l1_d_ways,l1_d_sets,16, // DCACHE size |
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| 139 | 4, // WBUF nlines |
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| 140 | 4, // WBUF nwords |
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| 141 | x_width, |
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| 142 | y_width, |
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| 143 | frozen_cycles, // max frozen cycles |
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| 144 | debug_start_cycle, |
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| 145 | proc_debug_ok); |
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| 146 | } |
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| 147 | |
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| 148 | /////////// MEMC |
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| 149 | std::ostringstream s_memc; |
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| 150 | s_memc << "memc_" << x_id << "_" << y_id; |
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| 151 | memc = new VciMemCache<vci_param_int, |
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| 152 | vci_param_ext, |
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| 153 | dspin_int_rsp_width, |
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| 154 | dspin_int_cmd_width>( |
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| 155 | s_memc.str().c_str(), |
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| 156 | mt_int, // Mapping Table INT network |
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| 157 | mt_ram, // Mapping Table RAM network |
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| 158 | IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network |
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| 159 | IntTab(cluster_id, memc_int_tgtid), // TGTID INT network |
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[550] | 160 | x_width, // number of bits for x coordinate |
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| 161 | y_width, // number of bits for y coordinate |
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[450] | 162 | memc_ways, memc_sets, 16, // CACHE SIZE |
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| 163 | 3, // MAX NUMBER OF COPIES |
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| 164 | 4096, // HEAP SIZE |
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| 165 | 8, // TRANSACTION TABLE DEPTH |
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| 166 | 8, // UPDATE TABLE DEPTH |
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[468] | 167 | 8, // INVALIDATE TABLE DEPTH |
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[450] | 168 | debug_start_cycle, |
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| 169 | memc_debug_ok ); |
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| 170 | |
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| 171 | std::ostringstream s_wi_memc; |
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| 172 | s_wi_memc << "memc_wi_" << x_id << "_" << y_id; |
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| 173 | memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 174 | dspin_ram_cmd_width, |
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| 175 | dspin_ram_rsp_width>( |
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| 176 | s_wi_memc.str().c_str(), |
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| 177 | x_width + y_width + l_width); |
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| 178 | |
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| 179 | /////////// XICU |
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| 180 | std::ostringstream s_xicu; |
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| 181 | s_xicu << "xicu_" << x_id << "_" << y_id; |
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| 182 | xicu = new VciXicu<vci_param_int>( |
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| 183 | s_xicu.str().c_str(), |
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| 184 | mt_int, // mapping table INT network |
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| 185 | IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space |
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[714] | 186 | xcu_nb_inputs, // number of timer IRQs |
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| 187 | xcu_nb_inputs, // number of hard IRQs |
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| 188 | xcu_nb_inputs, // number of soft IRQs |
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| 189 | 16); // number of output IRQs |
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[450] | 190 | |
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| 191 | //////////// MDMA |
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| 192 | std::ostringstream s_mdma; |
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| 193 | s_mdma << "mdma_" << x_id << "_" << y_id; |
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| 194 | mdma = new VciMultiDma<vci_param_int>( |
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| 195 | s_mdma.str().c_str(), |
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| 196 | mt_int, |
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| 197 | IntTab(cluster_id, nb_procs), // SRCID |
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| 198 | IntTab(cluster_id, mdma_int_tgtid), // TGTID |
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| 199 | 64, // burst size |
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| 200 | nb_dmas); // number of IRQs |
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| 201 | |
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| 202 | /////////// Direct LOCAL_XBAR(S) |
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| 203 | size_t nb_direct_initiators = nb_procs + 1; |
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| 204 | size_t nb_direct_targets = 3; |
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| 205 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 206 | { |
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| 207 | nb_direct_initiators = nb_procs + 2; |
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| 208 | nb_direct_targets = 4; |
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| 209 | } |
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| 210 | |
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[693] | 211 | std::ostringstream s_int_xbar_d; |
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| 212 | s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; |
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| 213 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 214 | s_int_xbar_d.str().c_str(), |
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[450] | 215 | mt_int, // mapping table |
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[693] | 216 | cluster_id, // cluster id |
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| 217 | nb_direct_initiators, // number of local initiators |
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| 218 | nb_direct_targets, // number of local targets |
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| 219 | 0 ); // default target |
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[450] | 220 | |
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[693] | 221 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 222 | s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" |
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| 223 | << x_id << "_" << y_id; |
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| 224 | int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int, |
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| 225 | dspin_int_cmd_width, |
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| 226 | dspin_int_rsp_width>( |
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| 227 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 228 | x_width + y_width + l_width); |
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[450] | 229 | |
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[693] | 230 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 231 | s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" |
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| 232 | << x_id << "_" << y_id; |
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| 233 | int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int, |
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| 234 | dspin_int_cmd_width, |
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| 235 | dspin_int_rsp_width>( |
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| 236 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 237 | x_width + y_width + l_width); |
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| 238 | |
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[450] | 239 | //////////// Coherence LOCAL_XBAR(S) |
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| 240 | std::ostringstream s_int_xbar_m2p_c; |
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| 241 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; |
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| 242 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 243 | s_int_xbar_m2p_c.str().c_str(), |
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| 244 | mt_int, // mapping table |
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| 245 | x_id, y_id, // cluster coordinates |
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| 246 | x_width, y_width, l_width, // several dests |
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| 247 | 1, // number of local sources |
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| 248 | nb_procs, // number of local dests |
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| 249 | 2, 2, // fifo depths |
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| 250 | true, // pseudo CMD |
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| 251 | false, // no routing table |
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| 252 | true ); // broacast |
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| 253 | |
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| 254 | std::ostringstream s_int_xbar_p2m_c; |
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| 255 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; |
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| 256 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 257 | s_int_xbar_p2m_c.str().c_str(), |
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| 258 | mt_int, // mapping table |
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| 259 | x_id, y_id, // cluster coordinates |
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| 260 | x_width, y_width, 0, // only one dest |
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| 261 | nb_procs, // number of local sources |
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| 262 | 1, // number of local dests |
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| 263 | 2, 2, // fifo depths |
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| 264 | false, // pseudo RSP |
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| 265 | false, // no routing table |
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| 266 | false ); // no broacast |
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| 267 | |
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[468] | 268 | std::ostringstream s_int_xbar_clack_c; |
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| 269 | s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; |
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| 270 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 271 | s_int_xbar_clack_c.str().c_str(), |
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| 272 | mt_int, // mapping table |
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| 273 | x_id, y_id, // cluster coordinates |
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| 274 | x_width, y_width, l_width, |
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| 275 | 1, // number of local sources |
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| 276 | nb_procs, // number of local targets |
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| 277 | 1, 1, // fifo depths |
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| 278 | true, // CMD |
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[707] | 279 | false, // no routing table |
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[468] | 280 | false); // broadcast |
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| 281 | |
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[450] | 282 | ////////////// INT ROUTER(S) |
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| 283 | std::ostringstream s_int_router_cmd; |
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| 284 | s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; |
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| 285 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 286 | s_int_router_cmd.str().c_str(), |
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| 287 | x_id,y_id, // coordinate in the mesh |
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| 288 | x_width, y_width, // x & y fields width |
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[468] | 289 | 3, // nb virtual channels |
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[450] | 290 | 4,4); // input & output fifo depths |
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| 291 | |
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| 292 | std::ostringstream s_int_router_rsp; |
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| 293 | s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; |
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| 294 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 295 | s_int_router_rsp.str().c_str(), |
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[550] | 296 | x_id,y_id, // router coordinates in mesh |
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[450] | 297 | x_width, y_width, // x & y fields width |
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[468] | 298 | 2, // nb virtual channels |
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[450] | 299 | 4,4); // input & output fifo depths |
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| 300 | |
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| 301 | ////////////// XRAM |
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| 302 | std::ostringstream s_xram; |
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| 303 | s_xram << "xram_" << x_id << "_" << y_id; |
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| 304 | xram = new VciSimpleRam<vci_param_ext>( |
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| 305 | s_xram.str().c_str(), |
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| 306 | IntTab(cluster_id, xram_ram_tgtid ), |
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| 307 | mt_ram, |
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| 308 | loader, |
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| 309 | xram_latency); |
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| 310 | |
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| 311 | std::ostringstream s_wt_xram; |
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| 312 | s_wt_xram << "xram_wt_" << x_id << "_" << y_id; |
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| 313 | xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext, |
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| 314 | dspin_ram_cmd_width, |
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| 315 | dspin_ram_rsp_width>( |
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| 316 | s_wt_xram.str().c_str(), |
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| 317 | x_width + y_width + l_width); |
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| 318 | |
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| 319 | ///////////// RAM ROUTER(S) |
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| 320 | std::ostringstream s_ram_router_cmd; |
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| 321 | s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; |
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[584] | 322 | size_t is_iob0 = (x_id == 0) and (y_id == 0); |
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| 323 | size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1)); |
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[550] | 324 | ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( |
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[450] | 325 | s_ram_router_cmd.str().c_str(), |
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[584] | 326 | x_id, y_id, // router coordinates in mesh |
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| 327 | x_width, // x field width in first flit |
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| 328 | y_width, // y field width in first flit |
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| 329 | 4, 4, // input & output fifo depths |
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| 330 | is_iob0, // cluster contains IOB0 |
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| 331 | is_iob1, // cluster contains IOB1 |
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| 332 | false, // not a response router |
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| 333 | l_width); // local field width in first flit |
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[450] | 334 | |
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| 335 | std::ostringstream s_ram_router_rsp; |
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| 336 | s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; |
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[550] | 337 | ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( |
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[450] | 338 | s_ram_router_rsp.str().c_str(), |
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[584] | 339 | x_id, y_id, // coordinates in mesh |
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| 340 | x_width, // x field width in first flit |
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| 341 | y_width, // y field width in first flit |
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| 342 | 4, 4, // input & output fifo depths |
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| 343 | is_iob0, // cluster contains IOB0 |
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| 344 | is_iob1, // cluster contains IOB1 |
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| 345 | true, // response router |
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| 346 | l_width); // local field width in first flit |
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[450] | 347 | |
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[550] | 348 | |
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[450] | 349 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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| 350 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 351 | { |
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| 352 | /////////// IO_BRIDGE |
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| 353 | size_t iox_local_id; |
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| 354 | size_t global_id; |
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| 355 | if ( cluster_id == cluster_iob0 ) |
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| 356 | { |
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| 357 | iox_local_id = 0; |
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| 358 | global_id = cluster_iob0; |
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| 359 | } |
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| 360 | else |
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| 361 | { |
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| 362 | iox_local_id = 1; |
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| 363 | global_id = cluster_iob1; |
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| 364 | } |
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| 365 | |
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| 366 | std::ostringstream s_iob; |
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| 367 | s_iob << "iob_" << x_id << "_" << y_id; |
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| 368 | iob = new VciIoBridge<vci_param_int, |
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| 369 | vci_param_ext>( |
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| 370 | s_iob.str().c_str(), |
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| 371 | mt_ram, // EXT network maptab |
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| 372 | mt_int, // INT network maptab |
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| 373 | mt_iox, // IOX network maptab |
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| 374 | IntTab( global_id, iobx_int_tgtid ), // INT TGTID |
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| 375 | IntTab( global_id, iobx_int_srcid ), // INT SRCID |
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| 376 | IntTab( global_id, iox_local_id ), // IOX TGTID |
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| 377 | 16, // cache line words |
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| 378 | 8, // IOTLB ways |
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| 379 | 8, // IOTLB sets |
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| 380 | debug_start_cycle, |
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| 381 | iob_debug_ok ); |
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| 382 | |
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| 383 | std::ostringstream s_iob_ram_wi; |
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| 384 | s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; |
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| 385 | iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, |
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| 386 | dspin_ram_cmd_width, |
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| 387 | dspin_ram_rsp_width>( |
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| 388 | s_iob_ram_wi.str().c_str(), |
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| 389 | x_width + y_width + l_width); |
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[550] | 390 | } // end if IO |
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[450] | 391 | |
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| 392 | //////////////////////////////////// |
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| 393 | // Connections are defined here |
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| 394 | //////////////////////////////////// |
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| 395 | |
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| 396 | // on coherence network : local srcid[proc] in [0...nb_procs-1] |
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| 397 | // : local srcid[memc] = nb_procs |
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[584] | 398 | // In cluster_iob0, 32 HWI interrupts from external peripherals |
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| 399 | // are connected to the XICU ports p_hwi[0:31] |
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| 400 | // In other clusters, no HWI interrupts are connected to XICU |
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| 401 | |
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[450] | 402 | //////////////////////// internal CMD & RSP routers |
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| 403 | int_router_cmd->p_clk (this->p_clk); |
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| 404 | int_router_cmd->p_resetn (this->p_resetn); |
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| 405 | int_router_rsp->p_clk (this->p_clk); |
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| 406 | int_router_rsp->p_resetn (this->p_resetn); |
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[468] | 407 | |
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| 408 | for (int i = 0; i < 4; i++) |
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[450] | 409 | { |
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[468] | 410 | for(int k = 0; k < 3; k++) |
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[450] | 411 | { |
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[468] | 412 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
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| 413 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
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[450] | 414 | } |
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[468] | 415 | |
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| 416 | for(int k = 0; k < 2; k++) |
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| 417 | { |
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| 418 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
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| 419 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
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| 420 | } |
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[450] | 421 | } |
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| 422 | |
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| 423 | // local ports |
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[468] | 424 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
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| 425 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
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| 426 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
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| 427 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
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| 428 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
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| 429 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
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[450] | 430 | |
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[468] | 431 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
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| 432 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
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| 433 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
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| 434 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
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[450] | 435 | |
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| 436 | ///////////////////// CMD DSPIN local crossbar direct |
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[693] | 437 | int_xbar_d->p_clk (this->p_clk); |
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| 438 | int_xbar_d->p_resetn (this->p_resetn); |
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| 439 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
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| 440 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
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[450] | 441 | |
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[693] | 442 | int_xbar_d->p_to_target[memc_int_tgtid] (signal_int_vci_tgt_memc); |
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| 443 | int_xbar_d->p_to_target[xicu_int_tgtid] (signal_int_vci_tgt_xicu); |
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| 444 | int_xbar_d->p_to_target[mdma_int_tgtid] (signal_int_vci_tgt_mdma); |
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| 445 | int_xbar_d->p_to_initiator[mdma_int_srcid] (signal_int_vci_ini_mdma); |
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[450] | 446 | for (size_t p = 0; p < nb_procs; p++) |
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[693] | 447 | int_xbar_d->p_to_initiator[proc_int_srcid + p] (signal_int_vci_ini_proc[p]); |
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[450] | 448 | |
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| 449 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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| 450 | { |
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[693] | 451 | int_xbar_d->p_to_target[iobx_int_tgtid] (signal_int_vci_tgt_iobx); |
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| 452 | int_xbar_d->p_to_initiator[iobx_int_srcid] (signal_int_vci_ini_iobx); |
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[450] | 453 | } |
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| 454 | |
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[714] | 455 | int_wi_gate_d->p_clk (this->p_clk); |
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| 456 | int_wi_gate_d->p_resetn (this->p_resetn); |
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| 457 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
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| 458 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
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| 459 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
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[450] | 460 | |
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[714] | 461 | int_wt_gate_d->p_clk (this->p_clk); |
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| 462 | int_wt_gate_d->p_resetn (this->p_resetn); |
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| 463 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
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| 464 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
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| 465 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
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[693] | 466 | |
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[450] | 467 | ////////////////////// M2P DSPIN local crossbar coherence |
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| 468 | int_xbar_m2p_c->p_clk (this->p_clk); |
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| 469 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
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| 470 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
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| 471 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
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| 472 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
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| 473 | for (size_t p = 0; p < nb_procs; p++) |
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| 474 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
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| 475 | |
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| 476 | ////////////////////////// P2M DSPIN local crossbar coherence |
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| 477 | int_xbar_p2m_c->p_clk (this->p_clk); |
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| 478 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
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| 479 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
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| 480 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
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| 481 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
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| 482 | for (size_t p = 0; p < nb_procs; p++) |
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| 483 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
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| 484 | |
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[468] | 485 | ////////////////////// CLACK DSPIN local crossbar coherence |
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| 486 | int_xbar_clack_c->p_clk (this->p_clk); |
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| 487 | int_xbar_clack_c->p_resetn (this->p_resetn); |
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| 488 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
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| 489 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
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| 490 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
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| 491 | for (size_t p = 0; p < nb_procs; p++) |
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| 492 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
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| 493 | |
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[450] | 494 | //////////////////////////////////// Processors |
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| 495 | for (size_t p = 0; p < nb_procs; p++) |
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| 496 | { |
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| 497 | proc[p]->p_clk (this->p_clk); |
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| 498 | proc[p]->p_resetn (this->p_resetn); |
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| 499 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
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[468] | 500 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
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| 501 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
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| 502 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
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[707] | 503 | |
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| 504 | for ( size_t j = 0 ; j < 6 ; j++) |
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[450] | 505 | { |
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[707] | 506 | if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); |
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| 507 | else proc[p]->p_irq[j] (signal_false); |
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[450] | 508 | } |
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| 509 | } |
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| 510 | |
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| 511 | ///////////////////////////////////// XICU |
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[468] | 512 | xicu->p_clk (this->p_clk); |
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| 513 | xicu->p_resetn (this->p_resetn); |
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| 514 | xicu->p_vci (signal_int_vci_tgt_xicu); |
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[714] | 515 | for ( size_t i=0 ; i < 16 ; i++) |
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[450] | 516 | { |
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[714] | 517 | xicu->p_irq[i] (signal_proc_it[i]); |
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[450] | 518 | } |
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[714] | 519 | for ( size_t i=0 ; i < xcu_nb_inputs ; i++) |
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[450] | 520 | { |
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[707] | 521 | if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); |
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| 522 | else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); |
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| 523 | else xicu->p_hwi[i] (signal_false); |
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[450] | 524 | } |
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| 525 | |
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| 526 | ///////////////////////////////////// MEMC |
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[468] | 527 | memc->p_clk (this->p_clk); |
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| 528 | memc->p_resetn (this->p_resetn); |
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| 529 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
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| 530 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
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| 531 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
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| 532 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
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| 533 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
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[607] | 534 | memc->p_irq (signal_irq_memc); |
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[450] | 535 | |
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| 536 | // wrapper to RAM network |
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| 537 | memc_ram_wi->p_clk (this->p_clk); |
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| 538 | memc_ram_wi->p_resetn (this->p_resetn); |
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| 539 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
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| 540 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
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| 541 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
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| 542 | |
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| 543 | //////////////////////////////////// XRAM |
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[468] | 544 | xram->p_clk (this->p_clk); |
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| 545 | xram->p_resetn (this->p_resetn); |
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| 546 | xram->p_vci (signal_ram_vci_tgt_xram); |
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[450] | 547 | |
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| 548 | // wrapper to RAM network |
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| 549 | xram_ram_wt->p_clk (this->p_clk); |
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| 550 | xram_ram_wt->p_resetn (this->p_resetn); |
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| 551 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
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| 552 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
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| 553 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
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| 554 | |
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| 555 | /////////////////////////////////// MDMA |
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[468] | 556 | mdma->p_clk (this->p_clk); |
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[450] | 557 | mdma->p_resetn (this->p_resetn); |
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[468] | 558 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
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| 559 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
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[450] | 560 | for (size_t i=0 ; i<nb_dmas ; i++) |
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| 561 | mdma->p_irq[i] (signal_irq_mdma[i]); |
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| 562 | |
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[550] | 563 | //////////////////////////// RAM network CMD & RSP routers |
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[707] | 564 | ram_router_cmd->p_clk (this->p_clk); |
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| 565 | ram_router_cmd->p_resetn (this->p_resetn); |
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| 566 | ram_router_rsp->p_clk (this->p_clk); |
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| 567 | ram_router_rsp->p_resetn (this->p_resetn); |
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[550] | 568 | for( size_t n=0 ; n<4 ; n++) |
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[450] | 569 | { |
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[707] | 570 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
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| 571 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
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| 572 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
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| 573 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
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[450] | 574 | } |
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[707] | 575 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
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| 576 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
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| 577 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
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| 578 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
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[550] | 579 | |
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| 580 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
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| 581 | if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) |
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[450] | 582 | { |
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| 583 | // IO bridge |
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| 584 | iob->p_clk (this->p_clk); |
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| 585 | iob->p_resetn (this->p_resetn); |
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[550] | 586 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
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| 587 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
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[450] | 588 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
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| 589 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
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| 590 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
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[550] | 591 | |
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[450] | 592 | // initiator wrapper to RAM network |
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| 593 | iob_ram_wi->p_clk (this->p_clk); |
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| 594 | iob_ram_wi->p_resetn (this->p_resetn); |
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[550] | 595 | iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); |
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| 596 | iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); |
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[450] | 597 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
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[550] | 598 | } |
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[450] | 599 | |
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| 600 | } // end constructor |
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| 601 | |
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| 602 | }} |
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| 603 | |
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| 604 | |
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| 605 | // Local Variables: |
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| 606 | // tab-width: 3 |
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| 607 | // c-basic-offset: 3 |
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| 608 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 609 | // indent-tabs-mode: nil |
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| 610 | // End: |
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| 611 | |
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| 612 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 613 | |
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| 614 | |
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| 615 | |
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