source: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h

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Diff Rev Age Author Log Message
(edit) @79   14 years gao Correction of dirty bit and access bit in data cache
(edit) @68   14 years bouyer A SC cause the dcache entry to be updated by the memcache, and the tlb …
(edit) @50   14 years gao Activity counter update
(edit) @48   14 years gao Activity counter update
(edit) @37   14 years gao Bug correction
(add) @2   14 years nipo Import TSAR modules in TSAR's own svn
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