[450] | 1 | ////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: tsar_iob_cluster.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : april 2013 |
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| 6 | // This program is released under the GNU public license |
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[648] | 7 | // |
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| 8 | // Modified by: Cesar Fuguet |
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| 9 | // Modified on: mars 2014 |
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[450] | 10 | ////////////////////////////////////////////////////////////////////////////// |
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| 11 | // Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. |
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| 12 | // These two clusters contain 6 extra components: |
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| 13 | // - 1 vci_io_bridge (connected to the 3 networks. |
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| 14 | // - 3 vci_dspin_wrapper for the IOB. |
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| 15 | // - 2 dspin_local_crossbar for commands and responses. |
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| 16 | ////////////////////////////////////////////////////////////////////////////// |
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| 17 | |
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| 18 | #include "../include/tsar_iob_cluster.h" |
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| 19 | |
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[648] | 20 | #define tmpl(x) \ |
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| 21 | template<typename vci_param_int , typename vci_param_ext,\ |
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| 22 | size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ |
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| 23 | size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ |
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| 24 | x TsarIobCluster<\ |
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| 25 | vci_param_int , vci_param_ext,\ |
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| 26 | dspin_int_cmd_width, dspin_int_rsp_width,\ |
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| 27 | dspin_ram_cmd_width, dspin_ram_rsp_width> |
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| 28 | |
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[450] | 29 | namespace soclib { namespace caba { |
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| 30 | |
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| 31 | ////////////////////////////////////////////////////////////////////////// |
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| 32 | // Constructor |
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| 33 | ////////////////////////////////////////////////////////////////////////// |
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[648] | 34 | tmpl(/**/)::TsarIobCluster(struct ClusterParams& params) : |
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[695] | 35 | soclib::caba::BaseModule(params.insname), |
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| 36 | p_clk("clk"), |
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| 37 | p_resetn("resetn") { |
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[450] | 38 | |
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[695] | 39 | assert((params.x_id < X_MAX) && (params.y_id < Y_MAX)); |
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[450] | 40 | |
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[695] | 41 | size_t cid = this->clusterId(params.x_id, params.y_id); |
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| 42 | size_t cluster_iob0 = this->clusterId(0, 0); |
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| 43 | size_t cluster_iob1 = this->clusterId(X_SIZE - 1, Y_SIZE - 1); |
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| 44 | size_t is_iob0 = (cid == cluster_iob0); |
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| 45 | size_t is_iob1 = (cid == cluster_iob1); |
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| 46 | bool is_io_cluster = is_iob0 || is_iob1; |
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[450] | 47 | |
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[695] | 48 | size_t l_width = vci_param_int::S - X_WIDTH - Y_WIDTH; |
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| 49 | |
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[648] | 50 | // Vectors of DSPIN ports for inter-cluster communications |
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| 51 | p_dspin_int_cmd_in = |
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| 52 | alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); |
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| 53 | p_dspin_int_cmd_out = |
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| 54 | alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3); |
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| 55 | p_dspin_int_rsp_in = |
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| 56 | alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2); |
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| 57 | p_dspin_int_rsp_out = |
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| 58 | alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2); |
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[450] | 59 | |
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[648] | 60 | p_dspin_ram_cmd_in = |
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| 61 | alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4); |
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| 62 | p_dspin_ram_cmd_out = |
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| 63 | alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4); |
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| 64 | p_dspin_ram_rsp_in = |
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| 65 | alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4); |
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| 66 | p_dspin_ram_rsp_out = |
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| 67 | alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); |
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[450] | 68 | |
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[648] | 69 | // ports in cluster_iob0 and cluster_iob1 only |
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[695] | 70 | p_vci_iob_iox_ini = NULL; |
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| 71 | p_vci_iob_iox_tgt = NULL; |
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| 72 | p_dspin_iob_cmd_out = NULL; |
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| 73 | p_dspin_iob_rsp_in = NULL; |
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| 74 | if ( is_io_cluster ) { |
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[648] | 75 | // VCI ports from IOB to IOX network |
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| 76 | p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; |
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| 77 | p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; |
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[450] | 78 | |
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[648] | 79 | // DSPIN ports from IOB to RAM network |
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[695] | 80 | p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; |
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| 81 | p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; |
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[648] | 82 | } |
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[450] | 83 | |
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[648] | 84 | // IRQ ports in cluster_iob0 only |
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[695] | 85 | for ( size_t n = 0 ; n < 32 ; n++ ) { |
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| 86 | p_irq[n] = ( is_iob0 ) ? new sc_in<bool> : NULL; |
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[648] | 87 | } |
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[450] | 88 | |
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[648] | 89 | /////////////////////////////////////////////////////////////////////////// |
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| 90 | // Hardware components |
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| 91 | /////////////////////////////////////////////////////////////////////////// |
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[450] | 92 | |
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[648] | 93 | //////////// PROCS |
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[695] | 94 | for (size_t p = 0; p < NB_PROCS; p++) { |
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[648] | 95 | std::ostringstream s_proc; |
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| 96 | s_proc << "proc_" << params.x_id << "_" << params.y_id << "_" << p; |
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| 97 | proc[p] = new VciCcVCacheWrapperType ( |
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| 98 | s_proc.str().c_str(), |
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[695] | 99 | cid * NB_PROCS + p, |
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[648] | 100 | params.mt_int, |
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[695] | 101 | IntTab(cid,p), |
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| 102 | (cid << l_width) + p, |
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[648] | 103 | 8, 8, |
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| 104 | 8, 8, |
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| 105 | params.l1_i_ways, params.l1_i_sets, 16, |
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| 106 | params.l1_d_ways, params.l1_d_sets, 16, |
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| 107 | 4, 4, |
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[695] | 108 | X_WIDTH, Y_WIDTH, |
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[648] | 109 | params.frozen_cycles, |
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| 110 | params.debug_start_cycle, params.proc_debug_ok); |
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[450] | 111 | |
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[695] | 112 | proc[p]->set_dcache_paddr_ext_reset(cid); |
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| 113 | proc[p]->set_icache_paddr_ext_reset(cid); |
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[648] | 114 | } |
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[450] | 115 | |
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[648] | 116 | /////////// MEMC |
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| 117 | std::ostringstream s_memc; |
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| 118 | s_memc << "memc_" << params.x_id << "_" << params.y_id; |
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| 119 | memc = new VciMemCacheType ( |
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| 120 | s_memc.str().c_str(), |
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| 121 | params.mt_int, |
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| 122 | params.mt_ext, |
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[695] | 123 | IntTab(cid, RAM_MEMC_INI_ID), |
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| 124 | IntTab(cid, INT_MEMC_TGT_ID), |
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| 125 | X_WIDTH, |
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| 126 | Y_WIDTH, |
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[648] | 127 | params.memc_ways, params.memc_sets, 16, |
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| 128 | 3, |
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| 129 | 4096, |
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[695] | 130 | 8, 8, 8, |
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[648] | 131 | params.debug_start_cycle, |
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| 132 | params.memc_debug_ok); |
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[550] | 133 | |
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[648] | 134 | std::ostringstream s_wi_memc; |
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| 135 | s_wi_memc << "memc_wi_" << params.x_id << "_" << params.y_id; |
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| 136 | memc_ram_wi = new VciExtDspinInitiatorWrapperType ( |
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| 137 | s_wi_memc.str().c_str(), |
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[695] | 138 | vci_param_int::S); |
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[450] | 139 | |
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[658] | 140 | /////////// LOCAL ROM |
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[695] | 141 | std::ostringstream s_brom; |
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| 142 | s_brom << "brom_" << params.x_id << "_" << params.y_id; |
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[658] | 143 | brom = new VciSimpleRom<vci_param_int>( |
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[695] | 144 | s_brom.str().c_str(), |
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| 145 | IntTab(cid, INT_BROM_TGT_ID), |
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[658] | 146 | params.mt_int, |
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| 147 | params.loader, |
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[695] | 148 | X_WIDTH + Y_WIDTH); |
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[658] | 149 | |
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[695] | 150 | // Multi-TTY controller |
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| 151 | mtty = NULL; |
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| 152 | if (NB_DEBUG_TTY_CHANNELS) { |
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| 153 | assert(NB_DEBUG_TTY_CHANNELS < 8); |
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| 154 | |
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| 155 | std::ostringstream s_mtty; |
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| 156 | s_mtty << "mtty_" << params.x_id << "_" << params.y_id; |
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| 157 | std::vector<std::string> vect_names; |
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| 158 | for( size_t tid = 0 ; tid < NB_DEBUG_TTY_CHANNELS ; tid++ ) { |
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| 159 | std::ostringstream term_name; |
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| 160 | term_name << s_mtty.str() << "_" << tid; |
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| 161 | vect_names.push_back(term_name.str().c_str()); |
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| 162 | } |
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| 163 | mtty = new VciMultiTty<vci_param_int>( |
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| 164 | s_mtty.str().c_str(), |
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| 165 | IntTab(cid, INT_MTTY_TGT_ID), |
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| 166 | params.mt_int, |
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| 167 | vect_names); |
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| 168 | } |
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| 169 | |
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[648] | 170 | /////////// XICU |
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| 171 | std::ostringstream s_xicu; |
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| 172 | s_xicu << "xicu_" << params.x_id << "_" << params.y_id; |
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| 173 | xicu = new VciXicu<vci_param_int>( |
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| 174 | s_xicu.str().c_str(), |
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| 175 | params.mt_int, |
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[695] | 176 | IntTab(cid, INT_XICU_TGT_ID), |
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[648] | 177 | 32, 32, 32, |
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[695] | 178 | NB_PROCS); |
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[550] | 179 | |
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[648] | 180 | //////////// MDMA |
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| 181 | std::ostringstream s_mdma; |
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| 182 | s_mdma << "mdma_" << params.x_id << "_" << params.y_id; |
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| 183 | mdma = new VciMultiDma<vci_param_int>( |
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| 184 | s_mdma.str().c_str(), |
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| 185 | params.mt_int, |
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[695] | 186 | IntTab(cid, NB_PROCS), |
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| 187 | IntTab(cid, INT_MDMA_TGT_ID), |
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[648] | 188 | 64, |
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[695] | 189 | NB_DMA_CHANNELS); |
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[450] | 190 | |
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[648] | 191 | /////////// Direct LOCAL_XBAR(S) |
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[695] | 192 | size_t nb_direct_initiators = NB_PROCS + 1; |
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[658] | 193 | size_t nb_direct_targets = 4; |
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[695] | 194 | if (NB_DEBUG_TTY_CHANNELS) { |
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| 195 | nb_direct_targets++; |
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[648] | 196 | } |
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[695] | 197 | if ( is_io_cluster ) { |
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| 198 | nb_direct_initiators++; |
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| 199 | nb_direct_targets++; |
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| 200 | } |
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[450] | 201 | |
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[696] | 202 | std::ostringstream s_int_xbar_d; |
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| 203 | s_int_xbar_d << "int_xbar_cmd_d_" << params.x_id << "_" << params.y_id; |
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| 204 | int_xbar_d = new VciLocalCrossbar<vci_param_int>( |
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| 205 | s_int_xbar_d.str().c_str(), |
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[648] | 206 | params.mt_int, |
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[696] | 207 | cid, |
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[648] | 208 | nb_direct_initiators, |
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| 209 | nb_direct_targets, |
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[696] | 210 | 0 ); |
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[450] | 211 | |
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[696] | 212 | std::ostringstream s_int_dspin_ini_wrapper_gate_d; |
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| 213 | s_int_dspin_ini_wrapper_gate_d |
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| 214 | << "int_dspin_ini_wrapper_gate_d_" << params.x_id << "_" << params.y_id; |
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| 215 | int_wi_gate_d = new VciIntDspinInitiatorWrapperType( |
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| 216 | s_int_dspin_ini_wrapper_gate_d.str().c_str(), |
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| 217 | X_WIDTH + Y_WIDTH + l_width); |
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[450] | 218 | |
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[696] | 219 | std::ostringstream s_int_dspin_tgt_wrapper_gate_d; |
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| 220 | s_int_dspin_tgt_wrapper_gate_d |
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| 221 | << "int_dspin_tgt_wrapper_gate_d_" << params.x_id << "_" << params.y_id; |
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| 222 | int_wt_gate_d = new VciIntDspinTargetWrapperType( |
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| 223 | s_int_dspin_tgt_wrapper_gate_d.str().c_str(), |
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| 224 | X_WIDTH + Y_WIDTH + l_width); |
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| 225 | |
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[648] | 226 | //////////// Coherence LOCAL_XBAR(S) |
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| 227 | std::ostringstream s_int_xbar_m2p_c; |
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| 228 | s_int_xbar_m2p_c << "int_xbar_m2p_c_" << params.x_id << "_" << params.y_id; |
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| 229 | int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 230 | s_int_xbar_m2p_c.str().c_str(), |
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| 231 | params.mt_int, |
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| 232 | params.x_id, params.y_id, |
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[695] | 233 | X_WIDTH, Y_WIDTH, l_width, |
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[648] | 234 | 1, |
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[695] | 235 | NB_PROCS, |
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[648] | 236 | 2, 2, |
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| 237 | true, |
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| 238 | false, |
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| 239 | true); |
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[450] | 240 | |
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[648] | 241 | std::ostringstream s_int_xbar_p2m_c; |
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| 242 | s_int_xbar_p2m_c << "int_xbar_p2m_c_" << params.x_id << "_" << params.y_id; |
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| 243 | int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>( |
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| 244 | s_int_xbar_p2m_c.str().c_str(), |
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| 245 | params.mt_int, |
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| 246 | params.x_id, params.y_id, |
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[695] | 247 | X_WIDTH, Y_WIDTH, 0, |
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| 248 | NB_PROCS, |
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[648] | 249 | 1, |
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| 250 | 2, 2, |
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| 251 | false, |
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| 252 | false, |
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| 253 | false); |
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[450] | 254 | |
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[648] | 255 | std::ostringstream s_int_xbar_clack_c; |
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| 256 | s_int_xbar_clack_c << "int_xbar_clack_c_" << params.x_id << "_" |
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[695] | 257 | << params.y_id; |
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[648] | 258 | int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>( |
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| 259 | s_int_xbar_clack_c.str().c_str(), |
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| 260 | params.mt_int, |
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| 261 | params.x_id, params.y_id, |
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[695] | 262 | X_WIDTH, Y_WIDTH, l_width, |
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[648] | 263 | 1, |
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[695] | 264 | NB_PROCS, |
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[648] | 265 | 1, 1, |
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| 266 | true, |
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| 267 | false, |
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| 268 | false); |
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[450] | 269 | |
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[648] | 270 | ////////////// INT ROUTER(S) |
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| 271 | std::ostringstream s_int_router_cmd; |
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| 272 | s_int_router_cmd << "router_cmd_" << params.x_id << "_" << params.y_id; |
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| 273 | int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>( |
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| 274 | s_int_router_cmd.str().c_str(), |
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[695] | 275 | params.x_id, params.y_id, |
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| 276 | X_WIDTH, Y_WIDTH, |
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[648] | 277 | 3, |
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| 278 | 4,4); |
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[450] | 279 | |
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[648] | 280 | std::ostringstream s_int_router_rsp; |
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| 281 | s_int_router_rsp << "router_rsp_" << params.x_id << "_" << params.y_id; |
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| 282 | int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>( |
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| 283 | s_int_router_rsp.str().c_str(), |
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[695] | 284 | params.x_id, params.y_id, |
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| 285 | X_WIDTH, Y_WIDTH, |
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[648] | 286 | 2, |
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| 287 | 4,4); |
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[450] | 288 | |
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[648] | 289 | ////////////// XRAM |
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| 290 | std::ostringstream s_xram; |
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| 291 | s_xram << "xram_" << params.x_id << "_" << params.y_id; |
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| 292 | xram = new VciSimpleRam<vci_param_ext>( |
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| 293 | s_xram.str().c_str(), |
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[695] | 294 | IntTab(cid, RAM_XRAM_TGT_ID), |
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[648] | 295 | params.mt_ext, |
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| 296 | params.loader, |
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| 297 | params.xram_latency); |
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[450] | 298 | |
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[648] | 299 | std::ostringstream s_wt_xram; |
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| 300 | s_wt_xram << "xram_wt_" << params.x_id << "_" << params.y_id; |
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| 301 | xram_ram_wt = new VciExtDspinTargetWrapperType( |
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| 302 | s_wt_xram.str().c_str(), |
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[695] | 303 | vci_param_int::S); |
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[450] | 304 | |
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[648] | 305 | ///////////// RAM ROUTER(S) |
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| 306 | std::ostringstream s_ram_router_cmd; |
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| 307 | s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id; |
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| 308 | ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( |
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| 309 | s_ram_router_cmd.str().c_str(), |
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| 310 | params.x_id, params.y_id, |
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[695] | 311 | X_WIDTH, Y_WIDTH, |
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[648] | 312 | 4, 4, |
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[695] | 313 | is_iob0, is_iob1, |
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[648] | 314 | false, |
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[695] | 315 | l_width); |
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[450] | 316 | |
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[648] | 317 | std::ostringstream s_ram_router_rsp; |
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| 318 | s_ram_router_rsp << "ram_router_rsp_" << params.x_id << "_" << params.y_id; |
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| 319 | ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>( |
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| 320 | s_ram_router_rsp.str().c_str(), |
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| 321 | params.x_id, params.y_id, |
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[695] | 322 | X_WIDTH, Y_WIDTH, |
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[648] | 323 | 4, 4, |
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[695] | 324 | is_iob0, is_iob1, |
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[648] | 325 | true, |
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[695] | 326 | l_width); |
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[450] | 327 | |
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[648] | 328 | ////////////////////// I/O CLUSTER ONLY /////////////////////// |
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[695] | 329 | iob = NULL; |
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| 330 | iob_ram_wi = NULL; |
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| 331 | if ( is_io_cluster ) { |
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[648] | 332 | /////////// IO_BRIDGE |
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| 333 | size_t iox_local_id; |
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| 334 | bool has_irqs; |
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[695] | 335 | if ( is_iob0 ) { |
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[648] | 336 | iox_local_id = 0; |
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| 337 | has_irqs = true; |
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| 338 | } |
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[695] | 339 | else { |
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[648] | 340 | iox_local_id = 1; |
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| 341 | has_irqs = false; |
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| 342 | } |
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[450] | 343 | |
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[648] | 344 | std::ostringstream s_iob; |
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| 345 | s_iob << "iob_" << params.x_id << "_" << params.y_id; |
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| 346 | iob = new VciIoBridge<vci_param_int, vci_param_ext>( |
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| 347 | s_iob.str().c_str(), |
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| 348 | params.mt_ext, |
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| 349 | params.mt_int, |
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| 350 | params.mt_iox, |
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[695] | 351 | IntTab(cid, INT_IOBX_TGT_ID), |
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| 352 | IntTab(cid, INT_IOBX_INI_ID), |
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| 353 | IntTab(cid, iox_local_id ), |
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[648] | 354 | has_irqs, |
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| 355 | 16, |
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| 356 | 8, |
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| 357 | 8, |
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| 358 | params.debug_start_cycle, |
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| 359 | params.iob_debug_ok ); |
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[450] | 360 | |
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[648] | 361 | std::ostringstream s_iob_ram_wi; |
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| 362 | s_iob_ram_wi << "iob_ram_wi_" << params.x_id << "_" << params.y_id; |
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| 363 | iob_ram_wi = new VciExtDspinInitiatorWrapperType( |
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| 364 | s_iob_ram_wi.str().c_str(), |
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[695] | 365 | vci_param_int::S); |
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[648] | 366 | } |
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[450] | 367 | |
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[648] | 368 | //////////////////////////////////// |
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| 369 | // Connections are defined here |
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| 370 | //////////////////////////////////// |
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[450] | 371 | |
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[695] | 372 | // on coherence network : local srcid[proc] in [0...NB_PROCS-1] |
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| 373 | // : local srcid[memc] = NB_PROCS |
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[648] | 374 | // In cluster_iob0, 32 HWI interrupts from external peripherals |
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| 375 | // are connected to the XICU ports p_hwi[0:31] |
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| 376 | // In other clusters, no HWI interrupts are connected to XICU |
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[450] | 377 | |
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[648] | 378 | //////////////////////// internal CMD & RSP routers |
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| 379 | int_router_cmd->p_clk (this->p_clk); |
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| 380 | int_router_cmd->p_resetn (this->p_resetn); |
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| 381 | int_router_rsp->p_clk (this->p_clk); |
---|
| 382 | int_router_rsp->p_resetn (this->p_resetn); |
---|
[450] | 383 | |
---|
[695] | 384 | for (int i = 0; i < 4; i++) { |
---|
| 385 | for(int k = 0; k < 3; k++) { |
---|
[648] | 386 | int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); |
---|
| 387 | int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); |
---|
| 388 | } |
---|
[695] | 389 | for(int k = 0; k < 2; k++) { |
---|
[648] | 390 | int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); |
---|
| 391 | int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); |
---|
| 392 | } |
---|
| 393 | } |
---|
[550] | 394 | |
---|
[648] | 395 | // local ports |
---|
| 396 | int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); |
---|
| 397 | int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); |
---|
| 398 | int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); |
---|
| 399 | int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); |
---|
| 400 | int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); |
---|
| 401 | int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); |
---|
[450] | 402 | |
---|
[648] | 403 | int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); |
---|
| 404 | int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); |
---|
| 405 | int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); |
---|
| 406 | int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); |
---|
[450] | 407 | |
---|
[696] | 408 | ///////////////////// CMD & RSP VCI local crossbar direct |
---|
| 409 | int_xbar_d->p_clk (this->p_clk); |
---|
| 410 | int_xbar_d->p_resetn (this->p_resetn); |
---|
| 411 | int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); |
---|
| 412 | int_xbar_d->p_target_to_up (signal_int_vci_g2l); |
---|
[450] | 413 | |
---|
[696] | 414 | int_xbar_d->p_to_target[INT_MEMC_TGT_ID] (signal_int_vci_tgt_memc); |
---|
| 415 | int_xbar_d->p_to_target[INT_XICU_TGT_ID] (signal_int_vci_tgt_xicu); |
---|
| 416 | int_xbar_d->p_to_target[INT_BROM_TGT_ID] (signal_int_vci_tgt_brom); |
---|
| 417 | int_xbar_d->p_to_target[INT_MDMA_TGT_ID] (signal_int_vci_tgt_mdma); |
---|
[695] | 418 | if (NB_DEBUG_TTY_CHANNELS) { |
---|
[696] | 419 | int_xbar_d->p_to_target[INT_MTTY_TGT_ID] (signal_int_vci_tgt_mtty); |
---|
[695] | 420 | } |
---|
[696] | 421 | int_xbar_d->p_to_initiator[INT_MDMA_INI_ID] (signal_int_vci_ini_mdma); |
---|
[695] | 422 | for (size_t p = 0; p < NB_PROCS; p++) { |
---|
[696] | 423 | int_xbar_d->p_to_initiator[INT_PROC_INI_ID + p]( |
---|
| 424 | signal_int_vci_ini_proc[p]); |
---|
[648] | 425 | } |
---|
[450] | 426 | |
---|
[695] | 427 | if ( is_io_cluster ) { |
---|
[696] | 428 | int_xbar_d->p_to_target[INT_IOBX_TGT_ID] (signal_int_vci_tgt_iobx); |
---|
| 429 | int_xbar_d->p_to_initiator[INT_IOBX_INI_ID] (signal_int_vci_ini_iobx); |
---|
[648] | 430 | } |
---|
[468] | 431 | |
---|
[696] | 432 | int_wi_gate_d->p_clk (this->p_clk); |
---|
| 433 | int_wi_gate_d->p_resetn (this->p_resetn); |
---|
| 434 | int_wi_gate_d->p_vci (signal_int_vci_l2g); |
---|
| 435 | int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); |
---|
| 436 | int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); |
---|
[468] | 437 | |
---|
[696] | 438 | int_wt_gate_d->p_clk (this->p_clk); |
---|
| 439 | int_wt_gate_d->p_resetn (this->p_resetn); |
---|
| 440 | int_wt_gate_d->p_vci (signal_int_vci_g2l); |
---|
| 441 | int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); |
---|
| 442 | int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); |
---|
| 443 | |
---|
[648] | 444 | ////////////////////// M2P DSPIN local crossbar coherence |
---|
| 445 | int_xbar_m2p_c->p_clk (this->p_clk); |
---|
| 446 | int_xbar_m2p_c->p_resetn (this->p_resetn); |
---|
| 447 | int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); |
---|
| 448 | int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); |
---|
| 449 | int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); |
---|
[695] | 450 | for (size_t p = 0; p < NB_PROCS; p++) { |
---|
[648] | 451 | int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); |
---|
| 452 | } |
---|
[450] | 453 | |
---|
[648] | 454 | ////////////////////////// P2M DSPIN local crossbar coherence |
---|
| 455 | int_xbar_p2m_c->p_clk (this->p_clk); |
---|
| 456 | int_xbar_p2m_c->p_resetn (this->p_resetn); |
---|
| 457 | int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); |
---|
| 458 | int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); |
---|
| 459 | int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); |
---|
[695] | 460 | for (size_t p = 0; p < NB_PROCS; p++) { |
---|
[648] | 461 | int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); |
---|
| 462 | } |
---|
| 463 | |
---|
| 464 | ////////////////////// CLACK DSPIN local crossbar coherence |
---|
| 465 | int_xbar_clack_c->p_clk (this->p_clk); |
---|
| 466 | int_xbar_clack_c->p_resetn (this->p_resetn); |
---|
| 467 | int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); |
---|
| 468 | int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); |
---|
| 469 | int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); |
---|
[695] | 470 | for (size_t p = 0; p < NB_PROCS; p++) { |
---|
[648] | 471 | int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); |
---|
| 472 | } |
---|
[450] | 473 | |
---|
[648] | 474 | //////////////////////////////////// Processors |
---|
[695] | 475 | for (size_t p = 0; p < NB_PROCS; p++) { |
---|
[648] | 476 | proc[p]->p_clk (this->p_clk); |
---|
| 477 | proc[p]->p_resetn (this->p_resetn); |
---|
| 478 | proc[p]->p_vci (signal_int_vci_ini_proc[p]); |
---|
| 479 | proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); |
---|
| 480 | proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); |
---|
| 481 | proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); |
---|
| 482 | proc[p]->p_irq[0] (signal_proc_it[p]); |
---|
[695] | 483 | for ( size_t j = 1 ; j < 6 ; j++) { |
---|
[648] | 484 | proc[p]->p_irq[j] (signal_false); |
---|
| 485 | } |
---|
| 486 | } |
---|
[450] | 487 | |
---|
[648] | 488 | ///////////////////////////////////// XICU |
---|
| 489 | xicu->p_clk (this->p_clk); |
---|
| 490 | xicu->p_resetn (this->p_resetn); |
---|
| 491 | xicu->p_vci (signal_int_vci_tgt_xicu); |
---|
[695] | 492 | for ( size_t p = 0 ; p < NB_PROCS ; p++) { |
---|
[648] | 493 | xicu->p_irq[p] (signal_proc_it[p]); |
---|
| 494 | } |
---|
[695] | 495 | for ( size_t i=0 ; i<32 ; i++) { |
---|
| 496 | if ( is_iob0 ) |
---|
[648] | 497 | xicu->p_hwi[i] (*(this->p_irq[i])); |
---|
| 498 | else |
---|
| 499 | xicu->p_hwi[i] (signal_false); |
---|
| 500 | } |
---|
[450] | 501 | |
---|
[648] | 502 | ///////////////////////////////////// MEMC |
---|
| 503 | memc->p_clk (this->p_clk); |
---|
| 504 | memc->p_resetn (this->p_resetn); |
---|
| 505 | memc->p_vci_ixr (signal_ram_vci_ini_memc); |
---|
| 506 | memc->p_vci_tgt (signal_int_vci_tgt_memc); |
---|
| 507 | memc->p_dspin_p2m (signal_int_dspin_p2m_memc); |
---|
| 508 | memc->p_dspin_m2p (signal_int_dspin_m2p_memc); |
---|
| 509 | memc->p_dspin_clack (signal_int_dspin_clack_memc); |
---|
| 510 | memc->p_irq (signal_irq_memc); |
---|
[450] | 511 | |
---|
[648] | 512 | // wrapper to RAM network |
---|
| 513 | memc_ram_wi->p_clk (this->p_clk); |
---|
| 514 | memc_ram_wi->p_resetn (this->p_resetn); |
---|
| 515 | memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); |
---|
| 516 | memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); |
---|
| 517 | memc_ram_wi->p_vci (signal_ram_vci_ini_memc); |
---|
[450] | 518 | |
---|
[658] | 519 | //////////////////////////////////// BROM |
---|
| 520 | brom->p_clk (this->p_clk); |
---|
| 521 | brom->p_resetn (this->p_resetn); |
---|
| 522 | brom->p_vci (signal_int_vci_tgt_brom); |
---|
| 523 | |
---|
[695] | 524 | if (NB_DEBUG_TTY_CHANNELS) { |
---|
| 525 | //////////////////////////////////// MTTY |
---|
| 526 | mtty->p_clk (this->p_clk); |
---|
| 527 | mtty->p_resetn (this->p_resetn); |
---|
| 528 | mtty->p_vci (signal_int_vci_tgt_mtty); |
---|
| 529 | |
---|
| 530 | for ( size_t i=0 ; i < NB_DEBUG_TTY_CHANNELS ; i++ ) { |
---|
| 531 | mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
| 532 | } |
---|
| 533 | } |
---|
| 534 | |
---|
[648] | 535 | //////////////////////////////////// XRAM |
---|
| 536 | xram->p_clk (this->p_clk); |
---|
| 537 | xram->p_resetn (this->p_resetn); |
---|
| 538 | xram->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 539 | |
---|
[648] | 540 | // wrapper to RAM network |
---|
| 541 | xram_ram_wt->p_clk (this->p_clk); |
---|
| 542 | xram_ram_wt->p_resetn (this->p_resetn); |
---|
| 543 | xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); |
---|
| 544 | xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); |
---|
| 545 | xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); |
---|
[450] | 546 | |
---|
[648] | 547 | /////////////////////////////////// MDMA |
---|
| 548 | mdma->p_clk (this->p_clk); |
---|
| 549 | mdma->p_resetn (this->p_resetn); |
---|
| 550 | mdma->p_vci_target (signal_int_vci_tgt_mdma); |
---|
| 551 | mdma->p_vci_initiator (signal_int_vci_ini_mdma); |
---|
[695] | 552 | for (size_t i = 0 ; i < NB_DMA_CHANNELS ; i++) |
---|
[648] | 553 | mdma->p_irq[i] (signal_irq_mdma[i]); |
---|
[468] | 554 | |
---|
[648] | 555 | //////////////////////////// RAM network CMD & RSP routers |
---|
| 556 | ram_router_cmd->p_clk (this->p_clk); |
---|
| 557 | ram_router_cmd->p_resetn (this->p_resetn); |
---|
| 558 | ram_router_rsp->p_clk (this->p_clk); |
---|
| 559 | ram_router_rsp->p_resetn (this->p_resetn); |
---|
[695] | 560 | for( size_t n=0 ; n<4 ; n++) { |
---|
[648] | 561 | ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); |
---|
| 562 | ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); |
---|
| 563 | ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); |
---|
| 564 | ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); |
---|
| 565 | } |
---|
| 566 | ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); |
---|
| 567 | ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); |
---|
| 568 | ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); |
---|
| 569 | ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); |
---|
[450] | 570 | |
---|
[648] | 571 | ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. |
---|
[695] | 572 | if ( is_io_cluster ) { |
---|
[648] | 573 | // IO bridge |
---|
| 574 | iob->p_clk (this->p_clk); |
---|
| 575 | iob->p_resetn (this->p_resetn); |
---|
| 576 | iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); |
---|
| 577 | iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); |
---|
| 578 | iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); |
---|
| 579 | iob->p_vci_ini_int (signal_int_vci_ini_iobx); |
---|
| 580 | iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); |
---|
[450] | 581 | |
---|
[696] | 582 | if ( is_iob0 ) { |
---|
| 583 | for ( size_t n = 0 ; n < 32 ; n++ ) { |
---|
[648] | 584 | (*iob->p_irq[n]) (*(this->p_irq[n])); |
---|
[696] | 585 | } |
---|
| 586 | } |
---|
[450] | 587 | |
---|
[648] | 588 | // initiator wrapper to RAM network |
---|
| 589 | iob_ram_wi->p_clk (this->p_clk); |
---|
| 590 | iob_ram_wi->p_resetn (this->p_resetn); |
---|
| 591 | iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); |
---|
| 592 | iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); |
---|
| 593 | iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); |
---|
| 594 | } |
---|
| 595 | } // end constructor |
---|
[450] | 596 | |
---|
[695] | 597 | tmpl(/**/)::~TsarIobCluster() { |
---|
[648] | 598 | if (p_vci_iob_iox_ini) delete p_vci_iob_iox_ini; |
---|
| 599 | if (p_vci_iob_iox_tgt) delete p_vci_iob_iox_tgt; |
---|
| 600 | if (p_dspin_iob_cmd_out) delete p_dspin_iob_cmd_out; |
---|
| 601 | if (p_dspin_iob_rsp_in) delete p_dspin_iob_rsp_in; |
---|
| 602 | if (iob) delete iob; |
---|
| 603 | if (iob_ram_wi) delete iob_ram_wi; |
---|
[450] | 604 | |
---|
[695] | 605 | for (size_t n = 0 ; n < 32 ; n++) { |
---|
[648] | 606 | if (p_irq[n]) delete p_irq[n]; |
---|
| 607 | } |
---|
[450] | 608 | |
---|
[695] | 609 | for (size_t p = 0; p < NB_PROCS; p++) { |
---|
[648] | 610 | delete proc[p]; |
---|
| 611 | } |
---|
[450] | 612 | |
---|
[648] | 613 | delete memc; |
---|
| 614 | delete memc_ram_wi; |
---|
| 615 | delete xicu; |
---|
[658] | 616 | delete brom; |
---|
[695] | 617 | delete mtty; |
---|
[648] | 618 | delete mdma; |
---|
[696] | 619 | delete int_xbar_d; |
---|
[648] | 620 | delete int_xbar_m2p_c; |
---|
| 621 | delete int_xbar_p2m_c; |
---|
| 622 | delete int_xbar_clack_c; |
---|
| 623 | delete int_router_cmd; |
---|
| 624 | delete int_router_rsp; |
---|
| 625 | delete xram; |
---|
| 626 | delete xram_ram_wt; |
---|
| 627 | delete ram_router_cmd; |
---|
| 628 | delete ram_router_rsp; |
---|
| 629 | } |
---|
[450] | 630 | |
---|
| 631 | }} |
---|
| 632 | |
---|
| 633 | |
---|
| 634 | // Local Variables: |
---|
| 635 | // tab-width: 3 |
---|
| 636 | // c-basic-offset: 3 |
---|
| 637 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 638 | // indent-tabs-mode: nil |
---|
| 639 | // End: |
---|
| 640 | |
---|
| 641 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|
| 642 | |
---|